EP0480703A2 - Producing metal patterns on a substrate - Google Patents
Producing metal patterns on a substrate Download PDFInfo
- Publication number
- EP0480703A2 EP0480703A2 EP91309278A EP91309278A EP0480703A2 EP 0480703 A2 EP0480703 A2 EP 0480703A2 EP 91309278 A EP91309278 A EP 91309278A EP 91309278 A EP91309278 A EP 91309278A EP 0480703 A2 EP0480703 A2 EP 0480703A2
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- EP
- European Patent Office
- Prior art keywords
- metal
- layer
- substrate
- titanium
- depositing
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/22—Secondary treatment of printed circuits
- H05K3/225—Correcting or repairing of printed circuits
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- B—PERFORMING OPERATIONS; TRANSPORTING
- B23—MACHINE TOOLS; METAL-WORKING NOT OTHERWISE PROVIDED FOR
- B23K—SOLDERING OR UNSOLDERING; WELDING; CLADDING OR PLATING BY SOLDERING OR WELDING; CUTTING BY APPLYING HEAT LOCALLY, e.g. FLAME CUTTING; WORKING BY LASER BEAM
- B23K26/00—Working by laser beam, e.g. welding, cutting or boring
- B23K26/36—Removing material
- B23K26/40—Removing material taking account of the properties of the material involved
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01C—RESISTORS
- H01C17/00—Apparatus or processes specially adapted for manufacturing resistors
- H01C17/22—Apparatus or processes specially adapted for manufacturing resistors adapted for trimming
- H01C17/24—Apparatus or processes specially adapted for manufacturing resistors adapted for trimming by removing or adding resistive material
- H01C17/242—Apparatus or processes specially adapted for manufacturing resistors adapted for trimming by removing or adding resistive material by laser
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
- H01L21/4814—Conductive parts
- H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/02—Apparatus or processes for manufacturing printed circuits in which the conductive material is applied to the surface of the insulating support and is thereafter removed from such areas of the surface which are not intended for current conducting or shielding
- H05K3/027—Apparatus or processes for manufacturing printed circuits in which the conductive material is applied to the surface of the insulating support and is thereafter removed from such areas of the surface which are not intended for current conducting or shielding the conductive material being removed by irradiation, e.g. by photons, alpha or beta particles
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/02—Apparatus or processes for manufacturing printed circuits in which the conductive material is applied to the surface of the insulating support and is thereafter removed from such areas of the surface which are not intended for current conducting or shielding
- H05K3/06—Apparatus or processes for manufacturing printed circuits in which the conductive material is applied to the surface of the insulating support and is thereafter removed from such areas of the surface which are not intended for current conducting or shielding the conductive material being removed chemically or electrolytically, e.g. by photo-etch process
- H05K3/061—Etching masks
- H05K3/062—Etching masks consisting of metals or alloys or metallic inorganic compounds
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- B—PERFORMING OPERATIONS; TRANSPORTING
- B23—MACHINE TOOLS; METAL-WORKING NOT OTHERWISE PROVIDED FOR
- B23K—SOLDERING OR UNSOLDERING; WELDING; CLADDING OR PLATING BY SOLDERING OR WELDING; CUTTING BY APPLYING HEAT LOCALLY, e.g. FLAME CUTTING; WORKING BY LASER BEAM
- B23K2103/00—Materials to be soldered, welded or cut
- B23K2103/02—Iron or ferrous alloys
- B23K2103/04—Steel or steel alloys
- B23K2103/05—Stainless steel
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- B—PERFORMING OPERATIONS; TRANSPORTING
- B23—MACHINE TOOLS; METAL-WORKING NOT OTHERWISE PROVIDED FOR
- B23K—SOLDERING OR UNSOLDERING; WELDING; CLADDING OR PLATING BY SOLDERING OR WELDING; CUTTING BY APPLYING HEAT LOCALLY, e.g. FLAME CUTTING; WORKING BY LASER BEAM
- B23K2103/00—Materials to be soldered, welded or cut
- B23K2103/08—Non-ferrous metals or alloys
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- B—PERFORMING OPERATIONS; TRANSPORTING
- B23—MACHINE TOOLS; METAL-WORKING NOT OTHERWISE PROVIDED FOR
- B23K—SOLDERING OR UNSOLDERING; WELDING; CLADDING OR PLATING BY SOLDERING OR WELDING; CUTTING BY APPLYING HEAT LOCALLY, e.g. FLAME CUTTING; WORKING BY LASER BEAM
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- B23K2103/08—Non-ferrous metals or alloys
- B23K2103/12—Copper or alloys thereof
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- B—PERFORMING OPERATIONS; TRANSPORTING
- B23—MACHINE TOOLS; METAL-WORKING NOT OTHERWISE PROVIDED FOR
- B23K—SOLDERING OR UNSOLDERING; WELDING; CLADDING OR PLATING BY SOLDERING OR WELDING; CUTTING BY APPLYING HEAT LOCALLY, e.g. FLAME CUTTING; WORKING BY LASER BEAM
- B23K2103/00—Materials to be soldered, welded or cut
- B23K2103/08—Non-ferrous metals or alloys
- B23K2103/14—Titanium or alloys thereof
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- B—PERFORMING OPERATIONS; TRANSPORTING
- B23—MACHINE TOOLS; METAL-WORKING NOT OTHERWISE PROVIDED FOR
- B23K—SOLDERING OR UNSOLDERING; WELDING; CLADDING OR PLATING BY SOLDERING OR WELDING; CUTTING BY APPLYING HEAT LOCALLY, e.g. FLAME CUTTING; WORKING BY LASER BEAM
- B23K2103/00—Materials to be soldered, welded or cut
- B23K2103/08—Non-ferrous metals or alloys
- B23K2103/15—Magnesium or alloys thereof
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- B—PERFORMING OPERATIONS; TRANSPORTING
- B23—MACHINE TOOLS; METAL-WORKING NOT OTHERWISE PROVIDED FOR
- B23K—SOLDERING OR UNSOLDERING; WELDING; CLADDING OR PLATING BY SOLDERING OR WELDING; CUTTING BY APPLYING HEAT LOCALLY, e.g. FLAME CUTTING; WORKING BY LASER BEAM
- B23K2103/00—Materials to be soldered, welded or cut
- B23K2103/16—Composite materials, e.g. fibre reinforced
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- B—PERFORMING OPERATIONS; TRANSPORTING
- B23—MACHINE TOOLS; METAL-WORKING NOT OTHERWISE PROVIDED FOR
- B23K—SOLDERING OR UNSOLDERING; WELDING; CLADDING OR PLATING BY SOLDERING OR WELDING; CUTTING BY APPLYING HEAT LOCALLY, e.g. FLAME CUTTING; WORKING BY LASER BEAM
- B23K2103/00—Materials to be soldered, welded or cut
- B23K2103/16—Composite materials, e.g. fibre reinforced
- B23K2103/166—Multilayered materials
- B23K2103/172—Multilayered materials wherein at least one of the layers is non-metallic
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- B—PERFORMING OPERATIONS; TRANSPORTING
- B23—MACHINE TOOLS; METAL-WORKING NOT OTHERWISE PROVIDED FOR
- B23K—SOLDERING OR UNSOLDERING; WELDING; CLADDING OR PLATING BY SOLDERING OR WELDING; CUTTING BY APPLYING HEAT LOCALLY, e.g. FLAME CUTTING; WORKING BY LASER BEAM
- B23K2103/00—Materials to be soldered, welded or cut
- B23K2103/18—Dissimilar materials
- B23K2103/26—Alloys of Nickel and Cobalt and Chromium
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- B—PERFORMING OPERATIONS; TRANSPORTING
- B23—MACHINE TOOLS; METAL-WORKING NOT OTHERWISE PROVIDED FOR
- B23K—SOLDERING OR UNSOLDERING; WELDING; CLADDING OR PLATING BY SOLDERING OR WELDING; CUTTING BY APPLYING HEAT LOCALLY, e.g. FLAME CUTTING; WORKING BY LASER BEAM
- B23K2103/00—Materials to be soldered, welded or cut
- B23K2103/30—Organic material
- B23K2103/42—Plastics
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- B—PERFORMING OPERATIONS; TRANSPORTING
- B23—MACHINE TOOLS; METAL-WORKING NOT OTHERWISE PROVIDED FOR
- B23K—SOLDERING OR UNSOLDERING; WELDING; CLADDING OR PLATING BY SOLDERING OR WELDING; CUTTING BY APPLYING HEAT LOCALLY, e.g. FLAME CUTTING; WORKING BY LASER BEAM
- B23K2103/00—Materials to be soldered, welded or cut
- B23K2103/50—Inorganic material, e.g. metals, not provided for in B23K2103/02 – B23K2103/26
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- B—PERFORMING OPERATIONS; TRANSPORTING
- B23—MACHINE TOOLS; METAL-WORKING NOT OTHERWISE PROVIDED FOR
- B23K—SOLDERING OR UNSOLDERING; WELDING; CLADDING OR PLATING BY SOLDERING OR WELDING; CUTTING BY APPLYING HEAT LOCALLY, e.g. FLAME CUTTING; WORKING BY LASER BEAM
- B23K2103/00—Materials to be soldered, welded or cut
- B23K2103/50—Inorganic material, e.g. metals, not provided for in B23K2103/02 – B23K2103/26
- B23K2103/54—Glass
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/01—Dielectrics
- H05K2201/0104—Properties and characteristics in general
- H05K2201/0112—Absorbing light, e.g. dielectric layer with carbon filler for laser processing
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/03—Conductive materials
- H05K2201/0332—Structure of the conductor
- H05K2201/0335—Layered conductors or foils
- H05K2201/0338—Layered conductor, e.g. layered metal substrate, layered finish layer, layered thin film adhesion layer
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- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/20—Details of printed circuits not provided for in H05K2201/01 - H05K2201/10
- H05K2201/2081—Compound repelling a metal, e.g. solder
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- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
- H05K2203/03—Metal processing
- H05K2203/0361—Stripping a part of an upper metal layer to expose a lower metal layer, e.g. by etching or using a laser
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- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
- H05K2203/03—Metal processing
- H05K2203/0384—Etch stop layer, i.e. a buried barrier layer for preventing etching of layers under the etch stop layer
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- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
- H05K2203/17—Post-manufacturing processes
- H05K2203/173—Adding connections between adjacent pads or conductors, e.g. for modifying or repairing
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- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
- H05K2203/17—Post-manufacturing processes
- H05K2203/175—Configurations of connections suitable for easy deletion, e.g. modifiable circuits or temporary conductors for electroplating; Processes for deleting connections
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- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/10—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern
- H05K3/108—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern by semi-additive methods; masks therefor
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- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/10—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern
- H05K3/14—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern using spraying techniques to apply the conductive material, e.g. vapour evaporation
- H05K3/143—Masks therefor
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- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/38—Improvement of the adhesion between the insulating substrate and the metal
- H05K3/381—Improvement of the adhesion between the insulating substrate and the metal by special treatment of the substrate
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- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/38—Improvement of the adhesion between the insulating substrate and the metal
- H05K3/388—Improvement of the adhesion between the insulating substrate and the metal by the use of a metallic or inorganic thin film adhesion layer
Definitions
- the present invention relates to the fields of metal patterning and electronics, and more particularly, to the patterning of thin layers of metal.
- a common method of providing a circuit pattern is to form a layer of metal on an electrically insulating substrate, deposit a layer of photoresist over the the metal, pattern the photoresist photolithographically and etch the metal where it is not protected by the photoresist in order to leave the metal present in the pattern of the retained photoresist.
- This etching technique is limited in its inability to maintain very fine line lithography due to photoresist lift-off or deterioration, undercutting and other phenomena during etching.
- An alternative technique is to electroplate metal on the portions of the initial metal layer which are not covered by the photoresist. Such a plating process is normally completed by removing the remaining photoresist and etching away the initial metal layer with an etchant which does not attack the electroplated metal.
- the use of this plating technique to form gold, chrome or nickel electroplated conductors is normally ineffective because the electroplating bath attacks the photoresist vigorously causing deterioration and lift-off of the photoresist which results in plating in areas intended to be kept plating-free.
- a high density interconnect (HDI) structure or system which has been developed by General Electric Company requires patterning of metal conductors disposed on dielectric layers in order to form the interconnections among the integrated circuit chips of a system it is being used to interconnect.
- This high density interconnect structure offers many advantages in the compact assembly of electronic systems. For example, an electronic system such as a micro computer which incorporates 30-50 chips can be fully assembled and interconnected on a single substrate which is 2 inches long by 2 inches wide by .050 inch thick.
- a ceramic substrate such as alumina which may be 100 mils thick and of appropriate size and strength for the overall system, is provided. This size is typically less than 2 inches square, but.may be made larger or smaller.
- individual cavities or one large cavity having appropriate depth at the intended locations of differing chips is prepared. This may be done by starting with a bare substrate having a uniform thickness and the desired size. Conventional, ultrasonic or laser milling may be used to form the cavities in which the various chips and other components will be positioned. For many systems where it is desired to place chips nearly edge-to-edge, a single large cavity is satisfactory. That large cavity may typically have a uniform depth where the semiconductor chips have a substantially uniform thickness.
- the cavity bottom may be made respectively deeper or shallower to place the upper surface of the corresponding component in substantially the same plane as the upper surface of the rest of the components and the portion of the substrate which surrounds the cavity.
- the bottom of the cavity is then provided with a thermoplastic adhesive layer which may preferably be polyetherimide resin available under the trade name ULTEM® 6000 from the General Electric Company.
- the various components are then placed in their desired locations within the cavity, the entire structure is heated to about 300°C which is above the softening point of the ULTEM® polyetherimide (which is in the vicinity of 215°C) and then cooled to thermoplastically bond the individual components to the substrate.
- a polyimide film which may be Kapton® polyimide, available from E.I. du Pont de Nemours Company, which is ⁇ 0.0005-0.003 inch ( ⁇ 12.5-75 microns) thick is pretreated to promote adhesion by reactive ion etching (RIE).
- RIE reactive ion etching
- the substrate and chips are then coated with ULTEM® 1000 polyetherimide resin or another thermoplastic and the Kapton film is laminated across the top of the chips, any other components and the substrate with the ULTEM® resin serving as a thermoplastic adhesive to hold the Kapton® in place.
- via holes are provided (preferably by laser drilling) in the Kapton® and ULTEM® layers in alignment with the contact pads on the electronic components to which it is desired to make contact.
- a metallization layer which is deposited over the Kapton® layer extends into the via holes and makes electrical contact to the contact pads disposed thereunder.
- This metallization layer may be patterned to form individual conductors during the process of depositing it or may be deposited as a continuous layer and then patterned using photoresist and etching. The photoresist is preferably exposed using a laser to provide an accurately aligned conductor pattern at the end of the process. Additional dielectric and metallization layers are provided as required in order to provide all of the desired electrical connections among the chips.
- a primary object of the present invention is to provide an improved metal patterning technique which enables copper, gold, chrome and nickel patterns to be formed with high definition and reliability.
- Another object of the present invention is to provide an improved technique for producing high definition conductor patterns by patterned removal of a uniform conducting layer.
- Another object of the present invention is to provide a laser ablation technique for patterning conductive layers.
- Another object of the present invention is to provide a metal patterning,technique in which two layers of different metals burn off together during laser patterning.
- Another object of the present invention is to provide a laser metal patterning technique which is useful on high thermal conductivity substrates.
- Another object of the present invention is to provide a technique for repairing open conductors in printed circuit type structures including wafer scale integrated assemblies, high density interconnect structures and so forth.
- Another object of the present invention is to provide temporary connections for testing and other purposes in printed circuit type structures including wafer scale integrated assemblies, high density interconnect structure and so forth.
- Another object of the present invention is to provide improved adhesion of subsequently deposited dielectric layers to previously deposited dielectric layers by greatly increasing the surface area of the previously deposited dielectric layers.
- Another object of the present invention is to provide an improved technique for trimming passive components.
- a first layer of a thermally inefficient, reactive metal is deposited on an electrically insulating substrate and a second ultraviolet light absorbing metal is deposited on that first metal.
- the resulting structure is scanned with a UV laser having sufficient power to ablate the first and second metals together to remove them from the substrate in a pattern which is determined by the scanning pattern of the laser beam, while leaving them on the substrate elsewhere.
- the substrate is a polymer and the first layer is titanium or chrome and the second layer is copper, the portion of the polymer surface from which the metals were ablated is greatly roughened.
- a UV absorbing metal may be deposited directly on a thermally inefficient insulating substrate and laser ablated to provide the desired metal pattern, however, the resulting pattern is not as good.
- an initial layer of a thermally inefficient metal such as titanium, chrome, stainless steel and so forth is disposed on the substrate prior to deposition of a subsequent layer of UV absorbing mecal.
- This layer of thermally inefficient metal is made thick enough to cause the combined structure to act as a thermally inefficient substrate.
- the UV absorbing metal is then ablated from the surface of the thermally inefficient metal to create a metal pattern with good definition.
- the remaining portions of the second metal layer may then be used as a mask for etching those portions of the first metal which were exposed by the ablation of the second metal. Thereafter, the second metal may be retained or removed, as may be desired.
- a four layer metal structure may be deposited on a thermally conducting substrate with the third layer being thermally inefficient and the fourth layer being UV absorbing.
- the fourth layer is then patterned by scanning a laser across it. That fourth layer is then used as an etching mask for the third, thermally inefficient layer.
- the second layer and then the first layer may be etched to provide a conductor pattern of the second layer metal over first layer metal.
- the third layer is titanium, the remaining portions of the fourth layer may be removed and additional metal may be electroplated on the exposed portions of the second layer without plating on the titanium.
- a printed circuit having a break in an intended-to-be-continuous trace is repaired by depositing an thermally inefficient metal over the entire surface, depositing a UV absorbing metal over the first metal and then ablating the two deposited layers every place where conductors are not desired.
- the result is a bridging conductor which connects the two pieces of the trace across the unintended gap therein.
- an electrically insulating substrate 10 is shown in cross-section view. It is desired to form a conductor pattern on the upper surface of this substrate.
- This substrate may be glass, polymer materials or other relatively thermally inefficient materials.
- thermally inefficient we mean that the material is relatively slow to dissipate localized heat. In this sense, this substrate is distinct from such substrates as alumina and the high thermal conductivity metals such as copper which dissipate heat much more rapidly.
- the dividing line between thermally efficient and thermally inefficient materials is in part dependent on the energy of the laser beam used to pattern the metal.
- a first, layer of a thermally inefficient metal 22 is formed on the upper surface of the substrate 10 to provide the structure shown in Figure 2.
- This metal is preferably titanium, but may instead be chrome, nichrome, nickel, stainless steel, magnesium, manganese and so forth.
- This metal is deposited on the substrate under vacuum or other non-oxidizing conditions by any appropriate method, such as sputtering, thermal evaporation, chemical vapor deposition and so forth. We prefer to deposit this metal layer by sputtering. This layer is preferably from 500 to 1,000 ⁇ thick.
- a layer 24 of a UV absorbing metal which is preferably copper but may also be gold, is deposited on top of the layer 22 without breaking the vacuum in the deposition system to provide the structure illustrated in Figure 3.
- This copper layer may preferably be deposited to a depth in the range from 500-3,000 ⁇ . While thicker layers can be used where higher laser power is available, this thickness is adequate to the purpose, and effective with a laser power of 1-2 watts at 351-363 nm. Other wave lengths may be used with other metals having different absorption spectra.
- the substrate with its metal coating is mounted in a laser delivery system which is capable of scanning an intense UV light beam across the substrate.
- This oxidizing atmosphere may be air, air with additional oxygen added to it, pure oxygen, a chlorine containing atmosphere and so forth. We prefer to use air or air plus oxygen.
- the titanium and copper burn as they ablate with a sparkling effect similar to that of Fourth of July sparklers. This sparkling extends substantially above the surface of the metal 24.
- a beneficial side effect of this process where the substrate 10 is a polymer is that the portion of the polymer surface from which the metal is ablated becomes roughened with a surface characteristic which looks much like needles standing on their end.
- This roughened surface is a substantial advantage in a high density interconnect structure or other structure where a subsequent dielectric layer is later formed over the metal pattern and the exposed portions of the substrate 10.
- this is an adhesion promoting technique which can be applied to a polymer surface even where none of the deposited metal is to be retained on the polymer and its only function is to enable the roughening of the polymer surface during its ablation. This results in a greatly increased surface area.
- chrome used as the first or lower metal layer produces a similar sparkling and improvement in pattern definition.
- chrome used as the first or lower metal layer produces a similar sparkling and improvement in pattern definition.
- nickel, stainless steel, magnesium, manganese and similar metals which are or contain highly reactive elements will produce similar sparkling and improvement in pattern definition.
- a layer 32 of such a UV absorbing metal may be deposited directly on the substrate 10, as illustrated in Figure 6.
- the layer 32 is then patterned by use of laser ablation in the same manner as described above to selectively remove the metal 32 from the surface of the substrate 10 to produce the structure shown schematically in Figure 7.
- the resulting pattern is poorer and the substrate surface may remain conductive in the ablated regions where the substrate is a polymer.
- a thermally inefficient layer between the substrate and the ultraviolet absorbing metal in order to enable the laser ablation process to remove the UV absorbing metal.
- a layer 112 of a thermally inefficient metal is vacuum deposited on a thermally conducting substrate 100 to provide the structure illustrated in Figure 8.
- This thermally inefficient metal may be titanium, chromium, stainless steel (as a laminated layer) nichrome, magnesium, manganese or other metals or mixtures or alloys of metals which are thermally inefficient and sufficiently reactive.
- the layer 112 is made thick enough to render its upper surface thermally inefficient.
- the poor thermal efficiency of the layer 112 insulates an overlying layer from the thermal efficiency of the substrate 100.
- a layer 114 of UV absorbing metal is vacuum deposited on the thermally inefficient metal 112 without breaking the vacuum in the deposition apparatus to provide the structure shown in Figure 9.
- the upper metal layer 114 protects the lower metal layer 112 from oxidation and other chemical reactions.
- the metal 114 is then ablated by a laser beam 126 as illustrated in Figure 10. This removes the UV absorbing metal 114 in the laser scan pattern and may also remove part of but not all of the thermally inefficient metal 112.
- At least the lower portion of the thermally inefficient metal remains on the substrate because for a sufficiently thin layer of the thermally inefficient metal, the underlying substrate 100 carries heat away so rapidly that the thermally inefficient layer can not be heated to an ablation temperature.
- the retained portions of that upper metal layer may be used as a mask for chemically etching of the now exposed portions of the thermally inefficient metal 112 to leave portions 120 of the substrate surface metal-free. After such etching of the exposed portions of layer 112, the structure appears as shown in Figure 11.
- a four layer metal structure may be formed prior to laser ablation by successfully depositing titanium, copper, titanium and copper to provide a structure of the general type shown in Figure 12.
- These layers may be ⁇ 1000 ⁇ thick titanium, ⁇ 3000 ⁇ of deposited copper on which copper is electroplated to ⁇ 3mm thick, ⁇ 500-1000 ⁇ thick titanium and ⁇ 500-3000 ⁇ thick copper, respectively.
- the upper-most copper layer 118 may then be ablated from the upper surface of the upper titanium layer 116 to leave the copper in the desired pattern for the metallization as shown in Figure 13. This ablation is generally non-reactive in that no burning or sparkling occurs and none of the titanium appears to be removed during the ablation where the titanium layer is ⁇ 500-1000 ⁇ thick.
- the now exposed portions of the underlying titanium may then be etched with an HF-based etchant to expose the thick copper layer 114 as shown in Figure 14.
- This etchant needs to be one which etches titanium without etching copper.
- a copper etch then removes the exposed portions of the lower, thick copper layer 114 and the remaining portions of the upper, thin copper layer 118 to provide the structure shown in Figure 15.
- a final titanium etch removes the now exposed portions of the lower titanium layer 112 and the portions of the upper titanium layer 116 which protected the copper of the conductor runs during the etching of the thick copper layer 114. This results in the structure shown in Figure 16
- copper layer 114 may be left with a thickness of ⁇ 6000 ⁇ or so and the layers 116 and 118 deposited thereon.
- the process then follows that described above through the etching of the upper titanium layer 116.
- the retained portions of the upper copper layer 118 are removed from the surface of the titanium by a quick copper etch in ferric chloride which leaves the layer 114 of copper ⁇ 3000 ⁇ thick as shown in Figure 17.
- Titanium forms titanium oxide when exposed to air.
- the surface of the upper titanium layer 116 is coated with titanium oxide.
- the resulting titanium oxide layer is sufficiently electrically insulating to prevent electroplating on the titanium, that is, the titanium oxide coated titanium acts as a resist for electroplating.
- this structure may then be electroplated in a copper, gold, chrome or nickel electroplating bath to produce plated conductors having the pattern of the exposed copper 114 without depositing the copper gold, chrome or nickel 122 on the titanium portion of the structure as shown in Figure 18.
- This provides an effective method of forming gold, chrome or nickel plating on copper without the problems of photoresist lifting which have been experienced in the prior art.
- the surface titanium layer may be removed in a HF-based etchant, the portions of the lower copper layer 114 which are not protected by plated metal 122 may be removed in a ferric chloride etchant and the then unprotected portions of the lower titanium layer may be removed in a HF-based etchant.
- the substrate 200 may be a single layer of insulating material or may be a multilayer printed circuit structure (including high density interconnect structures) having an insulating upper surface on which the two portions 210 and 212 of an open trace are disposed with an unintended gap 214 therebetween.
- a first layer 222 of a thermally inefficient, reactive metal such as titanium is deposited over the entire upper surface of the substrate 200 and any conductors thereon.
- a second layer 224 of a UV absorbing metal such as copper is uniformly deposited over the upper surface.
- the entire upper surface of the substrate 200 is conductive.
- the deposited metals are then laser reactive ablated from those portions of the upper surface of the substrate 200 where conductors are not desired, but without ablating the portions of the deposited metals which bridge the gap 214 between the conductors 210 and 212.
- the retained portion of the deposited metals in the vicinity of the gap between the conductors 210 and 212 serve as a bridging conductor to close the gap, thereby repairing the structure as shown in Figure 22.
- This same technique can also be used to provide temporary connections for programming during testing or for other purposes. Such temporary connections can then be removed by etching or by further laser ablation.
- a resistor 310 is disposed on a substrate 300.
- a two layer metallization 320 is disposed on top of the resistor material as its contacts. These contacts can be initially patterned by photomasking and etching. These contacts are then laser ablated to increase the length of the current path through the resistor material between the two contacts to thereby increase the resistance exhibited by the resistor. Alternatively, all of the patterning of these contacts can be done by laser ablation.
Abstract
Description
- The present invention relates to the fields of metal patterning and electronics, and more particularly, to the patterning of thin layers of metal.
- In the electronic arts, a common method of providing a circuit pattern is to form a layer of metal on an electrically insulating substrate, deposit a layer of photoresist over the the metal, pattern the photoresist photolithographically and etch the metal where it is not protected by the photoresist in order to leave the metal present in the pattern of the retained photoresist. This etching technique is limited in its inability to maintain very fine line lithography due to photoresist lift-off or deterioration, undercutting and other phenomena during etching.
- An alternative technique is to electroplate metal on the portions of the initial metal layer which are not covered by the photoresist. Such a plating process is normally completed by removing the remaining photoresist and etching away the initial metal layer with an etchant which does not attack the electroplated metal. The use of this plating technique to form gold, chrome or nickel electroplated conductors is normally ineffective because the electroplating bath attacks the photoresist vigorously causing deterioration and lift-off of the photoresist which results in plating in areas intended to be kept plating-free.
- A high density interconnect (HDI) structure or system which has been developed by General Electric Company requires patterning of metal conductors disposed on dielectric layers in order to form the interconnections among the integrated circuit chips of a system it is being used to interconnect. This high density interconnect structure offers many advantages in the compact assembly of electronic systems. For example, an electronic system such as a micro computer which incorporates 30-50 chips can be fully assembled and interconnected on a single substrate which is 2 inches long by 2 inches wide by .050 inch thick.
- Briefly, in this high density interconnect structure, a ceramic substrate such as alumina which may be 100 mils thick and of appropriate size and strength for the overall system, is provided. This size is typically less than 2 inches square, but.may be made larger or smaller. Once the position of the various chips has been specified, individual cavities or one large cavity having appropriate depth at the intended locations of differing chips, is prepared. This may be done by starting with a bare substrate having a uniform thickness and the desired size. Conventional, ultrasonic or laser milling may be used to form the cavities in which the various chips and other components will be positioned. For many systems where it is desired to place chips nearly edge-to-edge, a single large cavity is satisfactory. That large cavity may typically have a uniform depth where the semiconductor chips have a substantially uniform thickness. Where a particularly thick or a particularly thin component will be placed, the cavity bottom may be made respectively deeper or shallower to place the upper surface of the corresponding component in substantially the same plane as the upper surface of the rest of the components and the portion of the substrate which surrounds the cavity. The bottom of the cavity is then provided with a thermoplastic adhesive layer which may preferably be polyetherimide resin available under the trade name ULTEM® 6000 from the General Electric Company. The various components are then placed in their desired locations within the cavity, the entire structure is heated to about 300°C which is above the softening point of the ULTEM® polyetherimide (which is in the vicinity of 215°C) and then cooled to thermoplastically bond the individual components to the substrate. Thereafter, a polyimide film which may be Kapton® polyimide, available from E.I. du Pont de Nemours Company, which is ≈0.0005-0.003 inch (≈12.5-75 microns) thick is pretreated to promote adhesion by reactive ion etching (RIE). The substrate and chips are then coated with ULTEM® 1000 polyetherimide resin or another thermoplastic and the Kapton film is laminated across the top of the chips, any other components and the substrate with the ULTEM® resin serving as a thermoplastic adhesive to hold the Kapton® in place. Thereafter, via holes are provided (preferably by laser drilling) in the Kapton® and ULTEM® layers in alignment with the contact pads on the electronic components to which it is desired to make contact. A metallization layer which is deposited over the Kapton® layer extends into the via holes and makes electrical contact to the contact pads disposed thereunder. This metallization layer may be patterned to form individual conductors during the process of depositing it or may be deposited as a continuous layer and then patterned using photoresist and etching. The photoresist is preferably exposed using a laser to provide an accurately aligned conductor pattern at the end of the process. Additional dielectric and metallization layers are provided as required in order to provide all of the desired electrical connections among the chips.
- Good adhesion of the metal conductors to the underlying dielectric and good adhesion of each dielectric layer to both the underlying metal and the underlying dielectric is necessary for proper fabrication of these high density interconnect circuits.
- This high density interconnect structure, methods of fabricating it and tools for fabricating it are disclosed in U.S. Patent 4,783,695, entitled "Multichip Integrated Circuit Packaging Configuration and Method" by C.W. Eichelberger, et al.; U.S. Patent 4,835,704, entitled "Adaptive Lithography System to Provide High Density Interconnect" by C.W. Eichelberger, et al.; U.S. Patent 4,714,516, entitled "Method to Produce Via Holes in Polymer Dielectrics for Multiple Electronic Circuit Chip Packaging" by C.W. Eichelberger, et al.; U.S. Patent 4,780,177, entitled "Excimer Laser Patterning of a Novel Resist" by R.J. Wojnarowski et al.; U.S. Patent Application Serial No. 249,927, filed September 27, 1989, entitled "Method and Apparatus for Removing Components Bonded to a Substrate" by R.J. Wojnarowski, et al.; U.S. Patent Application Serial No. 310,149, filed February 14, 1989, entitled "Laser Beam Scanning Method for Forming Via Holes in Polymer Materials" by C.W. Eichelberger, et al.; U.S. Patent Application Serial No. 312,798, filed February 21, 1989, entitled "High Density Interconnect Thermoplastic Die Attach Material and Solvent Die Attachment Processing" by R.J. Wojnarowski, et al.; U.S. Patent Application Serial No. 283,095, filed December 12, 1988, entitled "Simplified Method for Repair of High Density Interconnect Circuits" by C.W. Eichelberger, et al.; U.S. Patent Application Serial No. 305,314, filed February 3, 1989, entitled "Fabrication Process and Integrated Circuit Test Structure" by H.S. Cole, et al.; U.S. Patent Application Serial No. 250,010, filed September 27, 1988, entitled "High Density Interconnect With High Volumetric Efficiency" by C.W. Eichelberger, et al.; U.S. Patent Application Serial No. 329,478, filed March 28, 1989, entitled "Die Attachment Method for Use in High Density Interconnected Assemblies" by R.J. Wojnarowski, et al.; U.S. Patent Application Serial No. 253,020,filed October 4, 1988, entitled "Laser Interconnect Process" by H.S. Cole, et al.; U.S. Patent Application Serial No. 230,654, filed August 5, 1988, entitled "Method and Configuration for Testing Electronic Circuits and Integrated Circuit Chips Using a Removable Overlay Layer" by C.W. Eichelberger, et al.; U.S. Patent Application Serial No. 233,965, filed August 8, 1988, entitled "Direct Deposition of Metal Patterns for Use in Integrated Circuit Devices" by Y.S. Liu, et al.; U.S. Patent Application Serial No. 237,638, filed August 23, 1988, entitled "Method for Photopatterning Metallization Via UV Laser Ablation of the Activator" by Y.S. Liu, et al.; U.S. Patent Application Serial No. 237,685, filed August 25, 1988, entitled "Direct Writing of Refractory Metal Lines for Use in Integrated Circuit Devices" by Y.S. Liu, et al.; U.S. Patent Application Serial No. 240,367, filed August 30, 1988, entitled "Method and Apparatus for Packaging Integrated Circuit Chips Employing a Polymer film Overlay Layer" by C.W. Eichelberger, et al.; U.S. Patent Application Serial No. 342,153, filed April 24, 1989, entitled "Method of Processing Siloxane-Polyimides for Electronic Packaging Applications" by H.S. Cole, et al.; U.S. Patent Application Serial No. 289,944, filed December 27, 1988, entitled "Selective Electrolytic Deposition on Conductive and Non-Conductive Substrates" by Y.S. Liu, et al.; U.S. Patent Application Serial No. 312,536, filed february 17, 1989, entitled "Method of Bonding a Thermoset film to a Thermoplastic Material to Form a Bondable Laminate" by R.J. Wojnarowski; U.S. Patent Application Serial No. 363,646, filed June 8, 1989, entitled "Integrated Circuit Packaging Configuration for Rapid Customized Design and Unique Test Capability" by C.W. Eichelberger, et al.; U.S. Patent Application Serial No. 07/459,844, filed January 2, 1990, entitled "Area-Selective Metallization Process" by H.S. Cole, et al.; U.S. patent application Serial No. 361,623, filed June 5, 1989, entitled, "Adaptive Lithography Accommodation of Tolerances and Chip Positioning in High Density Interconnect Structures", by T.R. Haller; U.S. Patent Application Serial No. 07/457,023, filed December 26, 1989, entitled "Locally Orientation Specific Routing System" by T.R. Haller, et al.; U.S. Patent Application Serial No. 456,421, filed December 26, 1989, entitled "Laser Ablatable Polymer Dielectrics and Methods" by H.S. Cole, et al.; U.S. Patent Application Serial No. 454,546, filed December 21, 1989, entitled "Hermetic High Density Interconnected Electronic System" by W.P. Kornrumpf, et al.; U.S. Patent Application Serial No. 07/457,127, filed December 26, 1989, entitled "Enhanced Fluorescence Polymers and Interconnect Structures Using Them" by H.S. Cole, et al.; U.S. Patent Application Serial No. 454,545, filed December 21, 1989, entitled "An Epoxy/Polyimide Copolymer Blend Dielectric and Layered Circuits Incorporating It" by C.W. Eichelberger, et al.; Application Serial No. 07/504,760, filed April 5, 1990, entitled, "A Building Block Approach to Microwave Modules", by W. P. Kornrumpf et al.; Application Serial No. 07/504,821, filed April 5, 1990, entitled, "HDI Microwave Circuit Assembly", by W. P. Kornrumpf, et al.; Application Serial No. 07/504,750 filed April 5, 1990, entitled, "An Ultrasonic Array With a High Density of Electrical Connections", by L. S. Smith, et al.; Application Serial No. 07/504,803, filed April 5, 1990, entitled, "Microwave Component Test Method and Apparatus", by W. P. Kornrumpf, et al.; Application Serial No. 07/504,753, filed April 5, 1990, entitled, "A Compact High Density Interconnected Microwave System", by W. P. Kornrumpf; Application Serial No. 07/504,769, filed April 5, 1990, entitled, "A Flexible High Density Interconnect Structure and Flexibly Interconnected System" by C. W. Eichelberger, et al.; Application Serial No 07/504,751, filed April 5, 1990, entitled, "Compact, Thermally Efficient Focal Plane Array and Testing and Repair Thereof", by W. P. Kornrumpf, et al.; Application Serial No. 07/504,749, filed April 5, 1990, entitled, "High Density Interconnect Structure with Top Mounted Components", by R. J Wojnarowski, et al.; Application Serial No. 07/504,770, filed April 5, 1990, entitled, "A High Density Interconnect Structure Including a Chamber", by R. J. Wojnarowski, et al.; Application Serial No. 07/504,748, filed April 5, 1990, entitled, "Microwave Component Having Tailored Operating Characteristics and Method of Tailoring" by W. P. Kornrumpf, et al.; Application Serial No. 07/546,963, filed July 2, 1990, entitled "Multiple Lamination High Density Interconnect Process and Structure Employing Thermoplastic Adhesives having Sequentially Decreasing Tg's" by H.S. Cole et al.;
- Application Serial No.07/546,964, filed July 2, 1990, entitled "High Temperature Polyether Imide Compositions and Method of Making" by J.H. Lupinski et al.; Application Serial No.07/545,793, filed June 29,1990, entitled, "Adaptive Lithography in a High Density Interconnect Structure Whose Signal Layers Have Fixed Patterns" by T.R. Haller et al.;
- Application Serial No. 07/546,965, filed July 2, 1990, entitled "A High Density Interconnect Structure Including a Spacer Structure and a Gap", by H.S. Cole et al.; Application Serial No.07/546,959, filed July 2, 1990, entitled, "Multiple Lamination High Density Interconnect Process and Structure Employing a Variable Crosslinking Adhesive", by T.B.Gorczyca et al.; Application Serial No.07/546,230, filed June 29, 1990, entitled, "Method of Developing a Self-Developing Resist", by H.S. Cole, et al.; Application Serial No.07/546,960, filed July 2, 1990, entitled, "Multi-Sublayer Dielectric Layert, by H.S. Cole et al.; and Application Serial No.07/548,462, filed July 2, 1990, entitled, "Compact High Density Interconnect Structure", by W.M. Marcinkiewicz et al.. Each of these Patents and Patent Applications is incorporated herein by reference.
- There is a continuing need for improved metal patterning techniques and for enhanced inter-dielectric layer adhesion.
- Accordingly, a primary object of the present invention is to provide an improved metal patterning technique which enables copper, gold, chrome and nickel patterns to be formed with high definition and reliability.
- Another object of the present invention is to provide an improved technique for producing high definition conductor patterns by patterned removal of a uniform conducting layer.
- Another object of the present invention is to provide a laser ablation technique for patterning conductive layers.
- Another object of the present invention is to provide a metal patterning,technique in which two layers of different metals burn off together during laser patterning.
- Another object of the present invention is to provide a laser metal patterning technique which is useful on high thermal conductivity substrates.
- Another object of the present invention is to provide a technique for repairing open conductors in printed circuit type structures including wafer scale integrated assemblies, high density interconnect structures and so forth.
- Another object of the present invention is to provide temporary connections for testing and other purposes in printed circuit type structures including wafer scale integrated assemblies, high density interconnect structure and so forth.
- Another object of the present invention is to provide improved adhesion of subsequently deposited dielectric layers to previously deposited dielectric layers by greatly increasing the surface area of the previously deposited dielectric layers.
- Another object of the present invention is to provide an improved technique for trimming passive components.
- The above and other objects which will become apparent from the specification as a whole, including the drawings, are accomplished in accordance with the present invention by laser ablation of an ultraviolet light absorbing metal layer to define a metal pattern.
- In accordance with one embodiment, a first layer of a thermally inefficient, reactive metal is deposited on an electrically insulating substrate and a second ultraviolet light absorbing metal is deposited on that first metal. The resulting structure is scanned with a UV laser having sufficient power to ablate the first and second metals together to remove them from the substrate in a pattern which is determined by the scanning pattern of the laser beam, while leaving them on the substrate elsewhere. Where the substrate is a polymer and the first layer is titanium or chrome and the second layer is copper, the portion of the polymer surface from which the metals were ablated is greatly roughened. If a subsequent dielectric layer is formed on top of this roughened surface by applying a liquid precursor and drying or curing it, then adhesion between the two layers is greatly enhanced by a resulting interlocking of the newly deposited dielectric layer with the roughened surface of the substrate.
- In accordance with another embodiment, a UV absorbing metal may be deposited directly on a thermally inefficient insulating substrate and laser ablated to provide the desired metal pattern, however, the resulting pattern is not as good.
- In accordance with another embodiment, where the substrate is highly thermally conducting, an initial layer of a thermally inefficient metal such as titanium, chrome, stainless steel and so forth is disposed on the substrate prior to deposition of a subsequent layer of UV absorbing mecal. This layer of thermally inefficient metal is made thick enough to cause the combined structure to act as a thermally inefficient substrate. The UV absorbing metal is then ablated from the surface of the thermally inefficient metal to create a metal pattern with good definition. The remaining portions of the second metal layer may then be used as a mask for etching those portions of the first metal which were exposed by the ablation of the second metal. Thereafter, the second metal may be retained or removed, as may be desired.
- In accordance with another embodiment, a four layer metal structure may be deposited on a thermally conducting substrate with the third layer being thermally inefficient and the fourth layer being UV absorbing. The fourth layer is then patterned by scanning a laser across it. That fourth layer is then used as an etching mask for the third, thermally inefficient layer. The second layer and then the first layer may be etched to provide a conductor pattern of the second layer metal over first layer metal. When the third layer is titanium, the remaining portions of the fourth layer may be removed and additional metal may be electroplated on the exposed portions of the second layer without plating on the titanium.
- In accordance with another embodiment, a printed circuit having a break in an intended-to-be-continuous trace is repaired by depositing an thermally inefficient metal over the entire surface, depositing a UV absorbing metal over the first metal and then ablating the two deposited layers every place where conductors are not desired. The result is a bridging conductor which connects the two pieces of the trace across the unintended gap therein.
- The subject matter which is regarded as the invention is particularly pointed out and distinctly claimed in the concluding portion of the specification. The invention, however, both as to organization and method of practice, together with further objects and advantages thereof, may best be understood by reference to the following description taken in connection with the accompanying drawings in which:
- Figures 1-5 illustrate a sequence of stages in the production of a metal pattern in accordance with one embodiment of the invention;
- Figures 6 and 7 illustrate a sequence of steps in accordance with another embodiment of the invention;
- Figures 8-11 illustrate a sequence of stages in the fabrication of a pattern in accordance with another embodiment;
- Figures 12-16 illustrate stages in another embodiment;
- Figures 17-19 illustrate stages in an electroplating process;
- Figures 20-22 illustrate circuit repair;
- Figure 23 illustrates trimming of a resistor to adjust its resistance.
- In Figure 1, an electrically insulating
substrate 10 is shown in cross-section view. It is desired to form a conductor pattern on the upper surface of this substrate. This substrate may be glass, polymer materials or other relatively thermally inefficient materials. By thermally inefficient, we mean that the material is relatively slow to dissipate localized heat. In this sense, this substrate is distinct from such substrates as alumina and the high thermal conductivity metals such as copper which dissipate heat much more rapidly. The dividing line between thermally efficient and thermally inefficient materials is in part dependent on the energy of the laser beam used to pattern the metal. - As an initial step in the process of forming the conductor pattern, a first, layer of a thermally
inefficient metal 22 is formed on the upper surface of thesubstrate 10 to provide the structure shown in Figure 2. This metal is preferably titanium, but may instead be chrome, nichrome, nickel, stainless steel, magnesium, manganese and so forth. This metal is deposited on the substrate under vacuum or other non-oxidizing conditions by any appropriate method, such as sputtering, thermal evaporation, chemical vapor deposition and so forth. We prefer to deposit this metal layer by sputtering. This layer is preferably from 500 to 1,000Å thick. Subsequently, alayer 24 of a UV absorbing metal which is preferably copper but may also be gold, is deposited on top of thelayer 22 without breaking the vacuum in the deposition system to provide the structure illustrated in Figure 3. This copper layer may preferably be deposited to a depth in the range from 500-3,000Å. While thicker layers can be used where higher laser power is available, this thickness is adequate to the purpose, and effective with a laser power of 1-2 watts at 351-363 nm. Other wave lengths may be used with other metals having different absorption spectra. Next, the substrate with its metal coating is mounted in a laser delivery system which is capable of scanning an intense UV light beam across the substrate. We prefer to use an argon ion laser operating at 351 nm, but other frequencies may also be used. The laser is then scanned across the surface of themetal 24 in a pattern which corresponds to the areas in which metal is to be removed as illustrated in Figure 4. The copper absorbs roughly 60% of the UV light incident thereon and is heated to an ablation temperature. Direct ablation of the titanium itself without an overlying absorbing layer is not effective because titanium reflects about 81% of incident 351 nm light. However, there is sufficient thermal coupling between the copper and the titanium that the laser heating of the copper heats the underlying titanium to an ablation temperature which results in the two metals ablating off the substrate together. We prefer to perform this ablation process in an oxidizing atmosphere. This oxidizing atmosphere may be air, air with additional oxygen added to it, pure oxygen, a chlorine containing atmosphere and so forth. We prefer to use air or air plus oxygen. In this oxidizing atmosphere, the titanium and copper burn as they ablate with a sparkling effect similar to that of Fourth of July sparklers. This sparkling extends substantially above the surface of themetal 24. - With this process, we have obtained line spacings of from 2 to 500 microns, while retaining metal patterns of from 2 to 500 microns wide. Wider or narrower lines and spaces may be produced in accordance with the laser beam size and scanning pattern used for the ablation.
- A beneficial side effect of this process where the
substrate 10 is a polymer is that the portion of the polymer surface from which the metal is ablated becomes roughened with a surface characteristic which looks much like needles standing on their end. This is illustrated in Figure 5 where theportion 12 of thesubstrate surface 10 from which the metal was ablated has needle-like columns 14 extending roughly vertically. In many instances these columns are mushroom shaped with their upper end larger in cross section than their stem or shank. This roughened surface is a substantial advantage in a high density interconnect structure or other structure where a subsequent dielectric layer is later formed over the metal pattern and the exposed portions of thesubstrate 10. If that subsequent layer is formed by spinning on or spraying on a liquid precursor which is then converted to a solid dielectric in situ, greatly enhanced adhesion results from the infiltration of the subsequent dielectric layer into the gaps between theneedles 14 in the roughened surface of the substrate. This provides improved adhesion for a subsequently formed dielectric layer in two ways. First, it provides an increased contact surface area over which chemical adhesion is provided and second, it provides a rough surface which results in mechanical interlocking of the two layers which further increases the strength of the bond between the two layers. This mushroom shape of many of the needles further enhances mechanical interlocking of dielectric layers. As a consequence, use of this process to pattern conductor layers in multilayer structures provides additional benefits in providing a more rugged, more thoroughly bonded structure. Thus, this is an adhesion promoting technique which can be applied to a polymer surface even where none of the deposited metal is to be retained on the polymer and its only function is to enable the roughening of the polymer surface during its ablation. This results in a greatly increased surface area. - The combination of these two metals (copper over titanium) results in much sharper patterning than can be obtained with copper alone even where the substrate on which the copper alone is disposed is a substantially poorer thermal conductor than titanium. It is clear that the two metals interact during ablation in accordance with this invention. We therefore refer to this process as reactive ablation. When copper alone is used, no sparkling results, the line edge definition is much poorer and with a polymer substrate the surface of the polymer remains conductive as a result of some of the copper being left behind. It is believed that the copper which is left behind is actually driven into the surface of the polymer. Thus, use of copper alone results in inferior patterning and inferior surface properties for the resulting structure. As is mentioned above, if titanium alone is used, no ablation takes place at these laser powers because not enough energy is absorbed by the titanium to raise it to an ablation temperature. Thus, the combination of the two metals is necessary for high quality definition of the pattern and that high quality is a result of an unexpected interaction between the two metals during the ablation which results in reactive ablation. This interaction affects the removal of the metals themselves from the substrate, and thus is not a reaction which takes place only in the debris which has already left the surface of the substrate, but also involves the metals while they are still disposed on that surface. Since titanium is highly reactive and in the initial structure has been protected from oxidation by the deposition of the copper layer directly over the titanium without breaking the vacuum in the metal deposition system, it is thought that oxidation is taking place at the exposed edge of the titanium as the laser beam heats the copper which in turn heats the titanium. That oxidation then further heats the titanium resulting in the sparkling effect and the improved definition of the ablation pattern as compared to the pattern when copper alone is present. However, whether this is in fact the actual process is not known at this time. Further, the exact chemical and thermal processes going on is unimportant, since our work establishes that whatever processes are in fact taking place produce the beneficial effects of improved pattern definition, result in a non-conductive surface even on polymer substrates and on polymer substrates produce the needles-on-end surface pattern which greatly increases the exposed surface area of the polymer where the metals have been ablated.
- In addition to titanium, chrome used as the first or lower metal layer produces a similar sparkling and improvement in pattern definition. Nichrome, nickel, stainless steel, magnesium, manganese and similar metals which are or contain highly reactive elements will produce similar sparkling and improvement in pattern definition.
- In accordance with another embodiment of the invention, where the UV absorbing metal will adhere to a desired, thermally inefficient substrate without need for an adhesion promoting layer, a
layer 32 of such a UV absorbing metal may be deposited directly on thesubstrate 10, as illustrated in Figure 6. Thelayer 32 is then patterned by use of laser ablation in the same manner as described above to selectively remove themetal 32 from the surface of thesubstrate 10 to produce the structure shown schematically in Figure 7. However, as has been discussed, the resulting pattern is poorer and the substrate surface may remain conductive in the ablated regions where the substrate is a polymer. - Where it is desired to form a metal pattern on a highly thermally conducting substrate such as alumina or a high thermal conductivity metal, the process described above must include the provision of a thermally inefficient layer between the substrate and the ultraviolet absorbing metal in order to enable the laser ablation process to remove the UV absorbing metal. To this end, a
layer 112 of a thermally inefficient metal is vacuum deposited on a thermally conductingsubstrate 100 to provide the structure illustrated in Figure 8. This thermally inefficient metal may be titanium, chromium, stainless steel (as a laminated layer) nichrome, magnesium, manganese or other metals or mixtures or alloys of metals which are thermally inefficient and sufficiently reactive. Thelayer 112 is made thick enough to render its upper surface thermally inefficient. That is, the poor thermal efficiency of thelayer 112 insulates an overlying layer from the thermal efficiency of thesubstrate 100. Thereafter, alayer 114 of UV absorbing metal is vacuum deposited on the thermallyinefficient metal 112 without breaking the vacuum in the deposition apparatus to provide the structure shown in Figure 9. Theupper metal layer 114 protects thelower metal layer 112 from oxidation and other chemical reactions. Themetal 114 is then ablated by alaser beam 126 as illustrated in Figure 10. This removes theUV absorbing metal 114 in the laser scan pattern and may also remove part of but not all of the thermallyinefficient metal 112. At least the lower portion of the thermally inefficient metal remains on the substrate because for a sufficiently thin layer of the thermally inefficient metal, theunderlying substrate 100 carries heat away so rapidly that the thermally inefficient layer can not be heated to an ablation temperature. After the ablative patterning of the UV absorbingmetal layer 114, the retained portions of that upper metal layer may be used as a mask for chemically etching of the now exposed portions of the thermallyinefficient metal 112 to leave portions 120 of the substrate surface metal-free. After such etching of the exposed portions oflayer 112, the structure appears as shown in Figure 11. - As an alternative to employing the just described two layer metal structure, a four layer metal structure may be formed prior to laser ablation by successfully depositing titanium, copper, titanium and copper to provide a structure of the general type shown in Figure 12. These layers may be ∼1000Å thick titanium, ∼3000Å of deposited copper on which copper is electroplated to ∼3mm thick, ∼500-1000Å thick titanium and ∼500-3000Å thick copper, respectively. The
upper-most copper layer 118 may then be ablated from the upper surface of theupper titanium layer 116 to leave the copper in the desired pattern for the metallization as shown in Figure 13. This ablation is generally non-reactive in that no burning or sparkling occurs and none of the titanium appears to be removed during the ablation where the titanium layer is ∼500-1000Å thick. However, excellent patterning is obtained. This is believed to be in part a result of the impervious nature of the titanium layer. The now exposed portions of the underlying titanium may then be etched with an HF-based etchant to expose thethick copper layer 114 as shown in Figure 14. This etchant needs to be one which etches titanium without etching copper. A copper etch then removes the exposed portions of the lower,thick copper layer 114 and the remaining portions of the upper,thin copper layer 118 to provide the structure shown in Figure 15. A final titanium etch removes the now exposed portions of thelower titanium layer 112 and the portions of theupper titanium layer 116 which protected the copper of the conductor runs during the etching of thethick copper layer 114. This results in the structure shown in Figure 16 - Alternatively, rather than electroplating the
first copper layer 114 to thicken it, thatcopper layer 114 may be left with a thickness of ∼6000Å or so and thelayers upper titanium layer 116. Then the retained portions of theupper copper layer 118 are removed from the surface of the titanium by a quick copper etch in ferric chloride which leaves thelayer 114 of copper ∼3000Å thick as shown in Figure 17. Titanium forms titanium oxide when exposed to air. As a result, the surface of theupper titanium layer 116 is coated with titanium oxide. The resulting titanium oxide layer is sufficiently electrically insulating to prevent electroplating on the titanium, that is, the titanium oxide coated titanium acts as a resist for electroplating. Thus, this structure may then be electroplated in a copper, gold, chrome or nickel electroplating bath to produce plated conductors having the pattern of the exposedcopper 114 without depositing the copper gold, chrome ornickel 122 on the titanium portion of the structure as shown in Figure 18. This provides an effective method of forming gold, chrome or nickel plating on copper without the problems of photoresist lifting which have been experienced in the prior art. Following this plating operation, the surface titanium layer may be removed in a HF-based etchant, the portions of thelower copper layer 114 which are not protected by platedmetal 122 may be removed in a ferric chloride etchant and the then unprotected portions of the lower titanium layer may be removed in a HF-based etchant. The result is the structure illustrated in Figure 19 in which electroplated copper, gold, chrome or nickel conductors are provided. While this process is highly effective for copper electroplating, its benefits are more pronounced for gold, chromium and nickel electroplating because copper plating baths attack photoresist much more slowly than gold, chromium and nickel electroplating baths do with the result that prior electroplating of copperhas been much more successful than prior art electroplating of gold, chromium and nickel. - This metal deposition and ablation technique is also suitable for repairing open conductors in printed circuit type structures such as printed circuit boards, VLSI integrated circuits, wafer scale integrated structures, high density interconnect structures and so forth. Such a printed circuit is shown in perspective view in Figure 20. The
substrate 200 may be a single layer of insulating material or may be a multilayer printed circuit structure (including high density interconnect structures) having an insulating upper surface on which the twoportions unintended gap 214 therebetween. Where thegap 214 between theconductors conductors - To effect a repair of this open trace, a
first layer 222 of a thermally inefficient, reactive metal such as titanium is deposited over the entire upper surface of thesubstrate 200 and any conductors thereon. Subsequently, asecond layer 224 of a UV absorbing metal such as copper is uniformly deposited over the upper surface. At this stage, as shown in Figure 21, the entire upper surface of thesubstrate 200 is conductive. The deposited metals are then laser reactive ablated from those portions of the upper surface of thesubstrate 200 where conductors are not desired, but without ablating the portions of the deposited metals which bridge thegap 214 between theconductors conductors - This same technique can also be used to provide temporary connections for programming during testing or for other purposes. Such temporary connections can then be removed by etching or by further laser ablation.
- This technique is also useful for trimming resistors. In Figure 23, a
resistor 310 is disposed on asubstrate 300. A twolayer metallization 320 is disposed on top of the resistor material as its contacts. These contacts can be initially patterned by photomasking and etching. These contacts are then laser ablated to increase the length of the current path through the resistor material between the two contacts to thereby increase the resistance exhibited by the resistor. Alternatively, all of the patterning of these contacts can be done by laser ablation. - While the invention has been described in detail herein in accord with certain preferred embodiments thereof, many modifications and changes therein may be effected by those skilled in the art. Accordingly, it is intended by the appended claims to cover all such modifications and changes as fall within the true spirit and scope of the invention.
Claims (23)
- A method of producing a desired metal pattern on a surface of a thermally inefficient substrate comprising:
depositing a layer of a first metal on said substrate;
depositing a layer of a second, ultraviolet light absorbing metal on said first metal;
exposing said second metal to intense ultraviolet light in accordance with said desired pattern to ablate said first and second metals from said substrate together. - The method recited in claim 1 wherein:
said first metal is selected from the group consisting of titanium, chromium, magnesium, manganese, nichrome and stainless steel and alloys and mixtures thereof; and
said second metal is selected from the group consisting of copper and gold and alloys and mixtures thereof. - The method recited in claim 1 further comprising:
etching those portions of said substrate from which said first and second metals were ablated. - The method recited in claim 1 wherein said substrate is electrically conducting, said first metal is titanium and said method further comprises, after the exposing step, the step of:
removing said second metal from said titanium;
allowing the then exposed titanium to form a surface coating of titanium oxide; and
electroplating said substrate to build up electroplated metal in those areas from which said metals were ablated without building up electroplated metal on said titanium. - A method of producing a metal pattern on a surface of a thermally inefficient substrate comprising:
depositing a layer of ultraviolet light absorbing metal on said substrate;
exposing said metal to intense ultraviolet light in the inverse of said pattern to ablate said metal from said substrate. - The method recited in claim 5 wherein:
said metal is selected from the group consisting of copper and gold. - A method of producing a metal pattern on a surface of a high thermal conductivity substrate comprising:
depositing a layer of a first thermally inefficient metal on said substrate, said layer being thick enough to render the resulting surface thermally inefficient;
depositing a layer of a second, ultraviolet light absorbing metal on said first metal;
exposing said second metal to intense ultraviolet light in the inverse of said pattern to ablate said second metal from said first metal. - The method recited in claim 7 wherein:
said first metal is selected from the group consisting of titanium, chromium, magnesium, manganese, nichrome and stainless steel; and
said second metal is selected from the group consisting of copper and gold. - The method recited in claim 2 or 8 wherein:
said substrate is disposed in an oxidizing atmosphere during said exposing step. - The method recited in claim 9 wherein:
said first and second metals burn off the substrate together during said exposing step. - The method recited in claim 2 or 10 wherein:
said oxidizing atmosphere comprises air. - The method recited in claim 9 wherein:
said oxidizing atmosphere comprises oxygen. - The method recited in claim 8 further comprising:
etching exposed portions of said first metal with an etchant which does not attack said second metal. - The method recited in claim 7 wherein said substrate is electrically conducting, said first metal is titanium and said method further comprises, after the step of exposing, the step of:
selectively removing said second metal from said titanium;
allowing the then exposed titanium to form a surface coating of titanium oxide; and
electroplating said substrate to build up electroplated metal in those areas from which said metals were ablated without building up electroplated metal on said titanium. - The method recited in claim 1, 5, 7, 9 or 12 wherein the step of exposing comprises:
scanning an ultraviolet laser beam across said substrate. - A method of producing a metal pattern on a surface of a high thermal conductivity substrate comprising:
depositing a first layer of a metal on said substrate,
depositing a second layer of a metal on said first layer of metal;
depositing a third layer of a thermally inefficient metal on said second layer of metal, said layer being thick enough to render the resulting surface thermally inefficient;
depositing a fourth layer of an ultraviolet light absorbing metal on said third layer of metal;
exposing said fourth layer of metal to intense ultraviolet light in the inverse of said pattern to ablate said fourth layer of metal from the surface of said third layer of metal. - The method recited in claim 16 further comprising the step of:
etching exposed portions of said third layer of metal with an etchant to which said fourth layer of metal is substantially immune to pattern said third layer of metal. - The method recited in claim 17 further comprising the step of:
etching exposed portions of said second layer of metal with an etchant to which said third layer of metal is substantially immune. - The method recited in claim 19 further comprising the step of:
etching exposed portions of said first layer of metal in an etchant to which said second layer of metal is substantially immune. - The method recited in claim 16 wherein:
said first and third layers comprise titanium; and
said second and fourth layers comprise copper. - A method of increasing the surface area of a polymer comprising:
depositing a first layer of metal selected from the group consisting of titanium, chromium, nichrome, stainless steel, magnesium and manganese and alloys and mixtures thereof on said polymer;
depositing a second layer of metal selected from the group consisting of copper and gold and alloys and mixtures thereof on saidfirst layer of metal;
laser ablating said second and first metal layers together in an oxidizing atmosphere under conditions in which said first layer of metal burns off to leave said polymer with a structured surface. - A method of repairing a broken trace in a printed circuit comprising:
depositing a layer of a first metal on said printed circuit, in ohmic contact with both pieces of said trace and the across the gap between them;
depositing a layer of a second, ultraviolet light absorbing, metal on said first metal;
laser ablating said first and second metals from said printed circuit while leaving said metals in ohmic contact with both pieces of said broken circuit trace and continuous therebetween to leave said first and second metals as a conducting bridge connecting the two pieces of said broken trace. - A method of trimming a resistor comprising:
depositing a layer of a first metal on said resistor;
depositing a layer of a second, ultraviolet light absorbing, metal on said first metal;
laser ablating said first and second metals together from said resistor in a pattern to provide said resistor with a desired resistance.
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US597255 | 1990-10-12 | ||
US07/597,255 US5104480A (en) | 1990-10-12 | 1990-10-12 | Direct patterning of metals over a thermally inefficient surface using a laser |
Publications (3)
Publication Number | Publication Date |
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EP0480703A2 true EP0480703A2 (en) | 1992-04-15 |
EP0480703A3 EP0480703A3 (en) | 1992-06-03 |
EP0480703B1 EP0480703B1 (en) | 1997-03-26 |
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---|---|---|---|
EP91309278A Expired - Lifetime EP0480703B1 (en) | 1990-10-12 | 1991-10-09 | Producing metal patterns on a substrate |
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US (1) | US5104480A (en) |
EP (1) | EP0480703B1 (en) |
JP (1) | JP3338465B2 (en) |
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Publication number | Priority date | Publication date | Assignee | Title |
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US10537027B2 (en) | 2013-08-02 | 2020-01-14 | Orbotech Ltd. | Method producing a conductive path on a substrate |
EP2887418A1 (en) * | 2013-12-19 | 2015-06-24 | The Swatch Group Research and Development Ltd. | Cell with non-conducting structured surface |
US9842740B2 (en) | 2014-08-29 | 2017-12-12 | Seagate Technology Llc | Ablation for feature recovery |
KR101810815B1 (en) * | 2017-04-07 | 2017-12-20 | 김병삼 | Manufacturing method of sensor cover penetrating electronic signal having micro crack and laser hole |
DE102018115205A1 (en) | 2018-06-25 | 2020-01-02 | Vishay Electronic Gmbh | Process for manufacturing a large number of resistance units |
CN111343793A (en) * | 2020-03-12 | 2020-06-26 | 电子科技大学 | Surface metallization method for printed circuit composite dielectric substrate |
Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
EP0180101A2 (en) * | 1984-11-01 | 1986-05-07 | International Business Machines Corporation | Deposition of patterns using laser ablation |
US4786358A (en) * | 1986-08-08 | 1988-11-22 | Semiconductor Energy Laboratory Co., Ltd. | Method for forming a pattern of a film on a substrate with a laser beam |
US4826785A (en) * | 1987-01-27 | 1989-05-02 | Inmos Corporation | Metallic fuse with optically absorptive layer |
Family Cites Families (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US3867217A (en) * | 1973-10-29 | 1975-02-18 | Bell Telephone Labor Inc | Methods for making electronic circuits |
DE2521543A1 (en) * | 1974-05-16 | 1975-11-27 | Crosfield Electronics Ltd | METHOD AND DEVICE FOR REPRODUCING IMAGES |
US4259433A (en) * | 1976-10-22 | 1981-03-31 | Fuji Photo Film Co., Ltd. | Method for producing disk-recording plates |
US4713518A (en) * | 1984-06-08 | 1987-12-15 | Semiconductor Energy Laboratory Co., Ltd. | Electronic device manufacturing methods |
-
1990
- 1990-10-12 US US07/597,255 patent/US5104480A/en not_active Expired - Lifetime
-
1991
- 1991-10-03 JP JP28202991A patent/JP3338465B2/en not_active Expired - Fee Related
- 1991-10-09 DE DE69125333T patent/DE69125333T2/en not_active Expired - Fee Related
- 1991-10-09 EP EP91309278A patent/EP0480703B1/en not_active Expired - Lifetime
Patent Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
EP0180101A2 (en) * | 1984-11-01 | 1986-05-07 | International Business Machines Corporation | Deposition of patterns using laser ablation |
US4786358A (en) * | 1986-08-08 | 1988-11-22 | Semiconductor Energy Laboratory Co., Ltd. | Method for forming a pattern of a film on a substrate with a laser beam |
US4826785A (en) * | 1987-01-27 | 1989-05-02 | Inmos Corporation | Metallic fuse with optically absorptive layer |
Non-Patent Citations (3)
Title |
---|
D. B[UERLE:"Chemical Processing with LASERs", Springerverlag,1986,ISBN 3-540-17 147-9, pp.162-170 * |
EDN ELECTRICAL DESIGN NEWS. vol. 17, no. 13, 1 July 1972, NEWTON, MASSACHUSETTS US page 14; 'Circuits Formed on Ceramic Substrates with Laser "Machining" Process' * |
IBM TECHNICAL DISCLOSURE BULLETIN. vol. 8, no. 12, May 1966, NEW YORK US page 1733; H.L. CASWELL: 'Electroforming Film Patterns for Interconnections' * |
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FR2795907A1 (en) * | 1999-07-01 | 2001-01-05 | Gemplus Card Int | PROCESS FOR THE MANUFACTURE AND TESTING OF ELECTRONIC MICROMODULAS, IN PARTICULAR FOR CHIP CARDS |
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US6571468B1 (en) | 2001-02-26 | 2003-06-03 | Saturn Electronics & Engineering, Inc. | Traceless flip chip assembly and method |
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US6846701B2 (en) | 2001-02-26 | 2005-01-25 | Saturn Electronics & Engineering, Inc. | Traceless flip chip assembly and method |
US6866758B2 (en) | 2002-03-21 | 2005-03-15 | Roche Diagnostics Corporation | Biosensor |
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US7185428B2 (en) | 2002-09-23 | 2007-03-06 | International Business Machines Corporation | Method of making a circuitized substrate |
US7325299B2 (en) | 2002-09-23 | 2008-02-05 | International Business Machines Corporation | Method of making a circuitized substrate |
US7596862B2 (en) | 2002-09-23 | 2009-10-06 | International Business Machines Corporation | Method of making a circuitized substrate |
JP2007524076A (en) * | 2003-06-20 | 2007-08-23 | エフ ホフマン−ラ ロッシュ アクチェン ゲゼルシャフト | Biosensor and fabrication method |
WO2006136319A1 (en) * | 2005-06-21 | 2006-12-28 | Hansgrohe Ag | Method for producing decorative surface structures |
EP1742290A1 (en) * | 2005-07-04 | 2007-01-10 | Samsung Electronics Co., Ltd. | Embedded type antenna pattern for portable terminal and method for manufacturing same |
US10913064B2 (en) | 2014-04-16 | 2021-02-09 | Abbott Laboratories | Droplet actuator fabrication apparatus, systems, and related methods |
EP2940528A1 (en) * | 2014-04-30 | 2015-11-04 | Wistron Neweb Corporation | Method of fabricating substrate structure and substrate structure fabricated by the same method |
US10369565B2 (en) | 2014-12-31 | 2019-08-06 | Abbott Laboratories | Digital microfluidic dilution apparatus, systems, and related methods |
US11213817B2 (en) | 2014-12-31 | 2022-01-04 | Abbott Laboratories | Digital microfluidic dilution apparatus, systems, and related methods |
Also Published As
Publication number | Publication date |
---|---|
US5104480A (en) | 1992-04-14 |
JPH04280494A (en) | 1992-10-06 |
EP0480703B1 (en) | 1997-03-26 |
JP3338465B2 (en) | 2002-10-28 |
EP0480703A3 (en) | 1992-06-03 |
DE69125333D1 (en) | 1997-04-30 |
DE69125333T2 (en) | 1997-10-02 |
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