EP0321493A1 - A content-addressable memory system - Google Patents

Abstract

An associative memory system (62) for connection to a host computer equipped with a host memory (66, 68) storing a plurality of records and a host processor bus (72), includes a memory unit index used to store a matrix of bitmap graphics representative of the records stored in the host computer (60), said memory unit (74) being connected during use to the host processor bus (72) and being addressable by the host computer (60). The associative memory system also includes an index processor (76) allowing access to the bitmap graphics stored in the memory unit (74) and performing bitmap graphics operations on the bitmap graphics, the index processor (76) being connected in use to the host processor bus (72) and being controlled by the host computer (60). The associative memory system further includes a memory system bus (78) connected between the index memory unit (74) and the index processor (76), the bus (78) being adapted to pass through. bitmap graphics between the memory unit (74) and the processor (76).

Description

A CONTENT-ADDRESSABLE MEMORY SYSTEM

The present invention relates to a content-addressable memory system. The present invention also relates an active memory circuit and a content-addressable memory system including one or more of the active memory circuits.

In computer systems which store a large amount of data in record form, where each each record includes a number of attributes or pieces of info_rmation, conducting a search of the records in order to find those records which have a particular attribute involves a considerable amount of computer time if each detailed record is accessed on the basis of its storage location only. This problem is enhanced if the records are stored in a remote storage location, such as on disc.

One way of alleviating this problem is to store the records in such a way that it is possible to access the records on the basis of their attributes or contents. This type of memory system is known as a co tent-addressable memory system and one way of implementing it is to encode a file of records so as to form a bit map matrix on which searches are carried out so as to find records which satisfy a particular query.

The bit map matrix comprises an array of bits in which each row represents a particular record and each column is known as a bit map. Depending on the form of encoding used, each bit in a row usually represents a predetermined attribute of the respective record. If the bit is high the record possesses the attribute and if the bit is low the record does not possess the attribute. Hence, each bit map provides an indication of which records possess a particular attribute and which records do not.

A complex query, such as which records possess particular combination of attributes, is solved by performing a logic operation or a series of logic operations on selected bit maps which correspond to the query so as to generate a bit map which provides <_n indication as to which records satisfy the query.

An object of the present invention is to provide a content-addressable memory system for use with a host computer and which is relatively inexpensive and enables searches to be carried out on records at a relatively fast rate, particularly with respect to the rate at which searches would be carried out by the host computer without the memory system. A further object of the present invention is to provide an active memory circuit which is capable of carrying out logic operations on a bit map matrix.

Another object of the present invention is to provide a content-addressable memory system which includes one or more of the active memory circuits.

In accordance with the present invention there is provided a content-addressable memory system for connection to a host computer having a host memory storing a plurality of records and a host processor bus, said memory system comprising: index memory means for storing a bit map matrix representative of records stored in said host computer, said memory means, being, in use, connected to said host processor bus'and addressable by said host computer; index processor means for accessing bit maps stored in said memory means and performing bit map operations on said bit maps, said index processor means being, in use, connected to said host processor bus and controlled by said host computer; and a memory system bus connected between said index memory means and said index processor means, said bus being adapted to pass bit maps between said memory means and said processor means.

Preferably the index memory means comprises a plurality of index memories which each include: an array of memory cells; and a shift register having a parallel input/output bus connected to said array, and a serial input port and a serial ouput port at opposite ends of said shift register, said parallel input/ouput bus being capable of accessing a selected row of data in said array; said memory system bus connects the serial input and output ports of the index memories in parallel to said index processor means; and said selected rows of data accessed simultaneously form at least one bit map.

In accordance with the present invention there is also provided an active memory circuit comprising: an array of memory cells arranged in rows and columns adapted to store at least part of a bit map; a shift register adapted to store at least part of a bit map; and

^* a logic unit connected between said array and said shift register; said array, shift register and logic unit comprising an integrated circuit and said shift register being able to copy a selected column of said array and said logic unit being able to perform a selected logic operation on the contents of said shift register and a selected column of said array, the result of said operation being stored in said shift register.

In accordance with the present invention there is also provided a content-addressable memory as defined above including one or more active memories as defined above.

Preferred embodiments of the present invention will now be described, by way of example only, with reference to the accompany drawings wherein:

Figure 1 is a diagram of an array of records and a bit map corresponding to a query made on the array of records;

Figure 2 is a diagram of a plurality of bit maps representing records responding to a plurality of constituent queries which generate a bit map responding to a complex query;

Figure 3 is a diagram of a bit map matrix containing a superimposed coding index to an array of records;

Figure 4 is a diagram of bit maps representing a boolean attribute;

Figure 5 is a diagram of a bit map matrix search involving logic operations on a binary encoded attribute;

Figure 6 is a diagram of a greater than/less than split performed on a bit map matrix and includes a listing of an algorithm to perform the split;

Figure 7 is a diagram illustrating how a minimum of a bit map matrix is found and includes a listing of an algorithm to determine the minimum;

Figure 8 is a block diagram of a memory system according to the present invention attached to a host computer; Figure 9 is a diagram showing the arrangement of memory in the system of Figure 8;

Figure 10 is a further diagram of showing the arrangement of memory in the system of Figure 8;

Figure 11 is a diagram illustrating bit map operations which the system of Figure 8 can perform;

Figure 12 is a diagram of a memory chip of the system of Figure 8;

Figure 13 is a diagram of a memory unit of the system of Figure 8;

Figure 14 is a diagram of an index processor of the system of Figure 8;

Figure 15 is a diagram of data flow in the system of Figure 8;

Figure 16 is a block diagram of an active memory circuit according to the present system;

« Figure 17 is a more detailed block diagram of the circuit of Figure 16;

Figure 18 is a circuit diagram of a shift register cell and a logic cell of the circuit of Figure 16;

Figure 19 is a diagram of indexing memory system architecture employing the active memory of Figure 16;

Figure 20 is a diagram of a superimposed code word calculation unit;

Figure 21 is a diagram of a unit to determine and store the addresses of responding records;

Figure 22 is a diagram of a collapse/expand unit;

Figure 23 is a diagram of a specialised table lookup unit; Figure 24 is a diagram of a plurality of cascading active memory units; and

Figure 25 is a diagram of the memory system of Figure 8 employing the active memory circuit of Figure 16.

A file 2, as shown in Figure 1, may be stored in memory incorporated in a computer system or on secondary storage, such as a disc, and comprises α plurality of records 4. In indexing or searching a file 2 we wish to determine whether a set of records 4 will meet a particular property or a query. For example each record 4 may contain information concerning vehicle registrations, such as the colour of vehicle, the owner of a vehicle, the state in which the vehicle is registered and the date on which registration took .place. A query, as shown in figure 1, may be to determine from the file 2 which vehicles are red, registered in the state of N.S. . and registered after 1st January 1985. The set of records which respond to such a query can be determined from a bit map 6, as shown in figure 1. A bit map 6 is an array of bits, one per record 4. The bit corresponding to a particular record 4 will be high or 1 if that record 4 satisfies or responds to the query and low or 0 if it does not respond. Thus, the bit map 6 gives a compressed representation of the set of records which satisfy the query. In the illustrated example, a table or file 2 of 4096 records needs 4096 bits or 512 bytes for a bit map 6. Figure 1 illustrates a complex query. The bit map 6 or records 4 responding to a complex query can be computed by a simple logical operation on bit maps 8, 10 and 12 representing the records responding to constituent simple queries which make up the complex query, as shown in figure 2. Following the previous example, the query can be broken up into three queries in order to determine three bit maps 8, 10 and 12 which indicate the records in which a car is red, registered in the state of N.S.W. and the date of registration is later than 1st January 1985, respectively. As shown in figure 2, performing an AND operation on the three bit maps 8 , 10 and 12 results in the bit map 6 which represents the records responding to the complex query. If bit maps are held in memory, computation of a final bit map 6 can be done quickly given the elementary bit maps 8, 10 and 12 are already available.-

In order to obtain full benefit from a high speed bit map processor it is desirable to be able to compute the elementary query bit maps by logical operations on still more elementary bit maps. One method of achieving this is to use a superimposed code indexing scheme described in an article entitled "Partial-Match Retrieval via the Method of Superimposed Codes" Roberts C.S. (1979) Proceedings of IEEE Vol.67, No.12, pp.1624-2642. The scheme will be briefly described with reference to Figure 3. The array of records 4 is represented in a superimposed code index as a bit matrix 14. Following our previous example in order to determine which records 4 have red cars a predetermined query code 20 is generated. The code 20 indicates that in order to satisfy the query a logical AND operation must be performed on the bit map columns 16 and 18 in order to determine a final bit map 22 which indicates the records which respond to the query. Each column of the matrix 14 is considered to be a bit map and by performing the logical operations indicated by a query 20 a desired bit map 22 is obtained.

The advantages of a superimposed code index are as follows:

1. The index is compressed, for example, the index for 4096 records occupies only 64 kBytes of memory.

2. If the index is represented in the column format as shown in figure 3 , only a small fraction of the index must be processed for any particular query.

The power of superimposed code indexing can be extended by using methods in which the attributes of the records which are of interest are represented in this form.

The disadvantages of superimposed coding, however, are as follows:

1. All ordering information is lost so that greater than/less than queries cannot be performed, although they can sometimes be approximated by encoding ranges as discrete attributes. 2. There is a (usually small) probability of false drops, so that the bit map produced in response to a query may contain more than the set of records which satisfy or respond to the query. The main problem with this is that it is not possible to use superimposed coding to find records responding to a not equals query, for example cars not registered in N.S.W.

There are, however, other methods of processing indexes. A boolean attribute of a record can be encoded as a single bit, for example if the attribute is whether an owner of a car has paid his registration fee requires merely a true or false answer. As shown in figure 4, a boolean attribute of a record can be determined by merely consulting a bit map 24 of an array 26 of records 28, the bit map 24 comprising the^* single bits representing the attribute. The bit map 24 provides an instant indication whether the attribute is true. A bit map 30 for a query on that attribute being false is computed by taking the logical complement of the map 30 , as shown in figure 4.

This leads to a process whereby exact quality queries can be effected, as shown in figure 5. An attribute, e.g. state of registration, is encoded as a binary number and the table 32 of that attribute is a collection of boolean attributes, and exact equality query can be posed as a sequence of true and false boolean queries. A not equals query can be processed in a similar fashion. As shown in figure 5, a series of boolean operations or logic operations are performed on the columns 34, 36 and 38 of the table 32 in order to determine the bit map 39 which indicates the records where the state of registration is N.S.W.

A disadvantage of the above approach, however, is unless the attribute has very few bits (less than 5, say) , it would take more processing time to compute the set of records which responds to the query than it would for a superimposed coded attribute. It is particulary useful, however, for attributes with a very small number of possible values.

As shown in figure 6 , queries involving determining the order of records can be computed using bit maps. The algorithm for performing greater than/less than splits is detailed in figure 6 in a PASCAL format where the labels L, G and B[i] represent bit map columns or kxl bit matrices, where k=the number of records in a table 40 and n is the number of bits in an encoded record in the table 40. W is the test word 42 and represents the code on which the greater or less than query is based. The algorithm performs a split of the records in the table 40 with respect to the test word 42 provided in the query. The algorithm has two working bit maps, L map 44 of records known to be less than the test word 42 and G map 46 of records known to be greater than the test word 42. A given word or encoded record is greater than the test word 42 if the first bit (going from the most significant bit to the least significant bit) in which it differs from the test word is greater than the corresponding bit in the test word. The bits can only be 0 or 1 and therefore if a word is greater than the test word the first differing bit must be 0 in the test word and 1 for that bit of the encoded record or word. If a bit in the test word is 0, the set of encoded words decided to be greater than the test word when that bit is considered is the set of encoded words or records with a 1 in that bit. Similarly, if the test word has a 1 in a particular bit position, the set of encoded words on considering that bit position to be less than the test word is the set of encoded records with a 0 in that bit position.

When the test word 42 has a 0 in a particular bit position, an uncharacterised reference or encoded word of the table 40 can either continue to be equal to the test 42 or it can be decided to be greater than the test word 42. When the test word 42 has a 1 in that bit position, an uncharacterised encoded word can either continue to be equal to the test word 42 or can be decided to be less than the word 42. Once an encoded v/ord has been characterised as greater than or less than the test word, the characterisation cannot be changed. The split operation requires several bit map operations per bit of an attribute, so that it would be economical to encode the raw attribute in some way which preserves the essential order information. For example, a date attribute which has a range of one year can be encoded with nine bits. By adapting an algorithm from associative memory literature, it is possible using bit map operations to find the minimum of an attribute and the location of the records containing that minimum value, as shown in Figure 7. The algorithm listed in Figure 7 is in a PASCAL format and the labels M and B[i] represent a bit map column whereas W[i] represents one bit of the smallest or minimum encoded word of a bit matrix 48. The M bit map 50 upon completion of the algorithm indicates which record contains the minimum encoded word of the matrix 48, n being the number of bits in an encoded record of the matrix 48. The algorithm computes the smallest word W 52 and the M bit map 50 together, by analysing one bit map of the matrix 48 at a time from left to right (most significant bits to least significant bits) .

At any particular bit position of the matrix 48 the bit map 50 will contain an indication as to the records not yet discarded and the word W 52 would contain the bits of a smallest word as so far detexmined. If any of the records not yet discarded has an encoded word with a value 0 in that bit position, then those records having an encoded word with 1 in that bit position cannot be the smallest. The bits in the M bit map 50 corresponding to records having encoded words with a 1 in that bit position must be set to 0. The smallest word must also have a 0 in that position. However, if all the records not yet discarded have encoded words with the value 1 in that bit position under consideration, then no records may be discarded and the smallest word has a one in that bit position. The step in the algorithm, (M AND B[i]) = M, can be reduced to testing for whether the bits in a bit map generated by the operation (M AND B[i]) XOR M are all zero or not (the "all zeroes test") , because if they are all zero the M bit map 50 has not changed and need not be operated on. As this step dominates computation time by reducing it using an all zeroes output from an active memory circuit, as described below, the algorithm is performed more rapidly which makes the algorithm practical.

It is possible to perform a large variety of queries on a bit map index, as described previously. The index*is preferably a table of superimposed coded words with the addition of full binary encodings of boolean and other attributes with a small number of values, attributes where a not equal query is possible, and attributes where order of information is necessary for queries. For economy of memory space, all full binary attributes are encoded by a small number of bits.

A content-addressable memory system 62 which enables the above operations to be performed on a bit map matrix is shown in Figure 8 connected to a host computer 60. The host computer 60 is a conventional computer system comprising a central processing unit 64, a memory 66, a mass storage capability 68, such as a plurality of discs, and an input/output port 70 for peripheral devices. A host processor bus 72 is also provided which enables data to transferred between the units 64, 66, 68 and 70 of the host computer 60.

The content-addressable memory system 62 comprises an index memory unit 74, an index processor 76 and a memory system bus 78 which connects the index memory unit 74 to the index processor 76 and enables data to transferred between the memory unit 74 and the processor 76.

The index memory circuit 74 and the index processor 76 are connected to the host processor bus 72. The index processor 76 transfers data to and from the index memory unit 74 and performs operations on the data in response to instructions received from the host computer 60, via the host processor bus 72. The host computer 60 is able to access data 'from the index memory unit 74 via the host processor bus 72, and to the computer 60 the index memory unit 74 appears to be standard random access memory organized into 16 bit words. Data may be accessed from the index memory unit 74 by the index processor 76, via the memory system bus 78, whilst the memory unit 74 is being accessed by the host computer 60 without memory contention problems. This is because the memory system 62 includes a bus 78 which operates autonomously with respect to the host computer 60.

The index memory unit 74 is used to store a bit map matrix which is an encoded representation of records stored in host computer 60. The index processor 76 is designed to perform bit map operations on the matrix stored in the index memory unit 74. A prototype of the memory system 62 has been constructed, known as the attached index machine (AIM) . The remaining description of the memory system 62 will be with respect to an implementation of the AIM which includes an index memory unit 74 capable of storing and performing operations on a bit map matrix having: a column length of 4096 bits and row length of 2 6- bits. It is to be understood that the memory system 62 could be used to store and perform operations on a bit map matrix of any practical size.

The memory system 62 is a bit-serial word-parallel content-addressable memory system as it accesses bits of a record serially, whilst accessing all of the records in parallel, the bits being bits of bit map matrix.

The index memory unit 74 comprises 32 index memories 80 which are arranged in groups of 4 so as to fit on vertical printed circuit boards 82, as shown in Figure 9. The memories 80 are also arranged into 2 banks each comprising 16 memories 80 which are capable of storing a 256 x 4096 bit map matrix. A 4096 bit column, or bit map, is stored in 256 bit portions 82 among 16 index memories 80, as shown in Figure 10, in corresponding locations in the memories 80.

The index processor 76 is adapted to access two 4096 bit columns, or bit maps, 84 and 86 from a matrix 88, as shown in Figure 11, perform a selected bit map operation on the columns 84 and 86 and return the resultant column, or bit map, 90 to the matrix 88. At present, the AIM is able to perform this function within one 16 microsecond cycle. This includes providing the host computer 60 with an indication of whether the bit map 90 comprises all zero bits and, if not, providing a report on the addresses of the records associated with the bits in the column 90 which are high.

An index memory 80 comprises a TMS4161EV4 video memory chip, as shown in Figure 12, which includes a 64 kbit dynamic random access memory array 92 and a 256 shift register 94. The memory array 92 is connected to the shift register 94 via a parallel 256 bit bijs 96. The TMS4161 chip 80 is basically a standard RAM provided with a shift register 94 which is capable of accessing any selected row of the array 92. A row of the array 92 comprises a 256 bit portion 82 of a 4096 bit column or bit map.

By accessing a particular 256 bit row in the array 92 using the address lines 98 and enabling the TR/QE input line 100, data is transferred between the row and the shift register 94. The direction of the transfer is governed by the read/write line 102. To perform a transfer of data between the shift register 94 and a selected row of the array 92 a transfer request is issued by the index processor 76 and the row is selected. It is necessary at this stage to synchronize any access request from the host computer 60 with the transfer request from the processor 76 and this is performed by a 3 way arbitration circuit (not shown) in the index memory unit 74. At any other time the index processor 76 may manipulate the contents of the shift register 94 without interferring with access requests from the host computer 60.

The shift register 94 at one end includes a serial output port 104, as shown in Figure 12, and at the other end includes a serial input port 106 and this enables the shift register 94 to be clocked by a clock line 108, so that data at one end of the shift register 94 is outputted via the output port 104 whilst data Is inputted at the other end of the shift register 94 via the input port 106.

The index memory unit 74, as shown in Figure 13, is arranged into two banks 110 and 112, each bank comprising 16 index memories 80, as mentioned previously. When a bit map operation is to be performed one operand is selected from the bank 110 and the other operand is selected from the bank 112. The operands are selected by the host computer 60 and in each bank 110 and 112 a predetermined row is accessed in each of the arrays 92 in each bank 110 and 112 and the contents of the predetermined rows transferred to the shift registers 94 of the banks 110 and 112. The shift registers 94 of the banks 110 and 112 thereby both contain a bit map. All of the serial output ports 104 of the ^"Sftift registers 94 in the first bank 110 are connected in parallel via a first bank output bus 114 to the memory system bus 78. Similarly, all the serial output ports 104 of the shift registers 94 and the second bank 112 are connected via a 16 bit second bank output bus 116 to the memory system bus 78. The operands for a bit map operation stored in the registers 94 in the two banks 110 and 112 are outputted to the index processor 76 via the buses 114 and 116, by clocking the registers 94 using the clock line 108. Although the bits of the bit maps in the registers 94 of the two banks 110 and 112 are outputted serially, a bit from each portion 82, as shown in Figure 10, 16 bits are outputted simultaneously along each bank output bus 114 and 116 and to the index processor 76 they appear as 16 bit words. The index processor 76 performs a selected bit map operation on the 16 bit words inputted via the bank output buses 114 and 116 and sends a resultant 16 bit word back along the memory system bus 78 to a 16 bit bank input bus 118. The bus 78 includes at least three 16 bit data paths.

The bank input bus 118 is connected in parallel to the 16 serial input ports 106 of the registers 94 in the banks 110 and 112. Hence, as 16 bit words are outputted via the bank output buses 114 and 116, a resultant 16 bit word is stored at the opposite ends of the shift registers 94 in the banks 110 and 112. At the end of the selected bit map operation a resultant bit map is stored in the shift registers 94 of the first bank 110 and the shift registers 94 of the second bank 112. The index processor 76 then transfers the resultant bit map to a predetermined row, selected by the host computer 60, in the arrays 92 of the first bank 110 or second bank 112.

The index processor 76 includes a host interface port 120 which is connected to the host processor bus 72 via a bidirectional bus 122. The processor 76 also includes a serial functions unit 124 which is connected between the host interface port 120 and the memory system bus 78 via bidirectional buses 126 and 128, respectively.

The serial functions unit 124 operates in response to instructions from the host interface port 120 an'd it performs the bit map operations on 16 bit words inputted to the unit 124 via the system bus 78. It also includes circuitry to compare resultant 16 bit words with test words, to determine if the resultant words comprise all zero bits and record the offset location or address location of bits In the resultant words which are high. The serial functions unit 124 can be configured so as to run for 256 cycles when triggered by the host interface port 120, each cycle including accessing two 16 bit words, performing a bit map operation on the words, analysing the resultant word and outputting the resultant word to the bus 78.

The host interface port 120 includes a control unit and receives instructions from the host computer 60. In response to the instructions received from the host computer 60, the port 120 controls the operations of the serial functions unit 124 and data transfer in and between the index memory unit 74.

Data flow between the index memory unit 74 and the index processor 76 is illustrated in Figure 15, however not all data paths are shown. In performing a b t map operation two 16 bit words are accessed by the processor 76 from the banks 110 and 112 and each word is inputted simultaneously to the serial functions unit 124. The two words are passed through respective gates 130 and 132 and masked in the gates according to state of respective mask registers 134 and 136. The gates 130 and 132 are connected to the inputs of a boolean logic unit 138 which performs a selected logic operation on the words and outputs the 16 bit result of the operation to a, shifting logic unit 140 and a matching logic unit 142. The boolean logic unit 138 is capable of performing a number of logic operations, such as AND, AND NOT, OR, OR NOT, NOT, XOR, XOR NOT OR COPY. COPY is performed by ensuring one of the operands is zero and an OR operation is performed. The operation to be performed is selected by a control unit 144 in the host interface port 120 in response to instructions received by the host computer 60.

The matching logic unit 142 compares resultant 16 bit words outputted by the boolean logic unit 138 with 16 bit test words stored in a test word register 148. If the resultant words match the test word the control unit 144 stores the offset or address location of the matching resultant word in a FIFO hits register 150. To perform an all zero test the test word register 138 is loaded with a word having all zeros or low bits. The shifting logic unit stores the resultant 16 bit words whilst they are compared in the matching logic units 142 and then outputs the resultant words to the banks 110 and 112 in the index memory unit 74. The control unit 134 controls the matching logic unit 142 and the shifting logic unit 140 as well as other components of the memory system 62 and receives instructions form the host computer 62 which are stored in an instructions register 152. Although the instruction register 152 is illustrated as forming part of the bank of registers 134, 136, 148 and 150 in the serial functions unit 120 the register_^ 152 usually forms part of the control unit 144.

An active memory circuit or chip 150 , as illustrated in figure 16, is designed so as to perform the bit map operations, described above, on a bit map matrix. The circuit 150 comprises a memory portion 152 capable of storing an array of bits, a shift register 154, which is preferably bidirectional, a logic unit or circuit 156 and a temporary storage area or portion 158 for temporarily storing bit maps during operations.

The chip 150, in use, contains an array of bits stored in the memory portion 152. The array of bits would represent a bit map matrix. The size of the array is not critical but 256x256 bits would be preferable. The data held in the chip 150, represented by the bits, is done in a different manner to a conventional memory. A bit matrix comprising part of the index to a table of records, in use, is mapped directly onto the array of the memory portion 152. A row 160 in the array holds the index bits representing a single record (256 bits is usually sufficient for complex records) . Any column 162 of the array holds a bit map of a table or matrix, of the type described with reference to figures 1 to 7.

The shift register 154 on the chip 150 is similar to that of the registers 94 to memory banks 110 and 112 used in the AIM, referred to previously. The chip 150 is able to copy a selected column from the bit array stored in the memory portion 152 onto the shift register 154, as in the banks 110 and 112. It is also possible to replace the contents of the shift register with the result of a logical operation performed on a selected column and the previous contents of the shift register 154.

Data may be shifted in and out of the shift register 154 by means of shift in and shift out lines 164 and 166, respectively. The chip 150 also comprises row/column selection input lines 168, and a row input/output line 170 for inputting and outputting data into the memory portion 152 in consecutive rows 160. A plurality of control lines 172 is also provided for controlling the operations performed by the chip or circuit 150 and selecting memory elements of the memory portions 152 and 158. An all zeroes output line 174 is also provided which goes low whenvever the bits of a column stored in the shift register 154 are not all zero. The all zeroes line 174 allows the minimum word algorithm to be performed practically. The command lines 172, inter alia, input signals which control the operation of the shift register 154, the logic unit 156 and input and output of bit maps from the memory portion 152 and the temporary memory portion 158. The inputs on the lines 172 would instruct the chip or circuit 150 to perform the following functions in order to carry out the bit map Indexing operations previously described.

(i) AND the contents of the shift register 154 with a selected bit map 162 and store the result in the shift register 154

(ii) OR the contents of the shift register 154 with a selected bit map 162 and place the result in the shift register 154

(iii) XOR the contents of the shift register 154 with a selected bit map 162 and input the contents to the shift register 154.

(iv) Copy a selected bit map 162 to the shift register 154

(v) Copy the contents of the shift register 154 to a selected column 162 of the memory portion 152.

(vi) Complement the contents of the shift register 154

(vii) Shift up one bit the contents of the shift register 154

(viii) Shift down one bit the contents of the shift register 154.

For many purposes, including the greater than/less than split operation, it is convenient to have a temporary storage portion 158 in which several extra columns or bit maps may be stored which cannot be stored in the shift register 154 simultaneously. The columns participate in the logical operations in the same manner as the columns of the bit array stored in the memory portion 152. The circuit 150 enables all of the bit map logic operations, described previously, to be performed entirely on board a single semi-conductor chip. Upon processing a query a final bit map can then be examined to identify the records responding to the query. This examination is performed by an external circuit which accesses the bit map^* through a shift out line 166. As the index for a table or file would be stored on a number of chips 150 and since only a few records will possibly respond to a query, most of bits in the shift registers 154 containing a final bit map could be all 0. Therefore the all zeroes line 174 provides an indication whether the records corresponding to the code index stored in a chip 150 need be examined in detail or not. If the all zeroes output 174 is high then the records associated with that respective chip 150 may be discarded as they do not respond to a certain query. Therefore, with the all zeroes output line 174 it is not necessary to search all of the chips 150 associated with the given file as only the chips having a low signal on the all zeroes output line 174 need to be examined in order to extract a final bit map, stored in their respective shift registers 154, to determine the records responding to a certain query.

The indexes stored on the chips 150 must be loaded onto the chips 150 from external storage and must be updated. Although the chip 150 processes the indexes column wise, it is convenient for the external storage and updates to be able to access the rows of the memory portion 152 directly which is achieved by serially inputting data via the serial input/output port 170 which shift bits directly to/from a selected row in the bit array. The rate of this operation is 1 or 2 MHz which is slower than the shift in/shift out operation which would be 25 MHz or more. The row input/output function could also be adequately carried out using a standard single-bit access port.

The active memory circuit 150, as shown in more detailed in figure 19 comprises a memory array 180 which comprises a number of 1 bit storage elements 182 that are addressable by a row column address decoder 184. An array 186 of 1 bit storage elements 182 is also provided to form the temporary storage portion 158. The array 186 is accessed via a temporary bit map address decoder 188. The decoders 184 and 188 access the arrays 182 and 186 on the basis of select, row/column and address inputs 190. These inputs 190 form part of the control inputs 172, described previously and the row/column selection inputs 168. Each one bit memory element 182 provides a bit output M 192 and a complement of the bit output M 194. Data is written out onto the lines M and M 192 and 194, respectively, of a selected element 182 in response to inputs received from a memory control unit 196 which receives inputs 197 forming part of the control inputs 172.

A bi-directional shift register 154 comprises an array of master-slave flip-flops 198. The contents of the flip-flops 198 may be shifted up or down by respective shift/complement units 1100 which can also complement the contents of the flip-flops 198. A logic unit 1102 is provided for each flip-flop 198 in order to perform selected logic operations on the contents of the shift register 154 and a column of the memory array 180, as described previously. The shift/complement units 1100 and logic units 1102 are controlled by inputs received from a command decoder 1104 such that each shift complement unit 1100 or each logic unit 1102 functions 'in the same manner simultaneously. Hence, logic, shifting and complementing operations are performed on a column of bits forming a bit map. The command decoder 1104 outputs signals to the units 1100 and 1102 in response to inputs received via command lines 1106 which form part of the control lines 172. As the shift register 154 is bi-directional data may be shifted in and out of the register 154 via the top of the register 154 or the bottom of the register 154 using a shift in/out top line 1108 or a shift in/out bottom line 1110, respectively. The all zeroes output 174 is obtained by performing a NOR operation on the contents of the flip-flops 198 in a multiple NOR gate 1112.

When the active memory circuit 150 is configured on a single semi-conductor chip each shift/complement unit 1100 and respective flip-flop 198 form a single shift register cell 1150, as shown in figure 18. The shift register cell 1150 comprises a master-slave flip-flop 1152 and a plurality of MOSFET transistors 115.4 most of which are controlled by control lines which receive outputs from the command decoder 1104. The lookthru control line 1156 allows data to be inputted and outputted via the input S. of the flip-flop 1152 and the not control line 1158 when set high complements the contents of the shift register 1152. The all zeroes line 1160 is brought low whenever the .output S 1162 of the flip-flop 1152 is high. When the shift down control line 1164 is high the contents of the flip-flop of an upφer shift . register cell 1150 is passed to the input S. 1164 of the flip-flop 1152. Similarly, when the shift up control line is high the contents of a flip-flop of a lower shift register cell 1150 is passed to the input 1164 of the flip-flop 1152.

The cell 1170 of the logic unit 1102, as shown in figure 10 comprises an OR gate 1172, an AND gate 1174 and an XOR gate 1176 which perform logic operations on the contents of the flip-flop register 1152, which appears on the output line 1166, and the contents of a selected memory cell 182, which appears on the line M 1178. In order to perform the XOR function the XOR gate 1176 requires inputs from the lines 1180 and 1182 on which are the complement of the contents in the flip-flop 1152 and the selected memory cell 182, respectively. The logic operations are performed and the results of a selected operation is only outputted to the input 1164 of the flip-flop 1152 when, in accordance with the selected operation, the OR control line 1184, the AND control 1186 or the XOR 1188 goes high. The high and low voltage lines 1190 and 1192, respectively, are provided, as shown in figure 18, for the OR gate 1172 and the AND gate 1174.

When the line M>S 1194 goes high the contents of a selected memory cell 182 is inputted via the line 1178 to the input 1164 of the flip-flop 1152. Similarly, the contents of the flip-flop 1152 is outputted to a selected memory cell 182 via the line 1162 when the S>M line 1196 goes high. The memory cells 182 when selected by the decoders 184 and 188 to have their contents shifted in and out of the shift register 154 to have logic operations performed on them are selected in a column which may come from the array 180 or the array 186.

The main applications for the active memory circuits are in respect of content-addressable memories, in order to provide indexing for information retrieval and a more specialised table look up as in the AIM, referred to previously.

An active memory dependent subsystem 1200, designed as a co-processor, is attached to a host system via a host system bus 1202, as shown in figure 19. The active memory, which comprises a number of active memory chips or circuits 150, is organized into a memory subsystem 1200 with addressing and control logic 1206. Control of the active memory to perform specific functions is done by specialised logic units 1208, grouped together into a logic subsystem 1204. Access to the host system bus 1202, transfer of data, and overall control is performed by an instruction decode/interpret unit 1210.

For general indexing, the logic units 1208 perform the operations described with reference to Figures 1 to 7. Superimposed coding is the most complex of these operations. Figure 20 shows a superimposed code word calculation unit 1220 which accepts as an input a hashed constant and produces either or both a code word (in a register Rl 1222) and a bit map of responding records in the memory subsystem 1200. The random numbers utilized in this unit 1220 are calculated using a linear sequential circuit.

The result of an indexing operation is a bit map of responding records in the memory subsystem 1200. The host application is interested mainly in the locations of the responding records, not in the bit map per se. Figure 21 illustrates a unit 1230 which holds a plurality of active memory circuits or chips 150 in order to extract a responding bit map from the shift registers of those circuits 150 not reporting all O's, i.e. those with a low signal on the all zeroes output line, and storing the addresses corresponding to the 1 bits in the responding bit map, in a FIFO storage unit 1232. Preferably the process would be pipelined, so that the host gets an address as soon as it is produced. The unit 1232 operates autonomously calculating further addresses and storing them in the FIFO unit 1232. If the FIFO unit 1232 becomes full before the entire responding bit map has been scanned the unit 1232 pauses until the host has either cancelled their request or query or removed an address from the FIFO 1232. The responding bit map is stored in a bit register 1231 and control is effected by a select/control unit 1233.

In highly dynamic applications, there is a frequent need to insert or delete index entries using the row input/output line 170, as previously described with reference to figure 16. Alternatively, during a given application periodic garbage collection may require a large number of data entries to be removed at one time. One way to perform such an operation is by using a collapse/expand unit 1234, as shown in figure 22. The unit 1234 either collapses or expands the index rows stored in the active memory circuits or chips 150 under control of a bit map. In collapse mode, the bit map has a 1 in every position where an index row is to be removed. The unit copies each row in turn into its row buffer 1236. The unit 234 keeps a count of the number of rows so far removed and uses that to determine the row into which to copy the contents of the row buffer 1236. Expansion operates in the reverse. The bit map would have a 1 in each position in which a row is to be inserted and the copying operation proceeds from the highest row address to the lowest. Zeroes are inserted into the vacant rows. A single bit set in the bit map would insert or delete a single row. The collapse/expand unit 1234 is controlled by a select/control unit 1235 and a control bit map store 1237 stores the bit map which indicates on which rows a collapse or expansion is to be performed.

A plurality of active memory circuits or chips 150 could be used in many applications for fast table lookup, such as for virtual memory support, node switching a data flow computer, and keeping track of objects in a CAD system. This is a much simpler application of the active memory circuit 150, requiring only equality tests and expecting only one hit, if any, so the elaborate architecture of figure 19 is not required. Figure 23 shows a preferred embodiment of a specialized table look up unit 1236 with integrated active memory chips 150. The host would supply a test word for storage in a test word register 1239 and the unit 1239 would return in a hit register 1240 an indication as to the the test word's address in a table. The unit 1238 includes a control unit 1241.

The active memory chip 150 preferably has a square array 180 of memory elements 182 with extra columns provided by a temporary storage array 186. It is clear from the potential applications of the circuit 150 that the row or column views of the array 180 are different, so there is no logical necessity for a symmetrical arrangment of storage elements 182 for bits. An index for a file of 100,000 records fits into 128 bits in most cases. A table look up might need only 32 bits per row but thousands of rows. Therefore it may be preferable to design the active memory circuit 150 as a cascadable unit 1250, perhaps 32 bit square. A high density chip might have many of these cascadable units 1250, as illustrated in figure 24.

In a table look up application, portions of the table would reside in each unit 1250 and elementary operations would be performed on all the units 1250 at the. same time. For a general indexing {application, a logical, row might extend over several units or chips 1250 in the row direction. The final bit map is produced section by section using operations selecting all the elements in a single column with a combining process at the end. It is convenient for combining to be able to copy the contents of a selected shift register into the shift register of a unit 1250 furtherest to the left in its row. Cascading down the " column is much simpler requiring only the logical coupling of the shift registers.

The most readily recognisable application of the active memory circuit 150 is in the content-addressable memory system 62 described previously. A content-addressable memory system 62 employing the active memory circuit 150, as shown in Figure 25, comprises 16 video memories 80, forming the index memory unit 74 , and 16 active memory circuits 150 which form the index processor 76. The index processor 76 would also include a control unit (not shown) such as the host interface port 120 described previously, to control the active memory circuits 150. Bit maps or columns having a size of 4096 bits are transferred to the bit map storage facilities on the active memory circuits 150, via a 16 bit bus 1500. Bit map operations are performed on the bit maps stored in the active memory circuit 150 and the results of the operations may be returned to the index memory unit 74 via a 16 bit data bus 1502. The architecture shown In Figure 25 enables complex bit map operations to be performed at a much fast rate as compared to the memory system 62 of Figure 8. The architecture of Figure 25 also enables large bit map matrixes to be stored with the same amount of memory, and data can be shifted out of the register 94 in the memory unit 74 without having to recover previous data outputted by inputting data at the serial input ports 102 of the registers 94 simultaneously. The bus required for the transfer of data is also only 16 -bits wide and, hence, only the transfer of 16 bit words needs to be monitored instead of the transfer of three 16 bit words as in the memory system 62 of Figure 8. The index processor 76 of the architecture 25 is able to perform bit map operations in cycles less than 1 microsecond.

Claims

1. A content-addressable memory system (62) for connection to a host computer (60) having a host memory (66, 68) storing a plurality of records and a host processor bus (72), said memory system (62) comprising: index memory means (74) for storing a bit map' matrix representative of records stored in said host computer (60), said memory means (74), being, in use, connected to said host processor bus (72) and addressable by said host computer (60); index processor means (76) for accessing bit maps stored in said memory means (74) and performing bit map operations on said bit maps, said index processor means (76) being, in use, connected to said host processor bus (72) and controlled by said host computer (60); and a memory system bus (78) connected between said index memory means (74) and said index processor means (76), said bus (78) being adapted to pass bit maps between said memory means (74) and said processor means (76).

2. A content-addressable memory system (62) as claimed in claim 1 wherein said index memory means (74) comprises a plurality of index memories (80) which each include: an array (92) of memory cells; and a shift register (94) having a parallel input/output bus (96) connected to said array (92), and a serial input port (106) and a serial output port (104) at opposite ends of said shift register (94), said parallel input/output bus (96) being capable of accessing a selected row of data in said array (92); said memory system bus (78) connects the serial input and output ports (106 and 104) of the index memories (80) in parallel to said index processor means (76); and said selected rows of data accessed simultaneously form at least one bit map.

3. A content-addressable memory system (62) as claimed in claim 2, wherein said arrays (92) may be accessed by said host computer (60), whilst said index processor means (76) accesses said shift registers (94) .

4. A content-addressable memory system (62) as claimed in claim 2 or 3, wherein said index memories (80) are arranged in a first or second bank (110 or 112) and, in performing a predetermined bit map operation, said index processor means (76) accesses a first bit map from said first bank (110) and a second bit map from said second bank (112), said first and second bit maps forming the operands for said operation.

5. A content-addressable memory system (62) as claimed in claim 4, wherein prior to performing said operation said bit maps which form the operands are stored in the shift registers (94) of the respective banks (110, 112) and during said operation said index processor means (76) simultaneously accesses a bit from the serial output port (104) of each shift register (94), said accessed bits forming two words one from each bank (110/ 112), performs said operation on said words and outputs the resultant word of the operation to the serial input ports (106) of the shift registers (94) of at least one bank (110, 112).

6. A content-addressable memory system (62) as claimed in claim 5, wherein said operation is performed in less than 16 microseconds if said bit maps comprise 4096 bits.

7. A content-addressable memory system (62) as claimed in anyone of claims 4 to 6, wherein said index processor means (76) includes: a host interface port (120) connected in use, to said host processor bus (72); and a serial functions unit (124) connected to said host interface port (120) and said memory system bus (20); said interface port (120), in response to instructions from said host computer (60), accessing said first and second bit maps and causing said serial functions unit to perform a predetermined bit map operation on said first and second bit maps.

8. A content-addressable memory system (62) as claimed in claim 7, wherein said serial functions unit (124) comprises a logic unit (138) having input lines coupled to said serial output ports (104), via said memory system bus (78), and outputs lines coupled to said serial input ports (106), via said memory system bus (78) and a delay unit (140), which enables the output of said logic unit (138) to be monitored.

9. An active memory circuit (150) comprising: an array (180) of memory cells (182) arranged in rows (160) and columns (162) adapted to store at least part of a bit map; a shift register (154) adapted to store at least part of a bit map; and a logic unit (156) connected between said array (180) and said shift register (154); said array (180), shift register (154) and logic unit (156) comprising an integrated circuit and said shift register (154) being able to copy a selected column (162) of said array (180) and said logic unit (156)° being able to perform a selected logic operation on the contents of said shift register (154) and a selected column (162) of said array (180), the result of said operation being stored in said shift register (154).

10. An active memory circuit as claimed in claim

9, wherein said shift register (154) comprises a column of shift register cells (1150) and said logic circuit (156) comprises a column of logic cells (1170), the logic cells (1170) being coupled to respective shift register cells (1150) and a respective rows (160)of memory cells (182).

11. An active memory circuit as claimed in claim

10, wherein said logic cells (1170) perform logic operations on the contents of said shift register cells (1150) and a selected column (162) of said memory cells (182) and the result of a selected operation is written to the shift register cells (1150) when a corresponding control line (1184, 1186 or 1188) is enabled.

12. An active memory circuit as claimed in claim 11, wherein said logic operations include NOT, AND, OR, XOR, AND NOT, OR NOT, and XOR NOT.

13. An active memory circuit as claimed in any one of claims 10 to 12, wherein said each shift register cell (1150) includes a flip-flop (1152) and circuitry to complement the contents of the flip-flop (1152), and shift the contents to another flip-flop (1152) in the column of shift register cells (1150).

14. An active memory circuit as claimed in any one of claims 10 to 13, wherein said logic cells (1170) include circuitry which enables the contents of said shift register cells (1150) to be stored in a selected column (162) of memory cells (182) and the contents of a selected column (162) of memory cells (182) to be stored in said shift register (1150) when first and second storage control lines (1196 and 1194) are enabled, respectively.

15. An active memory circuit as claimed in any one of claims 9 to 14 further comprising a NOR gate (1112) the output of which goes high when the contents bits stored in said shift register (154) are all low.

16. An active memory circuit as claimed in claims 11 or 14 further comprising a command decoder (1104) having outputs connected to said control lines (1184, 1186, 1888, 1194 and 1196), said decoder (1104) being responsive to inputs received via command lines (1106).

17. A content-addressable memory system (62) as claimed in any one of claims 1 to 3, wherein said index processor means (76) comprises one or more active memories (150) as claimed in any one of claims 9 to 16.