EP0044182A2

EP0044182A2 - Plasma display panel drive

Info

Publication number: EP0044182A2
Application number: EP81303065A
Authority: EP
Inventors: Joseph Thomas Suste; Larry Francis Weber; Michael James Marentic
Original assignee: Interstate Electronics Corp
Current assignee: L3Harris Interstate Electronics Corp
Priority date: 1980-07-07
Filing date: 1981-07-06
Publication date: 1982-01-20
Also published as: EP0044182B1; DE3176916D1; EP0044182A3

Abstract

A circuit for performing sustaining and pulsing operations for an AC plasma panel is disclosed, wherein two MOSFET transistors are used to alternatively, selectively provide a two level output signal. The circuit requires only a single logic input, thus preventing both transistors from conducting simultaneously, and features full slew rate control of the output. The drive circuitry is improved so that the waveforms applied to the panel electrodes to perform the sustain, write, erase, and bulk-erase functions are simplified to comprise a sequential series of rectangular waves, and only one high voltage power supply is required. High voltage is supplied to the driver chips only when they are to perform a write or erase function, thus greatly reducing the amount of power which must be dissipated in the driver chips.

Description

Plasma display panels are presently in commercial use as digitally addressable information display devices. The panel itself typically consists of two glass plates with a gas mixture sealed between them. A plurality of X-axis electrodes extend in a mutually parallel array on an interior substrate of one plate, and a plurality of Y-axis electrodes extend in a mutually parallel array on the interior of the other plate. The X-axis electrodes are at a 90° angle to the Y-axis electrodes, thereby forming a plurality of intersections between the X-axis and Y-axis electrodes. A typical commercially available AC plasma panel has 512 X-axis electrodes and 512 Y-axis electrodes, yielding 262,144 intersections or cells.
When a voltage of between 180 and 200 volts is applied across an X-axis electrode and a Y-axis electrode, a discharge in the gas occurs at the cell formed by the electrodes, causing a pulse of light to be emitted at this point. Simultaneously, a charge is collected on the cell walls, which results in the cell being an "on" cell. Once such a discharge has been produced and the cell is turned "on", the collected wall charge acts to continue the discharging when a lesser AC sustain.voltage is applied between the electrodes. In an "on" cell, the gas will discharge and the cell will emit a pulse of light at each transition of the applied AC sustain waveform. The sustain voltage, however, is insufficient to initiate a discharge at an X-Y intersection. This phenomenon is known as inherent memory, and was originally disclosed by Baker et al in Patent 3,499,167, and by Bitzer et al in Patent 3,959,190. By precisely timing, shaping, and phasing multiple alternating voltage waveforms supplied to X and Y axes electrodes, the generation, sustaining, and erasure of light emitting gas discharges at selected locations on the plasma display panel can be controlled.
Prior art devices have typically used multiple level alternating voltage sustainer drive signals which . are applied to both the X and Y electrodes, and present a composite sustainer waveform across the gas at each cell or point in the display panel where the X and Y electrodes intersect. Each of the X and Y electrodes in the past devices has been driven by one of the two separate complex sustainer circuits, operating typically at 95 volts. An improvement to this system was disclosed in Patent 4,180,762, issued December 25, 1979, to Larry Francis Weber and assigned to Interstate Electronics Corporation. This patent disclosed a means by which a single sustainer circuit is connected to one axis only of the panel electrodes, and accomplishes the sustaining function for all of the intersections in the panel.
Past systems typically required at least seven voltage levels to be supplied from the power supply, some of these levels required to be floating. These numerous voltage levels were required in order for the circuitry to generate the particular waveform required to control the generation, sustaining, and erasure.of light emitting gas discharges at the selected location in the plasma display panel. Since an AC plasma display unit is generally packaged in one unit with its power supply contained within the unit, the requirement of numerous voltage levels presents the specific disadvantages of: (a) the size of the power supply; (b) difficulties in cooling the power supply; and (c) power dissipation problems within the circuitry of the display itself .associated with the numerous voltage levels-required. A further disadvantage of the requirement of numerous voltage levels is that such systems are costly to produce and test, and must frequently have the voltage levels adjusted.
Previous sustainer designs have also required at least two logical inputs, one input controlling the high output level of the sustainer, and the second input controlling the low output level of the sustainer. If these inputs do not have the proper phase relationship to each other, serious damage could occur to the sustainer circuit, generally resulting in the destruction of part or all of the sustainer circuitry.
State of the art systems drive the electrodes in the plasma panel with Texas Instruments' integrated circuit driver chips. These chips, each capable of driving 32 electrodes on the panel, are types SN75500 and SN75501. These are the only currently available driver chips, and they have several serious design problems that the manufacturer cannot remedy at this time. The only alternative to using these driver chips is to use a resistor-diode matrix, wherein each electrode is connected to two diodes and a resistor. For 512 lines there are also 16 high voltage pulser circuits and 32 high voltage switch circuits required. In order to drive a 512 x 512 plasma display panel, the discrete electronics alternative to the Texas Instruments drive chips, it is no longer economically feasible to build plasma panel display systems without using the driver chips.
The most significant problem encountered in using the Texas Instruments driver chips is that of dissipating the power consumed in these chips. Power dissipation can be divided into 5 areas: low voltage logic power, quiescent power, level shifting boost power, parasitic power, and notch dissipation power.
Low voltage logic power is the power used to control the logical switching process of the driver chips. This power is not an appreciable cause of excess power dissipation.within the driver chips.
Quiescent power is the power consumed by the . high voltage switching components within the chip while the chip is turned on but not performing any type of operation. Since the driver chips are being used to switch 100 volts, even a small amount of quiescent current drawn by the chips will result in a fairly large amount of power being dissipated in the chips. The quiescent current for the SN75500 chips is 2 mA, and the quiescent current for an SN75501 driver chips is 3 mA. The quiescent power consumed by the chips is 200 mW and 300 mW, respectively. Since a 512 x 512 plasma display panel system requires 16 of each of the two types of chips, the quiescent power of the system's driver circuitry will be 8 watts. This power level typically represents 10 to 20% of the entire plasma display panel system power.
Level shifting boost power is the power consumed by the chip when it is being switched between output stages. The chips use a boost current of 2 mA to switch from the low state to the high state. If all of the 32 outputs of the driver chip are to be switched, a 2 mA current will be drawn by a switching transistor in the circuitry of each output at a duty cycle of 2.5%, which results in a time-averaged level of 192 mW of power per chip being consumed when switching at a standard rate of 50 kHz.
The next major power dissipation problem is created by the existence of parasitic transistors in the driver chips. A parasitic transistor is an inadvertently created np or pn junction which is inherent in the forming of a pn or np diode. In order to better understand the problem it is necessary to understand the basic operation of the driver chip switching circuit.
The design of the Texas Instruments driver chips utilizes 32 output stages in order to perform the switching operation. Each output stage is basically two switching transistors connected in series, with their common lead being the output of the circuit. The second switch lead of one transistor is connected to. high voltage, and the second switch lead of the second transistor is connected to the integrated circuit ground, or low voltage input. By ensuring that only one of these transistors is turned on at a time, the output of the circuit can be switched from high voltage to low voltage.
The transistors used in the output stages of the Texas Instruments driver chips are N-channel enhancement DMOS (double diffused metal oxide silicon) transistors, which are the key for fabricating high voltage drivers and low voltage control logic on the same chip. The Texas Instruments design utilizes a pair of clamp diodes on the common lead of the output stage transistors to prevent the output-level from rising above the high voltage or below the low voltage. When these clamp diodes are fabricated, parasitic bi-polar transistors are formed along with the diodes. These parasitic transistors, inherent in junction isolation IC technology, result from the existence of an additional np or pn junction being formed with the clamp diodes. The clamp diodes are the base-emitter junction of the parasitic transistor, and the additional junction is the base-collector junction. The resulting transistor has its emitter connected to the common output, its base connected to either the high or low voltage, and its collector connected to the other voltage level. This has the effect of placing a 100-volt drop across the base-collector junction of each of these parasitic transistors. Therefore, when the base-emitter junction is forward biased, current will flow between the base and the collector, causing power to be dissipated in this junction. While Texas Instruments endeavored to make the parasitic transistor's beta (ratio of collector current to base current) as low as possible, the typical beta of 0.4 which resulted was not low enough to eliminate the parasitic transistor as a power dissipation problem.
When the system performs a switching operation, there is a current spike drawn by the panel of 20 mA. Therefore, a current of 8 mA (0.4 x 20 mA) will flow through the base-collector junction, resulting in an instantaneous power dissipation of 800 mW for each of the 32 outputs of the chip. The only thing which prevents the chip from immediately self-destructing is the fact that the current spike lasts only 300 nS. For purposes of comparison, the clamping diode portion of the parasitic transistor dissipates only 50 mW of instantaneous power, less than one-tenth that dissipated by the parasitic transistor. The time-averaged-parasitic power consumed may be as high as 384 mW per chip.
Another type of power dissipated by the driver chips is notch dissipation power. The term "notch" derives from the level of voltage supplied by the driver chip's output stages.
If an oscilliscope is placed across the voltage supplied to the electrode and ground, the trace generated when a voltage pulse is sent to the electrode would initially rise to close to 100 volts, and then, for a fraction of a second, will drop several volts before returning to the 100-volt level. The drop in voltage level, being very short, makes the oscilliscope trace look like it had a notch removed from it; hence, the term voltage notch.
The voltage notch is caused by the high current drawn by the electrodes, which is approximately 20-mA if all 512 cells are being supplied with the voltage pulse. This current causes the transistors in a driver chip totem-pole output to develop a voltage drop which causes less than the 100 volts to be applied to the electrode. The pull-up transistor in the totem-pole of the Texas Instruments chips will develop an 8.5-volt drop, and the pull-down transistor will develop a 2.5-volt drop.
Notch dissipation power is the power dissipated in the switching transistors of the output stage, and the large amount of notch dissipation power is caused by the excess voltage drop across the switching transistors. Since the voltage drops are relatively high, a considerable amount of power must be dissipated by the switching by the switching transistors. The average power per fully loaded electrode is 1.3 mW, and the power dissipated in these switching transistors due to notch dissipation power may reach a time averaged level of about 39 mW per driver chip.
The cumulative effect of all of the above power dissipation problems in the integrated circuit chip is that the power dissipated will cause the chip to operate at a fairly high remperature. It has been observed that the temperature rise of the driver chip case is over 75°C in an ambient environment of 23°C. Since ittis generally required that the drive electronics be encased in a sealed unit, the possibility of failure due to power dissipation in the driver chips becomes even greater. It has been found that the operating life of a driver chip in a circuit using the above-described advanced technology is only hours to days.
The next problem present in the Texas Instruments driver chips is an output pulse fall time which is so fast that it generates high instantaneous currents which will cause noise generation, disrupting system performance. Both chips have fall times of 30 to 50 nS. The instantaneous current may be calculated by using the formula i = c.dv/dt. The capacitance for a typical 512 x 512 panel is 3500 pf, the voltage change is 100 V in 50 nS. The instantaneous current is therby 7 A, a tremendous amount even for a short time. This current will cause a voltage to be induced in nearby interconnecting wires, and this voltage will cause logic errors in the system.
In selecting the rise time and fall time of the voltage pulse which is suppled to the electrodes, there is a compromise involved. If the transition between voltage levels is too slow, the plasma panel display cells, or intersections between X and y electrodes, will exhibit poor memory and light emitting characteristics. Under normal circumstances, the discharge causing the emission of light pulse and the execution of a write or erase operation occurs at a point on the pulse where the peak voltage level of the pulse has been reached. However, if the transition time is too slow,.this discharge will have a tendency to occur during the rising portion of the pulse, before the peak voltage has been reached. The result is a weak discharge causing poor memory and poor light emitting characteristics in the plasma panel system.
In contrast, too fast a transition time will cause noise to be generated in the system, given the relatively high voltage of about 100 volts that is being switched. The Texas Instruments driver chips have fall times of 30 to 50 nS. If an electrode of the plasma panel is charged to 100 volts in 50 nS, the instantaneous current flowing through the charging circuit is approximately 7 amps. Since the physical size of a typical plasma display panel is 1 foot x 1 foot, the presence of 512 X-electrodes and 512 Y-electrodes in that area indicates that these electrodes are extremely close together. Interconnecting wires to the plasma panel have been found to have approximately 1 nH of inductance and the extremely high instantaneous current will therefore cause voltage drops of several volts in adjoining wires, which will result in logic errors in the plasma display panel system.
Transition times of between 200 and 400 nS are generally considered ideal. While the rise times of the Texas Instruments driver chips fall within this range, the fall times are much too fast. The result of using the Texas Instruments driver chips is an unacceptably large number of logic errors.
The next problem associated with these driver chips is caused by the voltage notch described above. In addition to being a power dissipation problem, the large voltage notch imposes constraints on the design of the system. The voltage notch, particularly the 8.5 V'drop in the high state, causes the voltage applied to the panel to be dropped from the desired 100 V to about 92.5 V, when the selected electrode is being driven to the high state.
This lesser voltage level is very near the absolute minimum required voltage, and any further losses will cause a failure in the operation of the panel. Since no further loss can be tolerated, precise regulation of the power supply, the use of high- precision components, and careful layout of the system are mandatory. The plasma display panel itself may have to meet more rigorous standards. All this leads to higher product cost, and less flexibility in making system trade-offs.
In addition, a 1024 x 1024 panel could not be driven by these driver chips, since such a panel would draw approximately 40 mA from each IC, increasing the voltage notch. Therefore, these chips are limited to driving a panel no larger than a 512 x 512 size.
There is also a logic error in the SN75501 driver chip. The chip is switched from its low output to its high output by a current booster (responsible for the boost current power dissipation problem described above). This current booster is essentially a bi-level current source. When the driver chip output is in its low state, 10 microamps are supplied. When a logic signal indicates the driver chip is to go high, the current booster supplies a 2 mA boost current, causing the pull-up output transistor to be driven on.
The logic error occurs when the strobe input pin of the chip (used for the address pulse input) is held low and the sustain pin (used for the distributed conditioning input) is brought high. This logic state should cause the driver output to quickly go to its high state. The boost current, however, is not applied, and the output is a slowly rising ramp, taking 5 to 10 microseconds to reach the high state.
Since an operation on the panel may take less than the 5 to 10 microsecond rise time of the pulse, it is not of any use in addressing the panel. In the past, systems have been designed around this flaw, resulting in inefficient and inconvenient operations being necessitated.
The present invention relates to improved driver circuitry for an AC plasma panel having a number of significant features. In order to understand the importance of those features, a brief description of the operation of a plasma panel is necessary.
There are four control functions that are used to operate an AC plasma panel: the write function, the erase function, the sustain function, and the bulk-erase function. The write function causes a selected cell on the panel to be changed from the "off", or non-light emitting state, to the "on", or light emitting state. The sustain function maintains the state of all cells in the panel, i.e., causes "on" cells to remain on, and "off" cells to remain off. The sustain function also causes the "on" cells to emit light. The erase function causes a selected cell to be changed from the "on" state to the "off" state. The bulk-erase function causes all "on" cells in the panel simultaneously to be changed to the "off" state.
In the preferred embodiment of the invention, the sustain voltage waveform is a simple rectangular wave for the X-axis, requiring no additional shaping or pedestals for all display operating modes. The sustainer waveform is generated by bipolar circuits in prior art systems, but the preferred sustainer is of a new type disclosed later in this specification. Since there are no complex pedestal shaped waveforms, there is no need to produce the plurality of intermediate voltage levels required in prior art systems. In addition, the control logic is also simplified by virtue of the simplified sustain waveform. Also, the X-axis electrode driver outputs are normally in their low (least power) state and only go high for addressing selected electrodes.
Another feature of this invention is that in the address mode, only the addressed cells are supplied an address pulse, with all other cells being supplied the normal sustain voltage levels. As a result, wide, error-free margins can be obtained in contrast to prior art systems in which addressing is accomplished by address modes which partially drive the non-addressed cells.
Operation of the four control functions is controlled by four logic signals: the X-sustain signal XS, the Y-sustain signal YS, the X-Address Pulse XAP and the Y-Address Pulse YAP. These signals, generally supplied by a waveform ROM (Read Only Memory), are digital pulse trains typically operating at a frequency of 50 kHz. The logic signals are supplied to the sustain and drive circuits, and cause these circuits to execute the four control functions on the panel.
The erase mode of this invention is also entirely novel. The erase waveform provides two erase pulses instead of the single pulse used in the prior art. Only the selected cell or cells are initially pulsed in the positive direction by a selective erase pulse. After this pulse returns to zero, a second non-selective erase pulse in the negative direction causes removal of any wall charge remaining after the selective pulse. This non-selective pulse does not affect any cell which did not receive the initial erase pulse, because the nonselected cells have already been discharged in the negative direction.
A further advantage of the present invention is that its operating waveforms are such that the sustainer, the X-electrode drivers and the Y-electrode drivers are powered from a single d.c. voltage supply, thereby further reducing the number of required power supply voltages. As a result, the present invention substantially simplifies and reduces the problem of manufacturing, testing, packaging and cooling the electronic hardware associated with the power supplies - and sustainer and driver circuits.
The preferred sustainer of the present invention uses Metal Oxide Semiconductor Field Effect Transistor (MOSFET) devices in the circuitry driving the plasma panel. The MOSFET sustainer circuitry may be utilized in the interface and control circuitry without requiring extensive changes to the exisiting circuit.
The sustainer uses two high voltage - high current MOSFET transistors to supply the sustainer voltage waveform, which is a simple rectangular wave which requires no-additional shaping or pedestals for any of the operating modes. One of the transistors is connected to a high voltage power supply V_CC2, and the second.transistor is connected to ground. The two transistors have a common connection, which is the output of the circuit. When a MOSFET transistor is turned on, it acts like a switch to connect the common mode with either V_CC2 or ground, depending on which transistor is turned on. The circuitry of the sustainer controls the two MOSFETs, so that only one of them can be turned on at a time. Therefore, when the transistor connected to V_CC2 is turned on, it will charge the plasma panel to high voltage, and when the transistor connected to ground is turned on, it will discharge the panel back to zero volts.
The input to the sustainer circuit is a single open collector TTL logic gate. Therefore, only a single input to the circuit is required, in contrast to past bipolar systems which require two inputs, one controlling each of the two transistors. The only power source which the sustainer circuit requires, other than the high voltage _VCC2 which is being switched, is a single 12-volt, ground based supply voltage. Since the sustainer of this invention needs only to produce a simple rectangular wave, there is no need to produce intermediate voltage levels, such as were required by prior systems, to produce complex pedestal-shaped waveforms.
Since only the single 12-volt DC power supply is needed to bias the sustainer circuitry, the number of required power supply voltage is greatly reduced. As a result, the present invention simplifies the manufacturing, packaging, and cooling of the electronic circuitry associated with the power supplies and the sustainer and driver circuits.
Since the sustainer waveform is a simple rectangular wave, only a single logical input is necessary to drive the sustainer circuit. Since only one logic input signal is being used, which is either high or low, the possibility for improper phasing of the two MOSFET transistors in the sustainer, which could result in the destruction of at least one of the transistors, is completely eliminated. Despite the fact that only a single logic input is used, there are no limitations imposed by this type of system on the logic timing.
The use of MOSFET transistors in this circuit eliminates the classic thermal runaway problem that all bipolar sustainer designs have had in the past. MOSFETs do'not exhibit storage time phenomena, which is a significant delay between the time an input is supplied to the transistor and the time at which the transistor supplies an output. Because MOSFETs do not exhibit storage time phenomena, the switching delays are extremely short. This feature, and the fact that the circuitry of the sustainer will prevent both transistors from being turned on at the same time, assure that excess power, which was required to be dissipated in prior sustainer designs, is no longer present, so power dissipation for the transistors is no longer a significant problem. The present sustainer is designed so that the output voltage has a maximum slew rate, or rate at which the voltage level will rise to its peak or fall to zero, that is independent of the logic input timing. Therefore, excessive displacement currents that could cause noise which could mis-trigger the low voltage logic signals are avoided. This slew rate limit also minimizes the sustainer overshoot on the rise and fall of the sustainer waveform.
This leaves one problem area remaining in the sustainer and driver circuitry--the driver chips which are used to drive the electrodes in the plasma panel. Voltages supplied to the electrodes are of two types: sustaining and pulsing. The sustain voltages perform the sustain function described above. The pulsed voltages are usd to write, or turn cells "on", and to erase, or turn cells "off". It is during the switching operation that the pulsed voltages are generated, and the problems described above occur. The driver chips supply these pulsed voltages only to the cells to be written or erased. This selective supplying is the second function of the driver chips.
The present invention solves the problems inherent in the driver chips by adding to the circuitry two voltage pulser circuits, one for the X-axis, and one for the Y-axis. The pulser circuits are inserted between the sustain circuits and the drive circuits. The Y-voltage ' pulser circuit provides a positive pulse, and the X-voltage pulser circuit provides a negative pulse.
The voltage pulser circuits are used to turn the high voltage level supplied to the electrodes by the driver chips on and off, this high voltage level being turned off whenever the driver chips are not performing an addressing function, i.e., a write or erase function. The high level voltage is turned off by connecting the high level input of the driver chips to the ground input of the driver chips.
For normal sustain operation and during the time in write and erase operations when a pulsed voltage is not to be sent to the electrodes, the voltage pulser circuit connects the driver chip ground pin to the high voltage input pin. This has the effect of shorting the parasitic np and pn junctions, as well as the output transistors, making the chip circuitry appear to be a small resistance in series with two parallel diodes, the diodes connected in reverse polarity. The most obvious advantage is that the parasitic transistors are completely eliminated, and with them goes'the.problem of excessive power dissipation in the parasitic transistors.
A second effect of short circuiting the floating ground and the high voltage input of the driver chips is to eliminate notch dissipation power in the output stage of these chips by shorting the output transistors. Since the high voltage potential is no longer applied to the circuitry of.the chips during sustain operation, quiescent power dissipation is no longer a problem. Therefore, it can be seen that quiescent power, parasitic power, and notch dissipation power are eliminated during the sustain operation and the non-addressing portions of the write and erase operations, which generally are the bulk of the time the panel is in operation.
The level shifting boost power is also eliminated during sustain operation by the short circuit action of the voltage pulser circuitry. Since a separate sustainer circuit is used to provide the sustaining voltage input to the floating ground of the driver chips, the boost current generator is no longer used to perform this operation.
The low voltage logic power, which is a fairly negligible amount, remains as the only one of the five power components of the driver chips which is not eliminated or reduced by the present invention. Therefore, it.can be seen that the present invention eliminates most of the power which the driver chips were required to dissipate in earlier applications. The benefits of the present invention are made more apparent by the fact that the temperature rise in the chips caused by power dissipation with the use of the present invention is only a 3 to 5°C rise over the ambient temperature, compared to a 75°C increase without the present invention. By utilizing the present invention, the early burn-out problem of the Texas Instruments driver chips is substantially eliminated.
The voltage pulser circuit utilizes the MOSFET sustainer described above, using that circuit as a pulser circuit. The fast fall time of the driver chips which resulted in system noise generation is no longer a problem because the MOSFET sustainer being used for the voltage pulser circuitry has a slew rate control which is utilized to prevent the fast fall time inherent in the Texas Instruments chips. Since the voltage pulser circuit is supplying the high voltage level to the driver chips, by having the voltage pulser circuit go to its low state, the slew rate of the transition being controlled, the voltage supplied by the driver chips will fall only as fast as the slew rate controlled falling voltage of the voltage pulser circuitry.
The shorting of the ground pin and the high voltage pin of the driver chips during the sustain operation also has the effect of eliminating the problem of lowered voltage supplied to the electrodes because of the voltage notch. Since the driver chips' output stages are shorted, the voltage drop developed across these transistors is now limited to only a diode voltage drop, approximately 0.7 volts, as contrasted with up to 8.5 volts with the earlier system. During the time addressing pulses are being generated, the ground pin and the high voltage pin of the driver chips will not be shorted. Since the high voltage input is supplied by the voltage pulser circuit, the slew rate control will prevent the high current levels which caused the voltage notch. There will be some degree of voltage notch, but much less than that experienced without the voltage pulser circuit.
Since the voltage notch is reduced, less precise regulation of the power supply, less precise components, and more flexibility in system layout are permitted. Lower product cost will also result.
Lowering of the notch voltage also has another important implication. The present invention would allow the Texas Instruments driver chips to be used .to drive a 1024 x 1024 plasma panel, a significant step forward since the larger panel allows much more flexibility in creating graphic displays.
The final design defect of the Texas Instruments driver chips is the internal logic'error, which is solved by utilizing the voltage pulser circuit to bring the voltage output of the driver chip high. When a write function is to be performed on the plasma panel, the sustain pin (used for the distributed conditioning input) is brought high and the strobe pin (used for the address pulse input) is brought low, before the voltage pulser goes to its high state. By doing this, the output of the driver chip will simply follow the high voltage input from the voltage pulser circuit. The logic error is bypassed in this manner.
Further advantages include the provision for expansion to include operating modes and features which may be developed in the future. Should another manufacturer design and build a driver chip, that driver chip may well have operational characteristics different from the Texas Instruments driver chips. The drive electronics improvements of this invention provide transparency to these different characteristics.
The invention is described further hereinafter, by way of example, with.reference to the accompanying drawings, in which:

Figure 1 is a block diagram of a.system for driving an AC plasma panel;
Figure 2 illustrates the waveforms generated by the X-sustainer, the X-electrode driver, the combination waveform generated by the X-sustainer and the X-electrode driver, the same waveforms for the Y-sustainer and the Y-electrode driver, and the applied cell voltage X - Y;
Figure 3 is a schematic diagram of the sustainer and driver circuitry using the MOSFET sustainer circuit of the present invention;
Figure 4 is a symbolic representation of a MOSFET transistor showing the output leads.
Figure 5 is a schematic diagram of the switching circuitry for a single output of the Texas Instruments driver chips, used in the driver circuits of Figure 4;
Figure 6 shows the logic error inherent in the Texas Instruments driver chips of Figure 5, and the logic input to the pins of the chips which will cause the error;
Figure 7 is a block diagram of a plasma display panel and its sustain and drive circuitry, containing the present invention;
Figure 8 is a schematic diagram of the Y-axis sustain, voltage pulser, and driver circuitry for the circuit shown in Figure 7;
Figure 9 is a schematic diagram of the X-axis sustain, voltage pulser, and driver circuitry for the circuit shown in Figure 7;
Figure 10 is a schematic diagram of the circuit for deriving a floating V_CC1 from a ground-based V_CCl power supply shown in Figures 8 and 9;
Figure 11A is a schematic diagram of a single output stage of the Texas Instruments driver chip as Texas Instruments intended it to be implemented;
Figure llB is a schematic diagram of a single output stage of a Texas Instruments driver chip as it was actually integrated;
Figure 11C is a schematic diagram of a single output stage of a Texas Instruments driver chip with the voltage pulser circuit of the present invention being used to short the ground and high voltage inputs of the driver chip;
Figure 12 is a waveform diagram showing the rise and fall times of the Y-driver output shown in Figure 8 as controlled by the Y-pulser output and the logic control signals YAPD and YAPP;
Figure 13 is a waveform diagram showing rise and fall times of the X-driver output shown in Figure 9 as controlled by the X-pulser output and the logic control signals XAPD and XAPP; and
Figure 14 is a waveform diagram showing the logic failure of Figure 6, and the manner in which it is remedied utilizing the present invention.

Figure 1 shows the improved circuitry of the present invention, which is used for controlling a plasma panel 70. A power supply 2 supplies three levels of voltage: V_CC2, which is typically 90 to 100 volts; V_CC1, typically 12 volts for CMOS logic; and V_CC3, which is typically 5 volts for TTL logic. These three voltage levels are a a significant reduction over the seven or more different power supply voltages typically required to operate the prior art systems. In addition, as will be apparent from the detailed description below, no separate floating power supplies are needed and the overall power requirements of the system are quite modest compared to prior art systems.
The plasma panel 70 is typically a 512 by 512 AC gas plasma panel, and is available commercially. A 512 by 512 panel has X and Y electrodes which form a matrix, which is composed of 512 X-axis electrodes and 512 Y-axis electrodes. These electrodes cross to form 262,144 intersection points or cells which are independently addressable to allow the display of two-dimensional information on the panel. The X-axis has a plurality of X addresses, with each X electrode being associated with an X address. The Y-axis has a plurality of Y addresses, with each Y electrode being associated with a Y address. The operations being performed on the plasma display panel 70 are, as described above, the write, erase, sustain, and bulk-erase functions.
. To data, the most sophisticated circuitry used to drive a plasma panel is that disclosed in U.S. Patent No. 4,180,762, to Larry F. Weber. That invention has been assigned to the assignee of the present invention, and is hereby incorporated herein by reference.
A computer and control circuitry standard in the art are used to supply the circuit shown in Figure 1 with information describing the operations to be performed, and the locations to be addresses. For the X-axis, this information includes an inverse X-Address Pulse XAP', and an X-sustain XS Signal, both of which are configured to implement one of the four functions of the panel. The X-Address Input 92 is supplied to the circuit to define which locations on the X-axis will be addressed.
Information supplied to the circuit to control operations on the Y-axis include a Y-sustain YS Signal and an inverse Y-Address Pulse YAP, both of which are configured to implement one of the four basic functions of the panel. The circuitry which is used to supply the YS, YAP, XAP', and XS pulse trains, and the address location information (Y Address Information and X Address Information), is of the same type as that used by past systems to control an AC plasma panel.
The circuitry for exciting any one of the plurality of intersections of the X-axis and Y-axis electrodes in the panel 70 is provided by an X-axis driver circuit 250 and a Y-axis driver circuit 150, respectively conncected to the X-axis electrodes and the Y-axis electrodes. The addressing of individual cells of the panel 70, to accomplish selective writing and erasing of these cells, is controlled by an X-address pulse XAP and a Y-address pulse YAP, supplied from a waveform ROM (Read Only Memory, not shown) through a pair of level shift circuits 240 and 140, which are required, since the driver circuits 250 and 150 operate on floating grounds. The X-address information and Y-address information is supplied to the driver circuits 250 and 150 through a pair of level shift circuits 93 and 91, on lines 96 and 95 respectively, and identifies which cells on the plasma panel 70 are to receive the X and Y address pulses. The level shift circuits 240, 140, 93 and 91 are inverting circuits, and thus provide the signals XAP, YAP, and those on lines 96 and 94, respectively in response to the inputs XAP', YAP', X-Address Information, and Y-Address Information. The X-level shift circuitry used to obtain floating signals is a common level shift circuit known in the past, and generally inverts the signal. It is commonly either a transformer circuit or an optical isolator circuit.
A pair of sustain circuits 210 and 110 are used to provide the sustain signal to the driver circuits 250 and 150, respectively. Past sustainer designs of the bipolar type may be utilized advantageously, but to take full advantage of the possible improvements to the driver circuitry the preferred embodiment utilizes the new MOSFET sustainer described below.
The X-axis sustain circuit 210 is controlled by an X-sustain signal XS, and the Y-axis sustain circuit 110 is controlled by a Y-sustain signal YS. The outputs of the sustainer circuits 210, 110 become floating grounds 260, 160, respectively, upon which the driver circuits 250, 150, respectively, are based. Float circuits 211 and 111 are used to supply floating supply levels of V_CC1, the low voltage used to power the logic circuitry, and V_CC2, the high voltage used to drive the panel, to the circuits 250 and 150, respectively.
The nature of the plasma panel is such that sustain voltages must be applied to the panel borders as a means for priming the plasma cells so that the panel may be reliably written. This priming produces free electrons and gas ions which enable a write operation to be carried on with complete accuracy. An X-border sustainer circuit 86 is connected to the X-axis borders, and a Y-border sustainer circuit 88 is connected to the Y-axis borders. The X-border sustainer circuit 86 and Y-border sustainer circuit 88 are driven by pulse trains generated by logic timing and control circuits 82 and 84, respectively.
The X-axis driver circuit 210 uses Texas Instruments SN75501 integrated circuit driver chips, and the Y-axis driver circuit 110 uses Texas Instruments SN75500 integrated circuit driver chips..The SN75501 chip has an inherent sustaining capability, and may be used to eliminate the X-sustain circuit 210, the float circuit 211, and the level shift circuits 240 and 93, as disclosed in the Weber patent incorporated by reference above. Due to the power dissipation problems in the driver chips described above, this is not a satisfactory arrangement, so the X-sustain circuit 210 is retained.
The operation of the plasma panel 70 to perform the sustain, write, erase, and bulk-erase functions is described by the waveforms shown in Figure 2.
The X-sustainer waveform comprises a continuous series of consistently timed rectangular waves which range between AC zero and V_CC2' The Y-sustainer waveform is also a series of rectangular waves, times so as to have an opposite phase relationship from the X-sustainer waveform.
The applied cell voltage Y - X for the sustain function is thus an alternating waveform, as shown in Figure 2. During the sustain function, the X and Y drivers 250, 150 are not pulsing, so that voltages supplied to the electrodes, Y-sustainer + driver to the Y electrodes, and X-sustainer + driver to the X-electrodes, are generated entirely by the sustainers 210, 110.
As noted above, the operation of the plasma panel requires that in order to sustain an "on" cell, a voltage -difference of around 2Vcc2 must be seen in an alternating waveform between the intersecting X and Y electrodes.
As is apparent in the applied cell voltage Y - X, the voltage across the X and Y intersecting electrodes varies from ^V _CC2 to -V_CC2, which permits the gaseous excitation between said intersecting electrodes to be sustained.
In order to perform a write operation, a cell which was preciously "off" is turned "on". The particular cell is identified by the X-addressing information and the Y-addressing information, and the pulses are generated in the driver circuits 250, 150 by XAP and YAP, respectively. The waveforms generated by the sustainer and driver circuitry are shown in Figure 2 in the segment for a write function.
The voltages generated by the sustainer circuits 210, 110 for a write function are identical to those generated for a sustain function. However, the driver circuits 250, 150 generate pulses as shown which are supplied only to cells to be written, causing the composite waveforms X-sustainer + driver and Y-sustainer + driver to be supplied to the selected cells. The resulting applied cell voltage Y - X causes a selected cell to be turned "on", while all non-selected cells are supplied with the sustain signal.
In order to perform an erase operation, a cell which was preciously "on" is turned "off". The particular cell is identified by the X-addressing . information and the Y-addressing information The waveforms used for performing the erase function are also shown in Figure 2.
The voltages generated by the sustainer circuits 210, 110 for the erase function are identical to those generated for a sustain function. However, the driver circuits 250, 150 generate the pulses shown at the same time, causing the applied cell voltage Y - X to be supplied to selected cells. These selected cells will be turned "off", while all non-selected cells are sustained.
The erase function is wholly novel in this invention with a combination of waveforms producing two pulses instead of the single pulse used on prior art devices. This is made possible by causing only a selected cell or cells to be pulsed in the positive voltage direction by the selective rectangular wave pulse. After this selective pulse has returned to AC zero, a non-selective erase pulse is generated in the negative direction causing removal of any wall charge remaining after the selective pulse. This non-selective erase pulse does not affect any cell which did not receive the selective positive pulse because the non-selective cell have already been discharged in the negative direction.
The bulk-erase function is used to turn all "on" cells in the plasma panel 70 "off" in one operation. Because all the cells are affected, the bulk-erase operation is non-selective and is therefore performed by the sustainer circuits 210, 110. The driver circuits 250, 150 do not generate any pulses, but merely relay the sustainer circuits 210, 110 signals to the electrodes. The applied cell voltage Y - X shown in Figure 2 for the bulk-erase function is generated, causing all cells in the panel 70 to be erased. The bulk-erase, like the other functions performed by the circuitry of the present invention, requires no pedestal waveforms, but only single rectangular waves. This is a significant advantage in that the circuitry is greatly simplified, and only a single high voltage Vcc2 is required.
Figure 3 shows the circuitry for the drive electrodes shown in block form in Figure 1, with each component of Figure 1 shown enclosed by dotted lines. The Y-sustainer circuit 110, and the level shift circuits for the Y-axis circuitry 111, 140 are not shown, but they are identical to and operate in the same way as the X-sustain.circuit 210, and the level shift circuits for the X-axis circuitry 211, 240. The sustain circuit shown is the MOSFET sustainer of this invention, but a conventional bipolar sustainer could be used in the circuit shown.
The X-driver chips XDl - XD16 are the Texas Instruments SN75501 chips, and the Y-driver chips YDl - YD16 are the SN75500 chips. These driver chips each drive 32 electrodes, so 16 chips are necessary for both the X-axis and the Y-axis of a typical 512 x 512 panel. These driver chips each consist of semiconductor structures diffused into a silicon substrate and overlaid with metal and glass films. Ordinarily, the circuitry of such an integrated circuit is embedded in a substrate so that the circuitry is referenced to the substrate voltage potential and so that the circuitry may be adjustably biased by adjusting the substrate potential. The X-driver chips XDl - XD16 have their substrate or ground inputs tied together to the floating ground 260. The Y-driver chips YDl - YD16 are tied to the floating ground 160.
The outputs of the driver chips are normally low, i.e., their outputs are connected through their output transistors to the floating grounds 260, 160. The sustainer waveform appears at the floating grounds 260, 160 and is in turn interconnected to the electrodes. When it is desired to address the plasma panel 70, the selected output of the driver chip is turned on by the XAP or YAP signal. This raises the potential of that particular output to a voltage level equal to VCC2 above (for the Y-axis) or below (for the X-axis) the substrate potential. In this manner, selected X electrodes are driven with the X-sustain + X driver waveform, and selected Y electrodes are driven with the Y-sustain + Y driver waveform (Figure 2).
The X-axis driver circuit 250 generates the .negative pulses, and the Y-axis driver circuit 150 generates the positive pulses sent only to electrodes . selected by the address information on lines 96, 94, respectively.
In order to accomplish selection of particular plasma panel electrodes for selective signals from the driver circuits 250, 150, it will be understood that these driver circuits 250, 150 are supplied with address data. The data entry ports of these on lines 96, 94 is serial, such that the data is shifted into a register within the device and then strobed onto the device outputs at the appropriate time. The logic system for formatting this serial data, routing it to the appropriate electrode driver and providing timing control to strobe the driver for addressing may be the same as that used to control applicant's device disclosed in the Weber patent incorporated by reference above.
The driver circuits 250, 150 are connected to the sustainer circuits 210, 110, respectively by the floating grounds 260, 160, respectively. Therefore, the summations of the signals from the sustainer circuits 210, 110 and the pulses generated by the driver circuits 250, 150 are sent to selected cells, and only the signals from the sustainer circuits 210, 110 are sent to non-selected cells.
Since the substrates of driver circuits 250, 150 are connected to the floating grounds 260, 160, the driver circuits must be supplied with high and low voltage power based on the floating grounds 260, 160. This is done by using float circuits 211, 111, which completely eliminate the need for floating power supplies.
The float circuit 211 is used to supply the X-driver chips _XDl - _XD16 with floating levels of power V_CC1 and V_CC2. A diode 226 and capacitor 230 will supply a floating V_CC2 at terminal 234 with reference to terminal 236, which is then supplied to the X-driver chips XDl - XD16 on line 252 with respect to the floating ground. The floating V_CC1 is supplied by the use of a diode 224 and a capacitor 228, which supplies a floating V_CC1 at terminal 232 with respect to the floating ground 260. The line 254 is connected to the logic level voltage input pin of the chips, and to the sustain pin of the chips, which is always high in this application, since an external sustainer is used. The line 252 is connected to the high voltage input pin of the chips.
The float circuit 111 operates in the same way, except the SN75500 chips have no sustain pin so line 154 is connected only to the logic level voltage input pin of these chips. The capacitors in float circuits 211, 111 all have their negative terminals connected to the substrates of the driver circuits 250, 150 and therefore, when the floating grounds 260, 160 are at ground potential, the substrates of the respective driver circuits 250, l50 will be at ground potential, as would be the negative terminals of the capacitors in the float circuits 211, 111.
Since the capacitors are connected with their positive terminals through the diodes to the voltage sources V_CC1 and V_CC2, they are charged from those voltage sources when the substrates of the driver chips are at ground potential. When the floating grounds 260, 160 are high (at V_CC2 potential), the positive terminal of the capacitors will be at the potential'of 2V_CC2 so that the diodes are reversed biased and no current flows. In'this state, power for the internal circuitry of the driver chips is supplied by the discharging capacitors.
HIgh voltage source 58 supplies a direct current voltage output having a voltage less than the discharge threshold voltage of panel 10. In this preferred embodiment, the voltage output of source 58 is 90 volts.
The X-axis sustainer circuit 16 is connected to voltage source 58, so that power for X-axis sustainer electrical signals (as shown by waveform 30 of Figure 2) is provided by the output of source 58.
The diodes and capacitors electrically connect the driver chips to the voltage sources, so that power for driver electrical signals (Figure 2) is provided by the output of the power supply 2 and the capacitors are electrically connected to the diodes so that: the capacitors may receive power from the power supply 2 when the floating grounds 260, 160 are not at the V_CC2 level, (waveform 30), and the capacitors may deliver power to the driver chips when the floating grounds 260, 160 are at the V_CC2 level.
It is important that the capacitors be sufficiently large such that they are not significantly discharged by the power requirements of the driver chips when the diodes are reverse biased so as to isolate the capacitors from the power supply 2. Also, the current drain on these capacitors must be low enough that these capacitors are not excessively large components. The permissible variation in supply voltage for a driver chip is between 10.8 volts and 13.2 volts for the low voltage supply, and as much as a volt in either direction in the high voltage supply, without exceeding the addressing margins of a typical plasma display panel. Calculations indicate that if the capacitors are one microfarad each, the voltage drop experienced in worst case conditions (when all 32 electrode connected lines of a chip are transmitting signals at the same time) causes a change in capacitor voltage of .12 volts, which is well within the acceptable limits.
The sustainers 210, 110 provide an output to the floating grounds 260, 160, respectively, of either 0 volts or V_CC2, As sgated earlier, while the sustainers 210, 110 can be either the prior art bipolar devices or the MOSFET devices of the present invention, the latter are preferred.
The X-sustainer circuit 210, shown in Figure 3, includes two high--voltage - high- current MOSFET transistors 278 and 276 which are connected to the floating ground 260 (transistor 276 is connected to the floating ground 260 through a diode 284), with the pull-up transistor 278 connected to V_CC2' and the pull-down transistor 276 is connected to ground. The pull-up transistor 278 is used to charge the plasma panel to voltage V_CC2' the pull-down transistor 276 is used to discharge the panel to zero volts. Both transistors 278 and 276 are N-channel enhancement type MOSFETs, the connections to which are shown in Figure 4 as a gate, a drain, and a source. Whenever the gate of a MOSFET is at a high potential with respect to the source, the transistor will conduct, connecting the drain and the source so that it operates as a closed circuit. The gates of the transistors 278 and 276 are driven by a single open collector TTL logic gate 280, such as an SN7417 or an SN7416.
The X-sustain circuit 210 requires only a single, low voltage, ground based power supply V_CC1. It is significant that no other power supplies are used. A further feature of the MOSFET sustainer is that only one logic input signal is needed, that signal being XS. With the single logic input XS in the present device, there is no possibility for improper phasing, since only one of the transistors can be turned on at a time. This prohibits simultaneous conduction through both of the transistors 276 and 278, which would conduct high voltage directly to ground through the transistors, and possible failure of at least one of the transistors 276, 278.
The use of MOSFET transistors in this design eliminates the classic thermal runaway problem that all bipolar sustainer devices have had.in the past. Bipolar transistors usually have an increased storage time whenever the temperature of the transistors has increased. This increased storage time, which is the time between the application of an input to the transistor and the time when the transistor supplies the desired output, may cause both the upper and lower transistors to conduct at the same time. This will result in excess power which must be dissipated by the transistors, which will cause a further increase in temperature. This condition will eventually result in thermal runaway of the transistors, and may result in the destruction of at least one of the transistors. This undesirable positive feedback characteristic is absent in MOSFET transistors, which do not exhibit storage time phenomena and have very short switching delays.

Operation of the MOSFET Sustainer Circuit

The gate of the pull-down transistor 276 is driven by the open collector TTL logic gate 280 and biased by the resistor 282. When the open collector output transistor of the logic gate 280 is non-conductive, the resistor 282 will pull the gate of the pull-down transistor 276 to the level V_CCl' which will cause the pull-down transistor 276 will pull the floating ground 260 to ground potential through a diode 284.
It is desirable that, when either of the transistors 276 or 278 is turned on, the output to the floating ground 260 not rise or fall too rapidly, since a rapid rise and fall cound result in excessive displacement current, causing noise that could possible mis-trigger low voltage logic signals of the system, particularly those in the driver chips. Therefore, the sustainer of the present invention has an output voltage supplied to the floating ground 260 which has a maximum slew rate independent of logic input timing. This slew rate limit also minimizes the sustainer overshoot on the rise and fall of the sustainer output.
A capacitor 286 and a resistor 282 control the fall time slew rate of the sustainer output. Thus, as the sustainer output falls, it forces displacement current through the capacitor 286 and the resistor 285. Since most of this current must flow through the resistor 282; as the output falls, the voltage drop across the resistor 282 causes considerable less than the value of V_CC1 to be provided at the gate of the pull down transistor 276. During this output fall, the gate of the pull-down transistor 276 is typically at a constant level of 5 volts. This constant 5 volt level causes the transistor.276 to act as a constant current source, so that the plasma panel 70 is discharged with a constant current, which results in a linearly decreasing ramp voltage. Since a linearly decreasing ramp voltage will also cause constant displacement current to flow through the capacitor 286, which condition is necessary for the constant 5 volts at the gate of the transistor 276, the constant displacement current is maintained by the ramp voltage which it creates.
Thus, the characteristics of the pull-down transistor 276 and the values of the resistor 282 and the capacitor 286 determine the slew rate of the falling output voltage.
The state of the.pull-up transistor 278 is controlled by the action of the pull-down transistor 276. When the pull-down transistor 276 conducts, a diode 284 is forward biased. Since the diode 284 has a voltage drop of typically 0.6 volts, the gate of the pull-up transistor 278 will be pulled down through a diode 291 to a voltage which is more negative than the source of the pull-up transistor 278. The diode 291 conducts to bypass a resistor 289 to prevent delay in pulling down the gate of the pull-up transistor 278. If the resistor 289 is not bypassed, the pull-up transistor 278 could conduct for a short time after the pull-down transistor 276 begins to conduct, possibly causing adverse power dissipation.
Because the pull-up transistor 278 has a very fast switching time, e.g., 5 ns, it is biased so that it will stop conducting almost as soon as the pull-down transistor 276 conducts, so that the transistors 276 and 278 may not both conduct at the same time. This quick turnoff is of substantial significance in reducing the power dissipated in the transistors 276 and 278.
While the pull-down transistor 276 is conducting, a capacitor 290 is charged to a level of approximately 11 volts by the power supply V_CC1 at terminal 272 through a diode 292. The capacitor 290 displacement current flows through the diode 284 and the pull-down transistor 276 to ground when the output of the logic gate 280 goes to a low level and turns the pull-down transistor 276 off, the diode 284 is immediately back- biased by the charge on the capacitor 290. The gate of the pull-up transistor 278 is then biased positive relative to the voltage at its source by the resistors 288 and 289 and the capacitor 290, causing the pull-up transistor 278 to conduct.
When the pull-up transistor 278 is turned on, the only paths provided for discharge of the capacitor 290 is the leakage currents through the diodes 284 and 292, the gate of the pull-up transistor 278, and the drain of the pull-down transistor 276. This current amounts to no more than a few microamps. Therefore, the capacitor 290 acts as a floating power supply for the gate of the pull-up transistor 278, holding the gate at a constant voltage level. The capacitor 290 will remain charged for a period much longer than the cunductive period of the pull-up transistor 278 for normal sustain operation.
The greatest amount of charge drawn from the capacitor 290 is drawn when the pull-down transistor 276 first becomes non-conductive and the pull-up transistor 278 first becomes conductive, since, at this time, the capacitor 290 charges the gate capacitance of the pull-up transistor 278 and the drain capacitance. of the pull-down transistor 276. The value of the capacitor 290 is selected so that it is considerably higher than the sum of these two capacitances. A typical value of 10 microfarads for the capacitor 290 has been found to be much larger than is necessary to satisfy these current supply needs.
When the pull-up transistor 278 is turned on, it is controlled in a way that limits the slew rate of the voltage output to a linear rising ramp. This rate of rising is controlled by the resistor 288, the source-to-drain capacitance of the pull-down transistor 276, the voltage across the capacitor 290, and the characteristics of the pull-up transistor 278. When the pull-down transistor 276 is turned off, the gate of the pull-up transistor 278 is pulled high by the resistor 288 and the capacitor 290, as stated earlier, so that the gate is at a voltage level which is somewhat higher than that present at its source. This will cause a constant current to flow out of the source of the pull-up transistor 278, which will charge up the plasma panel at a constant rate. Some of this current will also flow through the capacitor 290 and the resistor 288, charging the drain-to-source capacitance of the pull-down transistor 276. Since this capacitance is charged entirely by the current that flows through 'the resistor 288, it is apparent that if the output of the sustainer rises too fast, the voltage across the drain of the pull-down transistor 276 will not rise as fast. The gate-to-source voltage of the pull-up transistor 278 will be reduced, causing the current from the source of the pull-up transistor 278 to also be reduced and thereby preventing the output of the sustainer from rising too rapidly. A similar situation occurs if the sustainer output rises too slowly, but in that case, the gate-to-source voltage of the pull-up transistor 278 will increase to compensate.
Therefore, it can be seen that when a switching operation occurs, the transistor which is turning off will turn off immediately. The transistor which is turning on is controlled so that the voltage supplied to the floating ground 260 will either rise or fall in a linear ramp function, thus preventing current surges and resulting noise from interfering with the performance of the system.
A possible problem with any feedback-type circuit using MOSFET transistors is that there may be oscillations when the sustainer is in transistion between the high and low states. These oscillations are very high frequency, too high to adversely affect the response of the plasma panel, but at a frequency which may cause excessive power dissipation in the MOSFET transistors. The circuit shown in Figure 3 includes a feedback circuit used to eliminate these oscillations by limiting the slew rate of the sustainer circuitry.
This circuit includes a feedback resistor 289 in the gate lead of the pull-up transistor 278. Since the resistor 289 would slow the response of the pull-up transistor 278 when its gate is pulled down, it is bypassed by a diode 291. The diode 291 will bypass the resistor 289 only when the pull-down transistor 276 is turned on. The diode 291 is a low capacitance diode to prevent high frequency oscillations from causing the resistor 289 to be bypassed.
The pull-down transistor 276 may also oscillate unless protective circuitry is provided. A resistor 285 is connected in series with the capacitor 286 to prevent oscillations in the pull-down transistor 276. The combination of the resistors 285 and 289 and the diode 291 prevents the transistor 276 and 278 from oscillating without otherwise affecting system performance.
The Y-sustain circuit 110 is identical to the X-sustain circuit 211 described above, and functions in the same way. The circuit of Figure 3 is vastly improved over the prior art, but one significant problem remains. This problem is the poor operational characteristics of the Texas Instruments driver chips.
Figure 5 shows the schematic diagram for a single output stage in a Texas Instruments driver chip used in the driver circuits 250, 150 (Figure 1) to drive the electrodes in the plasma panel 70. Each output stage is designed with two DMOS transistors, pull-down transistor 301 and pull-up transistor 301, having a common connection 325. For a sustain function, pull-down transistor 301 will be turned on, so that the output 325 will be supplied the voltage level of the output from a sustain circuit, supplied to terminal 294. To address a cell, the logic signal input at 298 will go from 0 to 1, and will cause the pull-down transistor 301 to turn off and the pull-up transistor 302 to turn on. When pull-up transistor 302 is on, the output 325 is connected to terminal 296, which is the high voltage input of the driver chip. Capacitors 311, 312, and 313, and inverter 320, and a Zener diode 322 are used to properly bias and operate the system. A transistor 305 and a current source 300 are used to switch from the low output to the high output. The current source 300 is a bi-level current source, triggered by the logic input 298. The normal current supplied by the current source 300 is 10 microamps, but when the logic input 298 indicates that the circuit is to switch to the high level, the current is boosted to 2 mA for 600 nS. The effect of this boosted current is to turn the transistor 302 on fairly quickly, but at a fairly large cost in terms of power dissipation.
The SN75501 chip has a logic error which will result in this boost current not being applied to the output stage for certain combinations of inputs to the sustain pin (used for a distributed conditioning input) and the strobe pin (used for the addressing input). These pins, not shown in the drawings, are inputs to the driver chip, and are described in Texas Instruments data books. Figure 6 shows the sequencing of the logic inputs to the sustain and strobe pins of the driver chip, and the output which will result. It can be seen that when the strobe is high at a time when a sustain pulse is applied, the boost current is properly applied and the output will be the desired rectangular wave. Since the rise time, which varies from chip to chip, is typically 5 to 10 microseconds, and an operation performed on the panel may take well less time than 2 microseconds, the pulse will not reach its peak while the operation is being performed. The result is an operation which does not properly perform the function.
The above-described problems are solved by controlling the supply of high level voltage to the driver chips contained in driver circuits 250, 150 (Figure 1). The driver chips, Texas Instruments SN75500 and SN75501, utilize the high voltage supplied to them only when pulsing during write and erase operations. A detailed description of the pulsing operation used to perform write and erase operations is contained in the U.S. patent application entitled "Constant Data Rate Brightness Control for an AC Plasma Panel" , by Joseph .T. Suste, Serial No. , filed June 12, 1981, and that specification is hereby incorporated by reference herein.
The present invention removes the high voltage level from the high voltage input lead 296 (Figure 5) of the driver chips, and ties this high voltage input lead of the driver chips to the ground lead 294 of the driver chips. By controlling the times when high voltage is supplied to the driver chips, addressing . operations can still be performed. During all times when the high voltage pulse is not required to perform a write or erase operation, the high voltage input of the chips will be tied to the ground of the chip. By typing these two inputs together, most of the power dissipation problems of the chip are eliminated. The manner in-which the other problems inherent in the driver chips are eliminated will become apparent later.
The operation of switching the high voltage input to the driver chips on and off and grounding the high voltage input of the chips to the ground of the chips when the high voltage input is turned off is performed by voltage pulser circuits. These voltage pulser circuits are of the MOSFET sustainer type, described above.
Figure 7 shows the voltage pulser circuits 170, 270 of the present invention installed into the circuit of Figure 1. Float circuits 213, 215 and 111 are used to supply the voltage pulser circuits 170, 270 with floating levels of V_CC1 power.
The voltage pulser circuits are controlled by two logic signals, the X-Address Pulse to Pulser XAPP and the Y-Address Pulse to Pulser YAPP. These pulses are suppled via level shift circuits 141, 241. The address pulses supplied to the driver circuits 150, 250 are now labeled Y-Address Pulse to Driver YAPD and X-Address Pulse to Driver XAPD; these pulses perform the same functions they performed in the circuit of Figure 1.
Figure 8 is a schematic diagram of the Y-sustain circuit 110, the Y-voltage pulser circuit 170, and the Y-axis driver circuit 150, with the various components of Figure 7 shown in dotted lines in Figure 8. The Y-sustain circuit 110, the float circuit 111, and the level shift 140 operate as they have in circuits not utilizing the voltage pulser circuit 170. For a further description of these circuits, see the above-incorporated application entitled "Constant Data Rate Brightness Control For An AC Plasma Panel".
The high voltage output of the float circuit 111 is on line 134. This high level voltage was supplied directly to' the driver chips on line 152 in applications not using the-voltage pulser circuit 170 (Figure 1). The voltage pulser circuit 170 acts to control switching of the high level voltage on line 134 to the driver chips on line 152.
When YAPP is at a logic level of 1, the control circuitry 172 will cause the pull-up transistor 176 to connect the high voltage supplied on line 134 to the positive voltage input of the circuit 150 on line 152 and will cuase the pull-down transistor 174 to be non-conductive. When YAPP is at a logic level of 0, the control circuitry 172 will cause the pull-down transistor 174 to be conductive, and the pull-up transistor 176 to be non-conductive, switching off the high voltage supplied by the line 134 and connecting the positive voltage input 152 of the driver circuit 150 to the floating ground 160, which is the ground input for the driver circuit 150. This later condition exists during sustain operations, when YAPP will be at a logic level of 0, so the high voltage will not be supplied to the driver chips. Even during write or erase operations, the high voltage will not be supplied to the driver chips during the entire function; rather, the high voltage will be supplied to the driver chips only during the actual time that a pulsing operation utilizing this high voltage is occurring. In this way, it can be seen that the Y-voltage pulser circuit 170 is itself performing the pulsing operation which the Y driver chips performed in earlier applications. Since the transistors 176, 174 in the Y-voltage pulser circuit 170 need not meet the same constraints imposed upon Texas Instruments in the development of their integrated circuit, and because these transistors are outside of the case of the driver 150, they do not have any , power dissipation problems. Thus, the addition of the voltage pulser circuit 170 will not adversely affect the system in any way.
The circuitry controlling the X-axis driver 250 is shown in Figure 9, and it differs from that of the Y-axis circuitry in that the X-axis driver circuit 250 includes SN75501 driver chips, which are designed for negative pulsing. In negative pulsing, instead of adding a pulse on top of the sustainer waveform in order to address the panel, a voltage is subtracted from the sustainer waveform. The X-sustainer 210 is exactly the same as the Y-sustainer, and it functions in the same manner.
A float circuit 213 is used to supply the X-voltage pulser circuit 270 wiht a floating V_CCl, and to supply the pull-down transistor 274 with the floating -V _CC2 voltage level. The -V_CC2 floating voltage is supplied by a capacitor 278 and a diode 279 to line 247. The floating V_CC1 is referenced to line 247, and is supplied to the X-voltage pulser circuit 270 on line 281 by a converter 217, which will be described in detail below. A second float circuit 215 is used to supply the driver circuit 250 with a floating V_CC1 on line 254 with reference to line 260. This second float circuit 215 contains a converter 219 which is identical to the converter 217.
A schematic for this converter is shown in Figure 10. Resistors 290 and 292 are used to bias an FET 280, "one of the resistors 290 being variable. Additional components of the circuit are a diode 282, a Zener diode 286, and a capacitor 284. The FET 280 acts as a constant current source and will therefore be adjustable by the resistors 290 and 29.2. The voltage supplied at the outputs is floating with respect to the grounded V_CC1 input. Although this circuit is the preferred embodiment, any circuit which will supply a floating level of V_CC1 is acceptable.
The operation of the X-voltage pulser circuit 270, shown in Figure 9, is much the same as the operation of the Y-voltage pulser circuit 170 described above. However, since the X-axis circuitry is designed for negative pulsing, when the pull-down transistor 274 is conductive, and the pull-up transistor 276 is non-conductive, line 260, the negative voltage input of the driver chips (supplied to the ground input of the chips), is supplied with a voltage level V_CC2 lower than the level on line 252, the floating ground of the driver chips (supplied to the high voltage input pin of the chips). This -V _CC2 is applied only during the addressing operation. The pull-up transistor 276 is rendered conductive, and the transistor 274 non-conductive, except when address pulses are needed during an erase or write operations.
Therefore, for both the X and Y axis driver circuits, 250, 150, during operation of the system when voltage pulses are not needed, the negative voltage input 260 and the floating ground 252 to the X-driver circuit 250 will be shorted together by the X-voltage pulser circuit 270, and the positive voltage input 152 and the floating ground 160 to the Y-driver circuit 150 will be shorted together by the Y-voltage pulser circuit 170.
Referring again to Figure 5, two parasitic transistors 303 and 304 are shown. The desired circuit for the Texas Instruments driver chips includes a pair of clamp diodes, which are shown in Figure llA as D303 and D304. The diode D303 would prevent the output from falling lower than the level of the negative voltage input 260, which was connected to terminal 294. The diode D304 functions to prevent the output 325 from rising to a level higher than that.of the floating ground input 252, which is connected to terminal 296. In the process of fabricating the diodes D303 and D304, the parasitic bipolar transistors 303 and 304, shown in Figure 11B, were created. The present invention connects the high voltage chip input 296 to the ground input 294, when the system is not pulsing, so that the circuit shown in Figure 11C is the net result. The terminals 294 and 296, connected together, are shown as the terminal 295 in Figure 11C. These terminals 294, 296 are shorted, as described above, by the pull-down transistor 174 of the Y-voltage pulser circuit 170 (Figure 8), or by the pull-up transistor 276 of the X-voltage pulser circuit 270 (Figure 9). The resulting circuit of Figure 11C has a resistance 308, representing the inherent resistance of the diodes D303, D304, connected in series with a pair of ideal diodes, which are connected in parallel, in reverse polarity. These diodes are the diodes D303 and D304, desired in the Texas Instruments chip. The other junctions of the transistors 303 and 304, shown in Figure 11B, are eliminated from the circuit, because they are shorted out by the shorting of terminals 294 and 294. Therefore, power dissipation problems of the parasitic transistors are completely eliminated except during the relatively short period-of time that address pulses are being generated.
A second problem which is solved by shorting the terminals 294 and 296 together is the elimination of the notch dissipation power during the time the circuit is not pulsing. During this time. there is no longer a voltage drop across the pull-up and pull-down transistors 301, 302 in the integrated circuit chip. Even when the circuit is pulsing during a write or erase operation, the voltage pulse has a maximum slew rate determined by the voltage pulser circuits 170, 270. Since this slew rate control will limit the amount of current flowing through the transistors 301, 302 in the driver chip, the voltage drop across these transistors is substantially reduced.
Since the high voltage input and the ground of the driver chips are shorted during all operations other than when a pulse for an erase or write function is occurring, the system-will draw no quiescent power. .Since this power is not drawn by the chip, it does not have to be dissipated within the chip. In addition, since circuitry external from the chip is performing the sustain and pulse operations, the number of times that the high level boost current of the current generator 300 (Figure 5) would be required are greatly reduced, thus greatly reducing the level shifting boost power which would normally have to be dissipated within the chip. This is the reason the X-sustain circuit 210 is used even though the SN75501 chip has sustaining capability.
Therefore, during sustain operation and non-pulsing portions of write and erase operations, the only power dissipated by the chip is low voltage logic power. Therefore, even if the system is operating in a 100% addressing rate, the only time when power will be dissipated by.the chip is during the actual pulsing period, which is approximately 10% of the overall.time. Therefore, approximately 90% of the power dissipated in the chip is eliminated.
The method of eliminating the fast fall time of . the driver chip output and the resulting system noise generation is shown in Figure 12 for the Y-axis circuitry, and in Figure 13 for the X-axis circuitry.
A description for the Y-axis circuitry is as follows. Figure 12 shows the possible ways in which the slew rate control of the voltage pulser can be utilized to control rise time and/or fall time. The first example, controlling neither rise nor fall time, and is a solution to the fast fall time of the driver chips. The final example controls both rise and fall time, and also eliminates the problem of fast fall time in the chips. The system of the present invention, therefore, presents a high degree of flexibility in that both rise and/or fall time may be controlled.
The voltage pulser 170 (Figure 7) is used to generate the. addressing pulse (Y-pulser output). The YAPP signal shown causes the Y-pulser output voltage to be generated. By supplying the appropriate YAPD logic signal, the output of the Y driver circuit will control the rise time, the fall time, or both the rise and fall time of the driver output voltage, as described above, which is conducted to the Y-electrodes on the plasma panel 70. By making the YAPD logic signal go low at points a either before, or simultaneously with the occurrence of YAPP going high, the driver output will follow the rising ramp of the voltage pulser output. On the other hand, by making the YAPD logic signals go low at point b, after YAPP has gone high, the rise time is not controlled by the voltage pulser circuit, but rather by the driver circuit.
The fall time may be controlled in a similar manner. By allowing the YAPD logic signal to return to the high state at the points indicated by c, either before or simultaneously with the YAPP going low, the fall time is not controlled by the voltage pulser circuit, and is allowed to fall as rapidly as the driver circuit allows. However, by having the YAPD logic signal remain low until the points indicated by d, after YAPP has gone low, the driver output will follow the pulser output, thus controlling the fall time of the pulse. The X-axis circuitry operates in a similar manner, as shown by Figure 13. In this way, the rise time and fall time may be controlled, and problems associated with the fast fall time of the driver chips are eliminated by allowing the voltage pulser circuits to use their inherent slew rate control circuitry to control the slew rate of the driver output voltage.
The notch voltage drop across the output transistors 301, 302 (Figure 5) of the driver chips is also eliminated during the sustain function and non-pulsing portions of the write and erase functions, since transistors 301 and 302 are shorted by the voltage pulser circuits 170, 270 (Figures 8 and 9) during these operations. The only voltage notch which will appear is the voltage drop across the diodes D303 and D304 (Figure 11C), illustrated by the resistor 308.
The voltage notch during the time that addressing pulses are being performed is also considerably smaller, as mentioned above, because the voltage pulser circuits 170, 270 include slew rate controls. The slew rate controls will limit the amount of current, thus resulting in lower voltage drops across the transistors 301, 302 (Figure 5) during the pulsing function. Since the voltage notch is greatly reduced, the characteristics of the plasma display itself and the power supplies are not nearly as critical, and thus the overall cost of the plasma panel system may be reduced by using less precise components.
It can therefore be seen from the above discussion that the present invention provides a number of distinct advantages over the prior art. The panel sustainer and addressing circuitry of this invention significantly reduces circuitry complexity, power dissipation, and the number of supply voltages necessary. Only a single logic input signal is required, eliminating the possibility for improper phasing of the transistors, which could result in the destruction of at least one of the transistors. The use of MOSFET transistors eliminates the classic thermal runaway problem present in all bipolar sustainer designs in the past, since MOSFET transistors are able to switch much faster than other types of transistors. Since the output voltage of this sustainer design has a maximum slew rate that is independent of the logic input signal, excessive displacement currents that could cause noise to mis-trigger low voltage logic signals in the system are avoided. The maximum slew rate also minimizes sustainer overshoot in the rise and fall of the sustainer output waveform.
The power dissipation problems of the Texas Instruments driver chips are virtually eliminated. Four of the five power dissipation factors, quiescent power, level shifting boost power, parasitic power, and notch dissipation power, are completely eliminated during the sustain operation and non-pulsing portions of the-write and erase operations. This is illustrated by the fact that the temperature rise over ambient temperature is now only 3-5°C as compared to a 75°C rise in a system not using voltage pulser circuits. The fast fall time inherent in the driver chips has been solved by using the slew rate control of the voltage pulser circuits. Therefore, generation cf system noise is no longer a significant problem.
The notch voltage problem has been virtually eliminated, allowing plasma design engineers considerably more leeway in extending the versatility of plasma panel operations and in achieving lower system cost due to the use of less precise components. In addition, the elimination of the notch voltage allows a 1024 x 1024 plasma display panel to be driven. The logic error inherent in the design of the Texas Instruments driver chips has been eliminated by using the voltage pulser circuits to generate the output pulse used to address the panel.
Additional features of the invention include a minimum number of discrete components and extensive use of large scale integrated circuits, minimum number of interconnections, no floating power supplies, and a maximum of three power supply voltages.

Claims

1. A circuit for controlling an AC plasma panel, said panel having an X-axis and a Y-axis, said X-axis having a plurality of X addresses identifying X electrodes, said Y-axis having a plurality of Y address identifying Y electrodes, said circuit supplying an output for controlling said panel, said circuit being connected to a first input voltage potential and a second input voltage potential and supplying an output for said electrodes, characterized by:

a pull-up switch connected to said first input voltage potential, and connected to drive said output to said first voltage potential when said pull-up switch is conductive;

a pull-down switch connected to said second input voltage potential and connected to drive said output to said second-voltage potential when said pull-down switch is conductive;

a single logic control input for controlling one of said pull-up and pull-down switches, causing said one switch to be either conductive or non-conductive; and

a coupling circuit interconnecting the other of said pull-up and pull-down switches to said one switch, to cause said other switch to operate in response to the state of said one switch, said other switch being caused to conduct only when said one switch is non-conductive, preventing simultaneous conduction of said pull-up and pull-down switches.

2. A circuit as claimed in Claim 1, additionally characterized by:

circuitry for controlling the rate at which the voltage potential of said output changes from said first input voltage potential to said second input voltage potential, and from said second input voltage potential to said first input voltage potential.

3. A circuit as claimed in Claims 1 or 2, wherein said pull-up and pull-down switches are MOSFET transistors.

4. A circuit as claimed in Claim 3, further characterized by:

circuitry coupled to said MOSFET transistors for preventing high frequency oscillations in said MOSFET transistors when they are alternatively conductive.

5. A circuit as claimed in Claims 1 to 3, additionally characterized by:

a driver circuit for electrical connection to , said electrodes, wherein said driver circuit has as its electrical ground said output, said driver circuit supplying said output to said electrodes, said driver circuit being responsive to second logic control inputs, and superimposing a voltage pulse on said output of said circuit, in response to said second logic control inputs, and supplying the superimposed signal to identified electrodes.

6. A circuit as clalmed in Claim 5, additionally characterized by:

a single high voltage ground-based power supply; and

. a level shift circuit for providing high voltage power to said driver circuit for producing said voltage pulse, said level shift circuit drawing input power from said single high voltage power supply, said level shift circuit providing high voltage power to said driver circuit which is referenced to said output.

7. A circuit as claimed in Claim 6, wherein said level shift circuit is characterized by:

a diode with the anode of said diode connected to said single high voltage power supply; and

a capacitor with one side of said capacitor connected to the cathode of said diode, and the other side of said capacitor connected to said output, the side of said capacitor connected to the cathode of said diode providing power to said driver circuit.

8. A circuit as claimed in Claims 6 or 7, wherein said single logic control input and said second logic control input cause said identified electrodes to execute a write or erase function on said panel.

9. A circuit as claimed in Claims 1 to 3, additionally characterized by:

an integrated circuit comprising:

a common node connected to one of said electrodes

a first transistor connected to one of said first and said second voltage potentials, and connected to drive said common node to said one voltage potential when said first transistor is conductive;

a second transistor connected to said output of said circuit, and connected to drive said common node to said output potential when said second transistor is conductive;

a second logic control input for controlling said first and second transistors, said second logic control input causing said first and second transistors to alternatively conduct to alternatively connect said common node to said one voltage potential and said output of said circuit.

10. A circuit as claimed in Claim 4, additionally characterized by:

a sustainer circuit for generating a sustainer signal to be supplied to said electrodes, wherein the output of said sustainer circuit is said one of said first and second input voltage potentials.

11. A circuit as claimed in Claim 10, wherein a first of said pull-up and pull-down switch is connected to said one of said first and second voltage potentials and said first switch is conductive except when a write or an erase function is being performed on said panel, thus reducing power dissipation within said integrated circuit.