EP0020997A1 - Ink jet printer comprising a device to control the position of ink drops on a printing matrix - Google Patents

Abstract

Ink-jet printer comprising a device for controlling the position of the droplets. Each of the droplets printed on the recording surface, having a relative movement with respect to the droplet generator in a first direction, is part of a character and can be placed in any position in a second direction, perpendicular at the first, from a predetermined position which is that corresponding to the gutter. The information on the position on the recording surface of each of the droplets to be printed with respect to the determined position in the second direction and with respect to the previous printed droplet or a margin in the first direction is stored in a ROM. (51). The information relating to the position of the droplet in the second direction is a voltage applied to a charging electrode, voltage stored in the register (64), the amplitude of which, together with the induction due to the previous droplets, stored in the read only memory (116), determines the deviation of the droplet.

Description

Technical area

The present invention relates to a device making it possible, in an ink-jet printer, to control the position of the ink droplets on a printing medium.

State of the prior art

When printing characters using a dot matrix printer, such as an inkjet printer in which the dots are ink droplets, or a wire printer in which each point is obtained by means of a hammer actuated by a solenoid which strikes one of the wires, the quality of the printing depends largely on the diameter of the points and on the capacity to arrange the various points at the desired locations. The more the size of the dots and their spacing decreases, the more the quality of the print obtained increases. However, the size of the dots cannot be less, in the case of an inkjet printer, than the minimum size of the droplets below which it is no longer possible to obtain a stable positioning of the latter , or, in the case of a wire matrix printer, to the minimum diameter of the wires below which it is no longer possible to prevent them from breaking by striking the printing surface.

For a given printing speed, more small dots than large dots must be printed in a fixed time interval. Obtaining a determined yield (or "throughput") from a printer can therefore lead to using large dots, to the detriment of the print quality.

Thus, the quality of the printing depends to a large extent on the position of the dots for a given size of the latter. One of the methods used to control the position of each of the points is to use a grid or a fixed matrix divided into squares, the length of the side of each of which is equal to the minimum spacing between droplets. To fill each of these squares, depending on the printing configuration required, this spacing should not be greater than the quotient of the diameter of the droplet divided by the square root of 2.

One then obtains characters having a discontinuous appearance and comprising, in the case of curves or diagonal lines other than those inclined at 45 °, distinct steps, thin segments and thick segments. This appearance of the characters affects the quality of the print.

The latter can be improved to a certain extent if there is greater freedom with regard to the positioning of all the vertical or horizontal segments of the characters while maintaining the minimum spacing of the points which constitute each of the segments. . For example, the droplets constituting a second vertical segment can be shifted upwards by half of one of the squares of the grid with respect to the droplets constituting a first vertical segment, so that an overlap occurs. The same can be done in the horizontal direction. This flexibility in the vertical direction mainly has the effect of improving the quality of the lines making an angle of low value with the horizontal, while the flexibility obtained horizontally has mainly the effect of improving the lines which make an angle of low value with the vertical.

In the case of an inkjet printer of the type to screen, this vertical printing flexibility can be achieved fairly easily and without affecting performance since an increment of deflection can be added to the entire screen. On the other hand, the flexibility of vertical printing and the flexibility of horizontal printing in a printer of this type can only be combined at the cost of a reduction in yield, since additional time must be allowed to print additional positions of the frame.

In the case of a wire matrix printer, horizontal printing flexibility can easily be obtained if it can be prevented from interfering with the minimum duration of the hammer cycle. However, as in the previous case, the flexibility of horizontal printing and the flexibility of vertical printing in such a printer can only be combined at the cost of a reduction in yield, since the printing of each line requires additional passes or scans.

Statement of the invention

The present invention makes it possible to avoid the discontinuous appearance of the printed characters, independently of the angle made by the lines of which they are composed with respect to the horizontal or the vertical or their curvature. This result is obtained, according to the invention, thanks to a so-called "free" positioning of the ink droplets, each of them being arranged in any desired location relative to the printed droplet which precedes it. The invention also makes it possible to obtain a high yield.

This free positioning of the droplets used for the purposes of printing is obtained by applying to each of them a load of a selected value so that the droplet is positioned at a desired location in a given direction, which is practically perpendicular to an axis along which a relative movement exists between the print medium and the generation device ink droplets. The instant when a given droplet hits the print medium is a function of the time when the previous droplet also hit the support. It is therefore possible, according to the present invention, to ensure that each droplet used for printing purposes is arranged on the support relative to a predetermined position in said direction and not according to the vertical distance which separates it from the previous droplet in this same direction. It is therefore unnecessary for the droplets to be protected towards the support in a monotonous ascending sequence when printing a given column, for example.

One of the objects of the present invention is therefore to provide a more sophisticated ink-jet printer than those of the prior art.

Another object of the present invention is to provide a device making it possible, in an ink-jet printer, to control the position on the support of each of the ink droplets used for the purposes of printing.

Another object of the present invention is to provide an ink projection printer making it possible to obtain a "free" positioning of the droplets used for the purposes of printing.

Other objects, characteristics and advantages of the present invention will emerge more clearly from the following description, made with reference to the drawings appended to this text, which represent a preferred embodiment thereof.

Brief description of the figures

• Figure 1 schematically shows part of an ink-jet printer with which the controller of the present invention is used.
• Figure 2 is a block diagram of the control printing of ink droplets in the inkjet printer.
• Figures 3 and 4 are timing diagrams showing the relationships between different signals generated by the control device of the present invention.
• Figure 5 is a block diagram partially showing a master pointer forming part of a pointer that comprises the control device of the invention.
• Figure 6 is a block diagram partially showing a slave pointer forming part of the pointer that comprises the control device of the invention.
• Figure 7 is a block diagram partially showing a master counter forming part of a track length counter that comprises the control device of the invention.
• Figure 8 is a block diagram partially showing a slave counter forming part of the track length counter that comprises the control device of the invention.
• Figure 9 is a block diagram showing a so-called end-of-character flip-flop that comprises the control device of the invention.
• Figure 10 is a block diagram showing a so-called synchronization flip-flop (SYNC) that comprises the control device of the invention.
• Figure 11 is a block diagram partially showing a point count register that includes the control device of the invention.
• Figure 12 is a block diagram of another part of the point count register of the control device of the present invention.
• FIG. 13 is a block diagram partially representing a master counter forming part of a counter associated with the network which comprises the control device of the invention.
• Figure 14 is a block diagram partially representing a "low" slave counter forming part of the counter associated with the network of the control device of the invention.
• FIG. 15 is a block diagram partially representing a "high" slave counter forming part of the counter associated with the network which comprises the control device of the invention.
• Figure 16 is a block diagram showing a pair of flip-flops forming part of the network detector that comprises the control device of the invention.
• Figure 17 is a block diagram showing one of the flip-flops of a so-called voltage register that comprises the control device of the invention.
• Figure 18 is a block diagram partially showing a so-called charge electrode voltage gate which comprises the control device of the invention and which makes it possible to control the application of a voltage to a charge electrode used to impart a charge to ink droplets.
• Figure 19 is a block diagram showing one of the flip-flops of a so-called gutter inductance register that comprises the control device of the invention.
• Figure 20 is a block diagram showing one of the flip-flops of a so-called first-order induction register that comprises the control device of the invention.
• Figure 21 is a block diagram showing one of the flip-flops of a master register that comprises a so-called second order induction register forming part of the control device of the invention.
• Figure 22 is a block diagram of one of the flip-flops of a slave register that comprises the so-called second order induction register forming part of the control device of the invention.
• Figure 23 shows an ideal "W" character.
• Figure 24 shows the positions of the ink dots that make up the character "W" when using a fixed grid or matrix.
• Figure 25 shows the positions of the ink dots constituting the "W" character when using a fixed grid or matrix, the dots forming part of each of a number of adjacent vertical segments being offset by one-half not vertically with respect to the previous vertical segment.
• Figure 26 shows the positions of the ink dots constituting the "W" character when using a fixed grid or matrix, the dots forming part of each of a number of adjacent vertical segments being offset by one-half not horizontally from the previous vertical segment.
• Figure 27 shows the positions of the ink dots necessary to form the character "W" in accordance with the present invention when using a single line width of dots.
• Figure 28 shows the positions of all the ink dots used to form the character "W" when using the control device of the invention, some parts of the character "W" being thicker than others.
• Figure 29 is an enlargement of part of the character "W" delimited by means of a dotted line in Figure 28 and shows the positions of the different points.

Description of an embodiment of the invention

FIG. 1 shows an ink-jet printer 10 of the type described in European patent application No. 79103976.6 filed on October 12, 1979 by the applicant. The printer 10 comprises a print head 11 mounted on a carriage 12 which is driven by a device 12A via circuits 13, so as to move from left to right and vice versa with respect to a recording medium 14, such as a sheet of paper, placed on a drum, for example. There is therefore a relative movement along a first axis between the print head 11 and the surface of the support 14.

Furthermore, the support 14 moves in a direction practically perpendicular to the first axis in the region in which the printing takes place. The support 14 can be driven continuously or advanced in increments at the end of each movement of the head 11 along the first axis. The print medium 14 could also be placed on a flat surface and move vertically, either continuously or in increments, as in the first case. There is therefore a relative movement between the head 11 and the printing medium 14 in a second direction practically perpendicular to the first axis.

A network 15 makes it possible to determine the horizontal position (that is to say along the first axis) of the head 11 at different times. A network of this type is described in European patent application No. 79101561.3 filed May 22, 1979 by the applicant.

The print head 11 includes a pump 16 which allows directing pressurized ink from a reservoir 17 to a droplet generator 18. The latter comprises a transducer which, when energized by a circuit 19, applies disturbances to the ink. The circuit 19 is excited by an oscillator 19 ', forming part of the electronic circuits 20 of the system, at a relatively high sequence, of the order of 117KHZ, for example.

An ink jet 21 flows from a nozzle 22 which comprises the droplet generator 18. The disturbances applied to the jet 21 from the generator 18 have the effect of causing the jet 21 to be divided into droplets 23 inside a charging electrode 24. Each of the droplets intended for printing characters, symbols, etc., on the support 14 receives a charge, the value of which is controlled by the present invention so that the droplet is diverted to a desired location on said support 14 after having passed between a pair of deflection plates 25 and 26.

Since a constant potential is applied across the terminals of the plates 25 and 26, it is the value of the charge that each droplet 23 receives for printing which determines the extent of the deflection that it undergoes during its trajectory. towards the printing medium 14. Thus, the amplitude of the voltage applied to the charging electrode to charge each of the droplets 23 used for printing, as well as the induction produced by the droplets 23 which immediately precede the charged droplet, determine the position to which the charged droplet 23 is deflected on the print medium 14.

If a droplet 23 is not used for printing purposes, it is directed to a gutter 27 and transmitted to the reservoir 17 after passing through a filter 29. The droplets 23 which are not used to form characters receive no charge other than that necessary to compensate for the induction produced by the droplets 23 which immediately precede them.

An ideal "W" character has been shown in Figure 23. The latter comprises a left external axis 31, a left internal axis 32, a right internal axis 33 and a right external axis 34. The axes 31 and 32 intersect in their lower part, the axes 32 and 33 intersect in their upper part and the axes 33 and 34 intersect in their lower part and in the same horizontal plane as the axes 31 and 32.

If we form the same character "W" by means of points 35, using a grid or a fixed matrix, we see, as shown in Figure 24, that only some of the points 35 have their centers on the axes 31, 32, 33 or 34. Only the points 35 which are at the top and at the bottom of the axis 31, at the top and at the bottom of the axis 34, and at the intersection of the axes 32 and 33 have their center on these axes. A very irregular "W" character is therefore obtained.

Some improvement is obtained, as shown in Figure 25, by moving the points 35 in certain vertical segments by a vertical distance corresponding to half of one of the squares of the grid.

As previously mentioned, the fact of moving the points 35 vertically above all makes it possible to obtain an improvement in the case of lines which make an angle of small value with the horizontal. As a result, the quality of the character reproduced in Figure 25 is hardly higher than that of the character in Figure 24.

However, as previously observed, a better quality impression is obtained in the case of lines which make an angle of small value 1 with the vertical by horizontally shifting the points 35 which certain vertical segments comprise. This is shown in Figure 26, in which the points 35 which are part of certain vertical segments have been shifted horizontally by one distance equal to half of one of the squares of the grid, which results in an overlap of the points 35. Thus, in Figure 26, the centers of the upper point, the third point, the eighth point and the last point are on the left outer axis 31 of the character. This is an improvement over the character shown in Figure 24, in which only two of the dots 35 have their center on line 31 and in comparison to the character shown in Figure 25, in which only three of the dots 35 have their center on axis 31.

When using the control device of the present invention, each of the points 35 can be arranged so that, as shown in Figure 27, its center is on one of the axes 31 to 34, and it occurs an overlap of each of the points. If a single row of dots 35 were to be printed, the center of each of these would be, thanks to this device, on one of the axes 31 to 34.

It may however be necessary in certain cases that the different parts of the printed character have a variable width, so that all the dots 35 could not have their center on the axes 31 to 34. The control device of the present invention makes it possible to solve this problem, as shown by the character "W" shown in Figure 28.

FIG. 2 shows a pointer read-only memory (PROS) 50 which receives an eight-bit character code which constitutes an address identifying the character to be printed. This memory can store 256 words of 16 bits each. The output of the memory 50 makes it possible to identify a determined position in a read-only memory known as a character assembly (FROS) 51, position where the data used to print the character specified by the eight-bit code must begin. The memory 51 contains a maximum of 65536 words of sixteen bits. It takes about 16,000 words to make up a collection of one hundred Roman characters.

The sixteen-bit word coming out of memory 50 is transferred to a pointer 52, which includes two counters respectively called master pointer (PCM) 53 and slave pointer (PCS) 54 which work together. The PCM counter 53 directly addresses the FROS memory 51 and accesses each of the lines of the latter sequentially from the bottom to the top.

The sixteen-bit word from the PROS memory 50 is transferred to the PCM counter 53 of the pointer 52 during the last drop time of the previous printed character. As shown in Figures 3 and 4, each droplet time is divided into eight equal time intervals defined by clock signals TO to T7 supplied by a clock excited by the oscillator 19 '(see Figure 1). This transfer coincides with the clock signal T2 (see Figure 3). During the last droplet times (including the last) relating to the previous printed character, a so-called end of character (EOC) flip-flop 55 (see Figures 2 and 9) generates an EOC signal which remains at the high level from the moment when the clock signal T7 (see Figure 3) goes high until the next clock signal T4 also goes high.

A GD flip-flop 55 '(see Figures 2 and 16) generates a GD signal, which remains high during the first part of the last drop time relating to a character. This signal is generated when a high level GP signal from network 15 is received (see Figure 1).

Dans l'équation (1), n représente chacun des seize bits d'un mot spécifique emmagasiné dans la mémoire 50, le transfert de chacun de ces bits coïncidant avec le signal d'horloge T2 lorsque le signal EOC et le signal GD sont tous deux au niveau haut.The transfer of the output from memory 50 (see Figure 2) to the PCM counter 53 is therefore defined by the logical equation:

In equation (1), n represents each of the sixteen bits of a specific word stored in memory 50, the transfer of each of these bits coinciding with the signal T2 clock when the EOC signal and the GD signal are both high.

The value d: PCM counter 53 is transferred to the PCS counter 54 when the clock signal T5 of the same cycle appears. After having been increased by one unit, this value is transferred to the counter 53 when the clock signal T2 of the next droplet time appears, the value of the counter 53 thus being increased by one unit.

Dans chacune des équations logiques (2) à (5), n = 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15 et 16 puisqu'il existe seize bits. Dans cette notation, "." représente "et", et "+" représente "ou".The following logical equations relating to pointer 52 can therefore be written as follows:

In each of the logical equations (2) to (5), n = 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15 and 16 since it exists sixteen bits. In this notation, "." represents "and", and "+" represents "or".

The logic circuits which constitute the pointer 52 are shown by way of example in FIGS. 5 and 6. The logic elements represented in these two figures are sold by the company Texas Instruments and relate respectively to the PCM 53 and PCS 54 counters, being understood that in this example n = 14. The counters 53 and 54 should obviously include similar elements for each of the other bits of the sixteen-bit word coming from the PROS 50 memory (see FIG. 2), that is to say for the bits one to thirteen, fifteen and sixteen.

The PCM counter 53 shown in FIG. 5 notably comprises doors 56 and 57 each of which consists of three NI doors with three inputs each and with positive logic of the type marketed by the company Texas Instruments under the designation SN7410 (J). It will be noted that each of the unused logic inputs of the gates 56 and 57 is maintained at a high logic level.

Pins 1 and 2 of gate 57 respectively receive the EOC signal from flip-flop 55 (Figures 2 and 9) and the clock signal T2. When each of these inputs is at the high level, a low level appears on pin 12 and is applied to pin 1 of an inverter 57 'which also includes the door 56. This inverter can be of the type marketed by the firm Texas Instruments under the designation SN 7404 (J).

Gate 56 receives respectively on its pins 1, 2 and 13 the signal EOC.T2 emanating from pin 2 of the inverter 57 ', the signal GD emanating from the flip-flop 55' (see Figures 2 and 16), and a signal PROS 14 (the fourteenth most significant bit of the sixteen bit word) emanating from the PROS 50 memory of Figure 2 and which can be at a high or low logic level. When these three input signals are at the high level, a low level appears on pin 12 of door 56 (FIG. 5) and is applied to the preset input P (pin 13) of a flip-flop 58, which can be made up of the flip-flop sold by the company Texas Instruments under the designation SN 74L71 (J). It will be noted that each of the unused logic inputs of the flip-flop 58 is maintained at a high logic level.

When pin 13 (input P) of flip-flop 58 is low and pin 2 (dump input or input C) is at the high level, as will be seen later, the flip-flop 58 provides a high level on its pin 8 (output Q), which corresponds to the PCM signal ₁₄ in the example in which n = 14. This makes it possible to satisfy one of the two parts of the logic equation (2) relating to the setting of the PCM signal ₁₄ to the logic level "1" and to set the position of the counter CPM 53 corresponding to the fourteenth bit of weight the higher of the sixteen-bit word from PROS 50 memory.

The PCM counter 53 also includes a gate 59 which is a NI gate with thirteen inputs and with positive logic of the type marketed by the firm Texas Instruments under the designation SN74S133 (J). Pins 1 to 7 of gate 59 respectively receive the signals PCS to PCS ₇ emanating from the PCS counter 54 (Figure 2) and corresponding to the first seven bits contained in this counter, while these pins ₁ 0 to 15 respectively receive the PCS signals ₈ to PCS ₁₃ emanating from the PCS 54 counter and corresponding to bits eight to thirteen. When these inputs are at the high level, thus indicating that the level of the PCM signal ₁₄ will have to change at the next count, the pin 9 of the gate 59 is at the low level. The signal obtained on this pin is inverted by the inverter 57 'and applied to pins 4 and 10 of the flip-flop 58.

Pin 5 of flip-flop 58 receives a PCS signal ₁₄ of pin 6 (output Q) of a flip-flop 61 (Figure 6), which is of the same type as flip-flop 58 of Figure 5 and including all the unused logic inputs are maintained at a high logical level. The clock signal T2 is applied to pin 12 (clock input or CK input) of flip-flop 58.

The pins 3 and 9 of the flip-flop 58 both receive a signal RLS = O.EOC emanating from pin 6 of the inverter 57 '. The EOC signal is applied to pin 10 of door 57 from the EOC flip-flop 55 (Figure 9) and the signal RLS = 0 is applied to pin 11 of this same door from a track length counter 62 (see Figure 7). Each of the signals RLS = 0 and EOC is at the high level, as will be seen below, when one of the ink droplets 23 is to be used for the purposes of printing.

When the inputs received by pins 10 and 11 of gate 57 (Figure 4) are both high, each of the signals applied to pins 3 and 9 of flip-flop 58 is high. Therefore, when the clock signal T2 goes low, the output signal obtained on pin 12 of the inverter 57 'is high, the PCS signal ₁₄ obtained on pin 6 (output Q) of flip-flop 61 (Figure 6) is at the high level, as will be seen below, as is the signal RSL = O. _EOC coming from pin 6 of inverter 57 ', flip-flop 58 will present a high level PCM signal ₁₄ on its pin 8 (output Q). The second part of the logical equation (2), in which n = 14, is therefore satisfied. This makes it possible to directly establish the desired high logic level at the position of the PCM counter 53 which corresponds to the fourteenth bit of the word received from the PROS memory 50, or to increase the value of this counter by one unit, from the PCS counter 54, to obtain this high logic level, once one of the droplets 23 intended for printing has been generated.

Gate 56 (Figure 6) receives respectively on its pins 11, 10 and 9 the EOC T2 signal, the signal from flip-flop 55 '(Figure 16) and the PROS signal ₁₄ , which is high when the fourteenth bit of highest weight of the sixteen bit word received from PROS 50 memory (Figure 2) is low.

Therefore, when the signals applied to pins 9, 10 and 11 of door 56 are at the high level, a low level signal is obtained on pin 8 of this door and applied to pin 2 (input C) of the flip-flop 58, which, since the signal obtained on its pin 13 (input P) is at the high level since the signal PROS ₁₄ is at low level when the signal PROS ₁₄ is at the high level, provides a PCM signal ₁₄ of high level on its pin 6 (output Q) since n = 14 in the example cited. This satisfies one of them part of the logic equation (3) relating to the setting to "0" of the PCM signal ₁₄ so that the PCM counter 53 presents a low level for the fourteenth most significant bit of the sixteen-bit word supplied by PROS 50 memory.

Pin 11 of flip-flop 58 (Figure 5) receives a PCS signal ₁₄ of pin 8 (output Q) of flip-flop 61 of Figure 6. As previously mentioned, pin 9 of this flip-flop 58 receives from the inverter 57 'the signal RLS = O.EOC.

Therefore, when the clock signal T2 is at the high level, the output of the pin 12 of the inverter 57 'is also at the high level, as well as the PCS signal ₁₄ from the pin 8 of the flip-flop 61 , as will be seen below, and when the signal RLS = O. _EOC , a PCM signal ₁₄ of high level is present on pin 6 (output Q) of flip-flop 58 after the transition to the low level of clock signal T2. The second part of the logical equation (3), which concerns the setting to "0" of PCM when n = 14 is therefore satisfied. Thanks to this logic, the position of the PCM counter 53 of the pointer 52 corresponding to the fourteenth bit of the word coming from the PROS memory 50 can be directly set low, or its value can be increased by one unit from the PCS 54 counter to obtain a low level after one of the droplets 33 used for the purposes of printing has been generated.

The flip-flop 61 of Figure 6, which is one of the sixteen flip-flops constituting the PCS counter 54, receives on its terminal 12 (input CK) the clock signal T5, and on its pin 3 the signal PCM ₁₄ coming from the pin 8 (output Q) of flip-flop 58. Consequently, when the PCM signal ₁₄ and the clock signal T5 are both high, flip-flop 61 receives on its pin 8 (output o) a- PCS ₁₄ high level signal after switching to low level of clock signal T5. The logical equation (4), which relates to the passage to the high level of the signal PCS ₁₄ when n = 14, is therefore satisfied. This allows to transfer the ^s counter PCS 54 the high level signal provided by the PCM meter relative to the fourteenth bit w higher in counter 53, during the same time of droplet when the signal was transferred to the counter PCM 53 from the PROS 50 memory in Figure 2 or from the PCS 54 counter.

If the PCM signal ₁₄ is at the high level, the flip-flop 61 of FIG. 5 receives a PCS ₁₄ signal of high level on its pin 6 (output Q) after the passage to the low level of the clock signal T5. This is due to the fact that the PCM signal ₁₄ is applied to pin 9 of flip-flop 61 from pin 6 (output Q) of flip-flop 58 in Figure 5.

The logic equation (5) relating to the transition to the low level of the PCS signal when n = 14 is therefore satisfied. This allows the position of the PCS 54 counter (see Figure 2) corresponding to the fourteenth most significant bit to be set to a desired low level when the fourteenth most significant bit contained in the PCM register 53 is at a low logic level. .

If the value of n was equal to 16, it would be necessary to apply the signals PCS ₁₃ , PCS ₁₄ and PCS _{15 respectively} to pins 3, 4 and 5 of gate 56 shown in Figure 5. If all these signals were at high level, the door 56 would have on its spindle 6 a low level which would be applied to the spindle 6 of the inverter 57 '. This would give a high level on pin 4 of inverter 57 'intended to be applied to pin 15, which receives the PCS signal ₁₃ when n = 14, from gate 59.

If the value of n was equal to 15, the PCS signal ₁₅ would not be applied to pin 5 of gate 56. This pin would be maintained at a high logic level, likewise than all of the logic inputs used from each of the different elements.

If the value of n is less than 13, one or more of the inputs of gate 59 of the PCM counter 53 receives no signal. These unused logic inputs are maintained at a high logic level.

It is understood that the PCM counter 53 has fifteen additional circuits corresponding to the other fifteen bits and which are analogous to the circuits represented in FIG. 5. As previously mentioned 1'.3, the PCM counter 54 has fifteen similar flip-flops to flip-flop 61 and each of which corresponds to one of the fifteen other bits of the sixteen-bit word.

The first ten bits of the sixteen bit word emanating from the FROS memory 51 of FIG. 2 are transferred to a so-called voltage register 64, the remaining six bits being transferred at the same time to the track length counter 62. The latter includes a master counter (RLM 65) and a slave counter (RLS 66) working together. The counter 62 receives a new sixteen-bit word from the FROS memory 51 once each of the droplets 53 used for the purposes of printing has received the required charge.

The transfer of the ten bits from the FROS memory 51 to the voltage register 64 is defined by the logic equation:

The transfer of the six remaining bits from the FROS memory 51 to the counter 62 is defined by the logical equation:

Dans chacune des équations logiques (8) à (11) relatives au compteur 62, n= 1, 2, 3, 4, 5 ou 6.From the logical equation (7), we can write the following logical equations relative to the track length counter 62:

In each of the logical equations (8) to (11) relating to the counter 62, n = 1, 2, 3, 4, 5 or 6.

FIGS. 7 and 8 respectively represent, by way of example, the logic circuits, produced by means of modules manufactured by the firm Texas Instruments, constituting the counters RLM 65 and RLS 66 which make up the track length counter 62. In this example, n = 5. The counters 65 and 66 must include elements of the same type as those represented for each of the other bits supplied to the counter 62 by the FROS memory 51.

As shown in Figure 7, the RLM counter 65 includes a door 68, which should preferably be constituted by the same module as that of door 56 in Figure 5. It will be noted that each of the unused logic inputs of door f 68 of Figure 7 is maintained at a high logic level.

Gate 68 receives on its pin 9 the clock signal T5, on its pin 11 a FROS signal ₁₅ (the penultimate bit of the sixteen bit word) emanating from the FROS memory 51, this last signal being at the high level or at the low level depending on whether the fifteenth bit is itself at the level high or low, and on its pin 10 the signal RLS = 0 emanating from pin 12 of an inverter 69, which is of the same type as the inverter 57 'of Figure 5. When these three inputs are at the level high, a low level signal appears on the output pin 8 of door 68 and is applied via a conductor 70 to pin 13 (input P) of a rocker 71 which is of the same type as the flip-flop 58 in Figure 5. All unused logic inputs of flip-flop 71 in Figure 7 are kept at a high logic level.

When, as will be seen below, a low level signal and a high level signal appear respectively on its pins 13 (input P) and 2 (input C), the flip-flop 71 provides a signal RLM ₅ of high level on its pin 8 (output Q), since n = 5 in the example cited. Therefore, one of the two parts of the logic equation is satisfied and the signal RLM, - is set to a high level when the fifteenth bit of the output word of the memory FROS 51 of FIG. 2 is at the high level .

The signal RLS = 0 which is obtained on pin 12 of the inverter 69 of FIG. 7, is generated by a gate 72, which is a gate of the NI type with eight inputs and with positive logic marketed by the firm Texas Instruments under the designation SN 7430 (J). Each of the unused logic inputs of gate 72 is maintained at a high logic level. It will be noted that only one gate 72 is necessary in the RLM counter 65 instead of being it for each bit.

Pins 1 to 6 of gate 72 respectively receive the signals RLS to RLS ₆ . Each of these signals is provided by a corresponding flip-flop of the RLS counter 66 of Figure 8. As shown in this figure, the RLS 66 counter comprises a flip-flop 73, which is of the same type as the bottom cule 58 of Figure 5 and of which all the unused logic inputs are maintained at a high logic level, the RLS signal ₅ being obtained on its pin 6 (output Q). When all the signals received on terminals 1 to 6 of door 72 are at the high level, pin 8 of the latter provides a low level RLS # 0 signal. This signal is applied via a conductor 74 to pin 13 of an inverter 69. This results in pin 12 of inverter 69 a signal RLS = 0 of high level which indicates that the value of the RLS 66 counter is zero, the logic equation (12) being satisfied.

The inverter 69 provides on its pin 10 a signal RLM = 0 which results from the inversion of the signal RLM # 0 applied to its pin 11 from the pin 8 of a door 75, which is of the same type as the door 72 and each of the unused logic inputs is maintained at a high logic level. It will be noted that the RLM counter 65 requires a single gate 75, and that there is no need to provide a gate 75 for each bit.

Pins 1 to 6 of gate 75 respectively receive signals RLM ₁ to RLM ₆ . These signals are provided by flip-flop 71 (in the case of the signal RLM ₅ ) and by a corresponding flip-flop for each of the other five bits. When all the signals received by these pins 1 to 6 are at the high level, the gate 75 provides on its pin 8 an RLM signal ≠ 0 which is at the low level. The logical equation (13) is therefore satisfied.

The signal RLS # 0 obtained on pin 8 of gate 72 belongs to the second part of the logic equation (8) and is applied to pin 4 of flip-flop 71. Pin 5 of the latter receives the signal RLS ₅ of scale 73 (Figure 8) of scale RLS 66.

Pin 3 of flip-flop 71 receives the inverted output of pin 6 of a door 76, which is a module comprising two NI doors with four inputs each and with logic positive of the type marketed by Texas Instruments under the designation SN7420 (J). All the unused logic inputs of gate 76 are kept at a high logic level.

Pins 1, 2, 4 and 5 of gate 76 respectively receive the signals RLS to RLS ₄ from the flip-flops that the counter RLS 66 has for n = 1, 2, 3 and 4 and which correspond to flip-flop 73 in Figure 8 When all these signals are at the high level, pin 6 of the door 76 provides an output signal which is at the low level. This pin is connected to pin 1 of the inverter 69 and, therefore, the signal obtained on pin 2 of the latter goes high when the signal obtained on pin 6 of gate 76 is low. Thus, when a high level signal is obtained on the input pin 3 of the flip-flop 71 due to the fact that each of the RLS signals _. at RLS ₄ is high, the RLS # 0 signal from pin 8 of gate 72 is high as is the RLS signal _. , and an RLM signal ₅ obtained on pin 8 (output Q) of flip-flop 71 goes high when the clock signal T5 goes low. The second part of the logic equation (8), relating to the setting to "1" of the signal RLM when n = 5, is therefore satisfied. Thanks to this logic, the position of the RLM counter 65 corresponding to the fifth bit received from the FROS memory 51 of FIG. 2 can be set to the desired high level, either directly or via the RLS counter 66 after a decrease of one unit of the value of the counter 65, following the generation of one of the droplets 23 used for the purposes of printing.

When the fifteenth bit (that is to say the fifth bit received by the RLM counter 65) of the signal emanating from the FROS memory 51 is at the low level, the first part of the logic equation (9) relating to setting the RLM ₅ signal to "0", which means that a signal PLM ₅ high level is obtained on pin 6 (output Q) of flip-flop 71 in Figure 7. This result is obtained by applying a low level signal to pin 2 (input C) of flip-flop 71 from pin 12 of the door 68 when the pin 13 (input P) of this rocker has a high level.

A low level signal is only obtained on pin 12 of gate 68 only when the signals respectively obtained on its pins 13, 1 and 2, namely the clock signal T5, the signal RLS = 0 and the signal FROS ₁₅ emanating from the memory FROS 51 of FIG. 2, are all three at the high level. The signal FROS ₁₅ can only be at the high level when the fifteenth bit coming from the FROS memory 51 is at logic level 0. Therefore, when the clock signal T5 goes to the high level, a low level is transmitted to pin 2 (input C) of flip-flop 71 to produce a high level signal on its pin 6 (output Q). This satisfies one of the two parts of the logic equation (9) relating to the setting to "0" of the signal RLM _S and lowers the position of the counter RLM 65 corresponding to the fifth of the six bits stored in it. this.

A high level RLM signal ₅ is also obtained on pin 6 (output Q) of flip-flop 71 when the input signals applied to its pins 9, 10 and 11 are at high level and the clock signal T5, which was at the high level, goes to the low level. A signal at the high level is obtained on its pin 11 when each of the signals RLS ₁ to RLS ₄ is at the high level. The RLS signal ₅ is applied to pin 9 of flip-flop 71 from pin 8 (output Q) of flip-flop 73 (Figure 8) of the RLS counter 66.

The signal RLS # 0 is applied to pin 10 of flip-flop 71 of Figure 7 from pin 8 of door 72. This signal is high whenever each at least one of the inputs of door 72 is at low level.

The second part of the logic equation (9), which concerns the setting to "0" of the signal RLM when n = 5, is therefore satisfied. Thanks to this logic, the position of the RLM counter 65 corresponds to the fifteenth bit (fifth bit contained in this counter) emanating from the FROS memory 51 of FIG. 2 can be set to the desired low level, either directly or via the counter 66 after decreasing the value of counter 65 by one unit at some of the droplet times.

Pin 12 (input CK) of flip-flop 73 of Figure 8, which is one of the flip-flops that includes the RLS counter 66, receives the clock signal T1 while its pin 4 receives the signal RLM, coming from the pin 8 (output Q) of flip-flop 71 in Figure 7. A SYNC signal received from flip-flop 77 (see Figure 10) is applied to pin 3 of flip-flop 73.

As will be seen below, the flip-flop 77 provides a high level SYNC signal when the value of a so-called network counter 78 (see FIG. 2) is equal to the value of a point counter 79 and when the clock signal T7 goes high. The counter 79 directly counts the ink droplets 23 while the counter 78 counts the droplets 23 from zero to thirty-one and then stops counting until it has received a high level GD pulse from the scale 55 '. Each of the counters 78 and 79 counts binary at the rate of generation of the droplets, starting from zero, when the initial GD pulse which coincides with the start of a character, is obtained.

When the SYNC signal provided by flip-flop 77 in Figure 10 is high, flip-flop 73 in Figure 8 provides a high level RLS signal ₅ on its pin 8 (output Q) when the clock signal Tl goes to low level and the RLM ₅ signal is high. The logical equation (10) is then satisfied.

The SYNC signal is also applied to pin 9 of flip-flop 73, and the RLM signal ₅ emanating from pin 6 (output Q) of flip-flop 71 is applied to its pin 10. Therefore, when the clock signal Tl applied to pin 12 of flip-flop 73 goes low and the SYNC and RLM signals ₅ are both high, flip-flop 73 provides a high level RLS _S signal on pin 6 (output Q). The logical equation (11) is then satisfied.

The value of the RLM counter 65 (FIG. 2) of the track length counter 62 is decreased by a binary unit each f _G -s as the clock signal T5 appears, as long as the SYNC signal supplied by the flip-flop 77 of the Figure 9 is at the high level when the clock signal Tl relating to the same droplet time appears. This is necessary to transfer the value from the RLM 65 counter to the RLS 66 counter and to satisfy one of the two logic equations (10) and (11). At least one of the six flip-flops of the RLS counter 66 (such as the flip-flop 73 shown in the figure) changes state each time this transfer takes place and makes it possible to decrease the value of the RLM counter 65.

Mise à "0" de la bascule 77 (SYNC est au niveau haut) =

The SYNC signal remains high until the value of the network counter 78 differs from that of the point counter 79 and the value of the RLM counter 65 is greater than three. The logical equations relating to rocker 77 can thus be written as follows: Setting to "0" of rocker 77 (SYNC is on high level) =

Setting to flip-flop 77 to "0" (SYNC is at high level) =

The SYNC signal goes high when the clock signal T7 is high and a GCM signal from the network counter 78 in Figure 2 is equal to a DCM signal from the point counter 79. Flip-flop 77 (Figure 10) therefore applies a signal GCM = DCM to pin 2 of gate 79A, of which all the unused logic inputs are kept at a high logic level, the clock signal T7 being applied to pin 1 of this same gate. . The module 79A can, for example, be of the type with four NI doors with two inputs each and with positive logic marketed by Texas Instruments under the reference SN7400 (J).

When the signals applied to pins 1 and 2 of gate 79A are at the high level, a low level signal appears on pin 3 of this gate and is applied to pin 13 of a gate 79B, whose unused logic inputs are maintained at a high logical level. Gate 79 can be of the type sold by Texas Instruments under the reference SN74L55 (J).

A SYNC signal appears on output pin 8 of gate 79B and is applied to pin 3 of the inverter 79C, which provides a SYNC signal on its pin 4. The inverter 79C is of the same type as the inverter 57 'in Figure 5.

The SYNC signal obtained on pin 4 of the inverter 79C is applied to pin 12 of gate 79B. Thus, when the signals T7 and GCM = DCM are both at the high level, the gate 79B has a low level input signal on its pin 13 and, therefore, a high level SYNC signal on its pin 8, however, the inverter 79C has a low level SYNC signal on its pin 4. The transition to the high level of the SYNC signal when the signals T7 and GCM = DCM are at high level, satisfies logic equation (16).

Pins 1, 2 and 3 of gate 79B respectively receive the clock signal T0, the signal RLM> 3 and the signal GCM = _DCM . The SYNC signal remains high until the TO clock signal is high, as well as the RLM> 3 and GCM = DCM signals, and then switches to low level, the SYNC signal then being high.

The RLM> 3 signal is only high when the binary value of the RLM 65 counter is greater than three. The = RLM signal> 3 is obtained on pin 8 of the door 76 of the counter 65. In order for the value of the latter to be greater than three, any bit corresponding to a signal greater than the RLM signal ₂ makes it possible to obtain a value greater than three (for example, the RLM ₃ signal alone makes it possible to obtain a value of four). Consequently, the gate 76 receives respectively on its pins 13, 12 10 and 9 the signals RLM ₃ , RLM _. , RLM _vs and RLM ₆ . When any one of these signals is at the low level, thus indicating that the value of the RLM counter 65 is greater than three, the signal RLM> 3 present on pin 8 of the gate 76 is at the high level.

The signal GCM = _DCM is applied to pin 5 of an inverter 81 forming part of the stitch counter 79 from pin 9 of a door 80 (see Figure 11). The latter is of the same type as gate 59 (see Figure 5) of the PCM counter 53 and all of its unused logic inputs are maintained at a high logic level. The inverter 81 is of the same type as the inverter 57 '(FIG. 5) which the counter 53 includes. The signal GCM = DCM is applied from pin 6 of the inverter 81 of FIG. 11.

The SYNC signal generated by the flip-flop 77 therefore makes it possible to decrease the value of the RLM counter 65 until the signal GCM = DCM obtained on pin 9 of the gate 80 of the point counter 79 goes high and the signal RLM> 3 obtained on pin 8 of door 76 is then at the high level. The counter 62 consequently stops counting when the SYNC signal goes low until the GCM = DCM signal goes high again. This only occurs when the value of the network counter 78 and that of the counter 79 are again equal, the value of the counter 78 increasing and the counter 79 ceasing to count.

The SYNC signal being at high level, the presence of a high level signal on each of pins 1, 2 and 3 of gate 79B in FIG. 9, this being due to the fact that the clock signal T0, the signal RLM> 3 and the signal GCM = _DCM are all at the high level, causes the SYNC signal on the pin 8 of the gate 79B to go low, the SYNC signal then passing to the high level on the inverter pin 4 79C. The logical equation (15) is therefore satisfied.

The SYNC signal being at the high level, the signals applied to pins 12 and 13 of the gate 79B are at the high level in order to maintain the SYNC signal at the low level despite the passage of the clock signal TO at the low level. Thus, the signal SYNC remains at the low level until the signal GCM = DCM again passes to the high level and the clock signal T7 is at the high level. The SYNC signal then goes high and the SYNC signal low, so that the track length counter 62 can start counting again.

By way of example, it will be assumed that there are at least 7680 droplet times per linear inch (or 3023.622 droplet times per linear centimeter) of movement of the carriage 12 (Figure 1). If the network 15 makes it possible to obtain 240 pulses per inch (or 94,488 pulses per centimeter) of the network, we obtain at mimmum 32 (7680/240 or approximately 3024/95) droplet time between pulses emanating from the network 15. In order to having the certainty that there will be at least thirty-two droplets 23 between said pulses, it is necessary to appropriately control the speed at which the carriage 12 moves. When printing a character, there An accumulation of additional droplet times will therefore occur which must be available without affecting the positioning of neighboring droplets 23 and without creating perceptible horizontal positioning errors.

To this end, the network counter 78 (see Figure 2) includes a "low" master counter (GCML) 82, which counts from zero to thirty-one (thirty-one droplets 23) and a "high" master counter (GCMH) 83, which counts one unit each time the counter 82 is restored from thirty-one to zero (thirty-two droplets 23). The counter 78 also includes a "low" exclave counter (GCSL) 84, which counts in the same way as the counter 82, and a "high" slave counter (GCSH) 85, which counts in the same way as the counter 83.

The point counter 79 includes a master counter (DCM) 86 and a slave counter (DCS) 87. As previously mentioned, the counter 79 counts each of the droplets 23, except when the SYNC signal generated by the flip-flop 77 goes high, this signal causing the counter to deactivate.

Il est sous-entendu que la seconde partie de l'équation (18) ne s'applique pas lorsque n=₂₅ puisque seules les première et troisième parties de cette équation sont requises.We can write the following logical equations for counters 82 and 84, equations in which n = 1, 2, 3, 4 or 5, since each of these counters contains only five bits:

It is understood that the second part of equation (18) does not apply when n = ₂₅ since only the first and third parts of this equation are required.

We can write the following logical equations for counters 83 and 85, equations in which n = 6, 7, 8, 9 or 10 since each of these counters contains only five bi s:

An exemplary embodiment of the circuits constituting the counter 78 is illustrated by FIGS. 13, 14 and 15 which respectively represent the various logical elements constituting the counters 82 and 83, the single logical element constituting the counter 84 and the sole logical element constituting the counter 85, these various logical elements being manufactured by the firm Texas Instruments. In Figure 13, we chose n = 4 for the counter 82 and n = 10 for the counter 83. In Figures 14 and 15, we respectively chose n = 4 and n = 10 for the counters 84 and 85. It it is understood that each of the counters 82 and 83 must include similar types of elements for each of the first, second, third and fifth bits, and that each of the counters 84 and 85 must include similar types of elements for each of the sixth, seventh, eighth and ninth bits.

As shown in Figure 13, the network counter 78 includes a gate 90, which is analogous to gate 76 in Figure 7 and of which all unused logic inputs are maintained at a high logic level. Gate 90 receives respectively on its pins 13, 12 and 10 a GCSL signal, a GCSL ₂ signal and a GCSL ₃ signal. Each of these signals is received from the GCSL 84 counter (see Figures 2 and 14).

When these three input signals are at the high level, the gate 90 has on its pin 8 a low level signal, which is applied to the pin 13 of an inverter 91. The latter is of the same type as the inverter 57 'in Figure 5.

The inverter 91 reverses the low level signal applied to its pin 13 and converts it into a high level signal available on its pin 12. This last signal is applied to pins 3 and 10 of a flip-flop 92, which is of the same type that flip-flop 58 of Figure 5 and whose all unused logic inputs are maintained at a high logic level.

A signal GCSL ₄ is applied to pin 5 of flip-flop 92 (Figure 13) from pin 6 (output Q) of a flip-flop 93 (Figure 14) which comprises the counter GCSL 84. The signal GCSL ₄ goes high when the fourth bit present in the counter GCML 82 (Figure 13) is a logical zero (the signal GCSLM ₄ present on pin 6 of the flip-flop 92 is at the high level) during the passage to the high level of the clock signal T5.

The flip-flop 93 (see Figure 14) receives on its pin 12 (input CK) the clock signal T5 and on its pin 11 the signal GCSLM ₄ coming from pin 6 (output Q) of the flip-flop 92. Thus, if the signal GCML ₄ is at the high level when passing to the low level of the clock signal T5, the flip-flop 93 has a signal GCSL ₄ of high level on its pin 6 (output Q).

Consequently, when the clock signal Tl applied to pin 12 (input CK) of flip-flop 92 goes low and the signal GCSL _. and the input signal applied to pin 3 of flip-flop 92 are both high, flip-flop 92 has on its pin 8 (output Q) a high level GCML ₄ signal. This has the effect of increasing the binary value of the GCML 82 counter by one unit, thus satisfying the logic equation (17).

The flip-flop 92 receives on its pin 11 a signal GCSL ₄ coming from pin 8 (output Q) of flip-flop 93 of the counter GCSL 84. When the signal GCML ₄ applied to pin 3 of flip-flop 93 from pin 8 (output Q) of the flip-flop 92 is at the high level and that the clock signal T5 applied to pin 12 (input CK) of the flip-flop 93 goes to the low level, the signal GCSL ₄ goes to the high level.

The flip-flop 92 receives on its pin 9 a GCSL signal ≠ 31. This signal is high, except when the value of the GCSL 84 counter is equal to thirty-one. Consequently, when the clock signal Tl goes low and the signal GCSL ₄ is high, as well as the signal present on pin 10 of flip-flop 92 and that signal GCSL # 31, flip-flop 82 has a high level GCML ₄ signal on pin 6 (output Q). This corresponds to a logical zero in the fourth bit position of the GCML 82 counter. The second part of equation (18) is therefore satisfied.

The GCSL signal ≠ 31 is transmitted from pin 8 of a door 94 (Figure 13), which is of the same type as door 72 of Figure 7 and of which all the unused logic inputs are kept at a high logic level. Pins 1 to 5 of gate 94 receive signals GCSL to GCSL _{5 respectively} . Gate 94 therefore presents a high level signal on its pin 8, except when these five inputs are all at high level, which can only happen when the GCSL counter 84 has counted thirty-one times (this is i.e. zero to thirty-one), so that the five bit positions of counter 84 are all high. By way of example, this is illustrated by the high level signal GCLS ₄ present on pin 8 of flip-flop 93.

The GCML ₄ signal present on pin 6 (output O ) of the flip-flop 92 also goes high when a low level input signal is received on pin 2 (input C) since the signal on its pin 13 (input P) is always high. This pin 2 is connected to pin 6 of a door 95, which is of the same type as door 79A in FIG. 10. It is understood that a single door 95 is required for all the flip-flops (flip-flop 92 corresponds to the case where n = 4) relating to the five bits of the GCML counter 82. A low level signal is present on pin 6 of gate 95 when the clock signal T2 present on its pin 5 is at the same high level than the signal on its pin 4.

The input pin 4 of the door 95 is connected to the output pin 3 of the same door. Pin 3 presents a high level output signal whenever the signals applied to pins 1 and 2 of gate 95 are not at high level.

Pin 1 of gate 95 receives an EOC signal from flip-flop 55 (see Figures 2 and 9). The signal GD is applied to pin 2 of door 95 from the flip-flop 55 '(see Figures 2 and 16). The flip-flop 55 'is designed to satisfy the following logical equation:

As shown in Figure 16, the flip-flop 55 'comprises doors 96, 97 and 98 and an inverter 99. The doors 96 and 97 are of the same type as the door 79B of Figure 10 forming part of the flip-flop 77 and all their unused logic inputs are maintained at a high logic level. Gate 98 is of the same type as gate 79B of flip-flop 77, and all of its unused logic inputs are kept at a high logic level. The inverter 99 is of the same type as the inverter 57 'in FIG. 5.

Gate 96 receives on its input pin 2 a GP signal of network 15 (see Figure 1). The signal GP goes high each time one of the lines of the network 15 is detected by the circuits associated with the latter.

Gate 96 (Figure 16) receives on its pin 3 a GPL signal from pin 8 of gate 97. When the signal GP goes high, the GPL signal is high.

Gate 96 receives on its pin 1 the clock signal T7. Thus, when the latter signal goes high after the GP and GPL signals have gone high, the gate 96 has a low level signal GD on its pin 8 which is connected to pin 13 of the inverter 99.

This last signal is then converted into a high level signal GD available on pin 12 of the inverter 99. The logic equation (26) is therefore satisfied.

The signal GD present on pin 12 of the inverter 99 is applied to pin 11 of door 96 and to pin 2 of door 97. As long as the signal applied to pin 13 of door 96 is at the high level , the signal GD present on pin 12 of the inverter 99 remains at the high level, even after the passage to the low level of the clock signal T7. Pin 13 of gate 96 is connected to output pin 8 of gate 98. The latter receives respectively on its pins 9 and 10 the clock signal T5 and an LPG signal coming from pin 2 of inverter 99 .

When the signal GD goes to the high level, the signal GPL coming from pin 2 of the inverter 99 is at the low level. Since the clock signal T5 is also at the low level at this time, the input signal applied to pin 13 of gate 96 is at high level, so that the signal GD present on pin 12 of l the inverter 98 remains at the high level after the passage to the low level of the clock signal T7.

The signal GD being at the high level, the passage to the high level of the following clock signal Tl, which is applied to pin 3 of door 97, makes it possible to obtain on pin 8 of door 97 a signal GPL of level low. This pin 8 is connected to pin 1 of the inverter 99, so that the appearance of a low level LPG signal results in obtaining a high level LPG signal on pin 2 of this inverter . As previously mentioned, pin 8 of door 97 is also connected to pin 3 of door 96.

Consequently, the signal GPL passing at the high level due to the passage at the high level of the clock signal Tl after the passage at the high level of the signal GD, the application of the following clock signal T5 to pin 9 of the gate 98 causes a low level signal to appear on pin 8 of this door. As a result, the signal applied to pin 13 of door 96 goes low, so that pin 8 of this same door has a high level signal GD. This has the effect of bringing the signal GD present on pin 12 of the inverter 99 to a low level. The logic equation (27) is therefore satisfied.

The signal LPG is applied to pin 10 of door 97, whose pin 11 is connected to pin 3 of door 98. Thus, if the signal applied to pin 11 of door 97 is at the high level while the signal GPL is also at the high level, this last signal remains at the high level after the passage to the low level of the clock signal Tl.

The signal present on pin 3 of door 98 is high, except when the signals applied to pins 1 and 2 of this same door are high. Pin 1 of gate 98 receives a signal GP from L, pin 8 from inverter 99, which receives signal GP on its pin 9. Gate 98 receives on its pin 2 the clock signal T7.

As a result, as long as the network 15 in Figure 1 generates a high level GP signal, the GP signal present on pin 1 of door 98 (Figure 16) remains low so that a high level signal remains on pin 3 of this door. The GPL signal therefore remains at the high level as long as the network 15 continues to provide a high level GP signal.

It is understood that the signal GP emanating from the network 15 remains at the high level for at least three droplet times. As previously mentioned, there are at least thirty-two drop times between the start of each of two consecutive GP signals.

When the GP signal goes low, the GP signal on pin 1 of gate 98 goes high. When the clock signal T7 goes high, the signals applied to pins 1 and 2 of door 98 are both high so that a low level signal is obtained on pin 11 of door 97. As a result, the LPG signal goes high and lowers the LPG signal. The signal GPL therefore remains at the high level as long as the signal GP is present, then passes to the low level when passing to the high level of the following clock signal T7. The GPL signal is therefore at the high level when the signal-GP goes to the high level.

The first part of the logic equation (18) is therefore satisfied when the signal GD is at the high level to indicate that a pulse has been generated by the network 15 and the clock signal T2 goes to the high level. The flip-flop 92 (Figure 13) and each of the flip-flops corresponding to each of the other four bits of the GCML counter 82 are then set to zero so that the counter 82 can start counting. The first part of the logic equation (18) is therefore satisfied when the counter 82 starts counting again.

As previously mentioned, pin 1 of gate 95 (Figure 13) receives the EOC signal from the scale 55. This signal goes low after printing a character, as will be seen below. The low level EOC signal causes all the flip-flops included in the GCML 82 counter to zero when the clock signal T2 goes high. The third part of the logical equation (18) is then satisfied.

As previously indicated, only the first and third parts of the logical equation (18) are necessary when n = 5. This is due to the fact that the GCML 82 counter performs a count without looping, i.e. counts from zero to thirty-one and then stops until it is set to zero by the appearance of a high level EOC signal or a high level GD signal. The second part of the logical equation (18) is therefore useless when n = 5 since the signal GCML _; - must only be at the high level in order to reach the value thirty-one. Consequently, pins 9, 10 and 11 of flip-flop 92 in the case where n = 5 are unused and kept at a high logic level.

The signal GCSL ₄ present on pin 8 (output Q) of the flip-flop 93 forming part of the counter GCSL 84 goes high when the signal GCML ₄ is high and the clock signal T5 goes low. This result is obtained by applying the signal GCML ₄ to pin 3 of flip-flop 93 and the clock signal T5 to pin 12 (input CK) of this same flip-flop.

If the GCML ₄ signal (instead of the GCML ₄ signal) is at the high level, the GCSL ₄ signal present on pin 6 (output Q) of the flip-flop 93 goes to the high level when the clock signal goes low. T5. Logic equations (19) and (20) are therefore satisfied, the GCSL counter 84 being set to the same value as the GCML counter 82 at the clock signal T5 after the value of counter 82 has been increased by one unit at clock signal Tl.

The value of the GCMH 83 counter is increased by one every time. that the GCML 82 counter has reached the value of thirty-one. Consequently, for n = 10, a flip-flop 100 (see Figure 13) provides a signal GCMHI0 on its pin 8 (output Q) and a signal GCMHI0 on its pin 6 (output Q). The flip-flop 100 is of the same type as the flip-flop 58 of FIG. 5 and all of its unused logic inputs are maintained at a high logic level. Pin 12 (input CK) of flip-flop 100 receives a signal Tl.GD.GCSL = ₃₁ from pin 6 of inverter 91 in Figure 13. This signal can only be at high level when the clock signal T1, the signal GD and the signal GCSL = 3 ₁ are all at the high level.

A gate 101, which is of the same type as gate 56 of FIG. 5 and of which all the unused logic inputs are kept at a high logic level, receives respectively on its pins 9, 10 and 11 the signal GCSL = 3 ₁ , the signal GD and the clock signal Tl. When these three input signals are at the high level, the gate 101 has a low level signal on its pin 8. The latter is connected to pin 5 of the inverter 91, and therefore the low level signal present on pin 8 is converted into a high level signal which is obtained on pin 6 of the inverter 91 and applied to pin 12 of flip-flop 100 when the signal T1.GD.GCSL = 31.

The gate 90 receives respectively on its pins 1, 2, 4 and 5 a signal GCSH ₆ , a signal GCSH ₇ , a signal GCSH ₈ and a signal GCSH ₉ from the flip-flops corresponding to flip-flop 100. When all these signals are at the level high, flip-flop 90 applies a low level signal to pin 3 of the inverter 91 from its pin 6, this signal being converted into a high level signal present on pin 4 of the inverter and applied to pins 3 and 10 of scale 100.

The latter receives on its pin 5 a signal GCSH ₁₀ from pin 6 (output Q) of a scale 102 (see Figure 15) that includes the GCSH 85 counter. is of the same type as flip-flop 58 in Figure 6 and all of its unused logic inputs are maintained at a high logic level.

Consequently, when the signals applied to pins 3 and 5 of flip-flop 100 are at the high level and that the signal applied to pin 12 of this flip-flop goes to low level, the flip-flop presents a signal GCSMH ₁₀ of high level on its pin 8 (output Q). This results in an increase of one unit in the value of the GCMH 83 counter. The logic equation (22) is therefore satisfied for n = 6, 7, 8, 9, 10.

The bacule 100 receives on its pin 11 a signal GCSH10 from pin 8 (output Q) of the scale 102 that includes the counter GCSH 85. When the latter signal is high, only the signal present on pin 10 of the scale 100 is at the high level and the signal present on the pin 12 goes to the low level due to the passage to the low level of the clock signal Tl, the flip-flop 100 presents a signal GCSMH ₁₀ high level on pin 6 (output Q).

The signal GCSH ₁₀ present on pin 8 of the flip-flop 102 is at the high level when the clock signal T5 goes to the low level and the signal GCMH ₁₀ is at the high level. The signal GCSH ₁₀ present on pin 6 (output Q) of flip-flop 102 is high when the clock signal T5_ goes low and the signal GCSMH ₁₀ is at the high level. Logical equations (24) and (25) are therefore satisfied for n = 6, 7, 8, 9 or 10.

On the other hand, pin 2 (input C) of the flip-flop 100 is connected to pin 6 of the door 101. Pins 3 and 4 of the latter receive respectively the clock signal T2 and the signal EOC. When these two signals are at the high level, a low level signal is obtained on pin 6 of gate 101 and applied to pin 2 (input C) of flip-flop 100. Since the signal applied to pin 13 (input P) of flip-flop 100 is always high, the signal GCMH ₁₀ present on pin 6 (output Q) of flip-flop 100 goes high.

Each of the two parts of the logical equation (23) is therefore satisfied for n = 6, 7, 8, 9 or 10.

Although the above description of the flip-flop 100 relates to the case in which n = 10, it will be noted that the signal GCML ₁₀ in principle never goes to the high level during counting because this would indicate that the counter 78 does not have sufficient capacity. However, for each of the flip-flops corresponding to flip-flop 100 in the case where n = 6, 7, 8 and 9, the GCML signal can normally go to the high level during counting.

The following logical equations can be written in relation to the different states of the DCM 86 and DCS 87 counters that the point counter 79 contains:

In each of the logic equations above, n = 1, 2, 3, 4, 5, 6, 7, 8, 9 or 10. It will be noted that the signal GCML or GCML _not is used in logical equation (33) in the case where n = ₁ , 2, 3, 4 or 5, and that the signal GCMH or GCMH is used in the case where n = ₆ , 7, 8, 9 or 10.

An exemplary embodiment, by means of logic elements manufactured by the firm Texas Instruments, of the logic circuits constituting the point counter 79 is shown in FIGS. 11 and 12 in the case where n = 10. It is understood that the counter 79 includes similar elements for each of the other nine bits (n = 1, .. 9).

The counter 79 includes a door 105 (Figure 11) which is of the same type as the door 59 (see Figure 4) of the PCM counter 53, and of which all the unused logic inputs are maintained at a high logic level. The gate 105 receives respectively on its pins 1 to 10 the signals DCS, to DCS ₉ . When each of these signals is high, a low level signal appears on pin 9 of gate 105 and is applied to pin 13 of inverter 81, which converts it to a high level signal available on pin 12. This last signal is applied to pins 4 and 10 of a flip-flop 106 which is of the same type as flip-flop 58 (see Figure 4) of the PCM counter 53 and of which all the unused logic inputs are kept at a high logic level.

The flip-flop 106 receives on its pin 5 a DCSI0 signal emanating from pin 6 (output Q) of a flip-flop 107, which is one of the ten flip-flops constituting the DCS counter 87 which comprises the point counter 79. The flip-flop 107 is of the same type as flip-flop 58 (see Figure 5) of the PCM counter 53 and all of its unused logic inputs are maintained at a high logic level.

Pins 3 and 11 of flip-flop 106 are both connected to pin 2 of inverter 81. The signal applied to this latter pin is obtained, after inversion, on pin 1 of the inverter and applied to pin 8 a door 108, which is of the same type as door 56 (see Figure 5) of the PCM counter 53 and of which all the inputs unused logic is maintained at a high logic level. Gate 108 receives on its pin 9 the EOC signal emanating from the EOC flip-flop 55 (see FIGS. 2 and 9) and, on its pin 1, the SYNC signal emanating from the flip-flop 77 (see FIGS. 2 and 10). Consequently, when the EOC signal and the SYNC signal are both at the high level, the gate 108 has a low level signal on its pin 8, so that a high level signal is applied to each of the pins 3 and 11. of scale 106.

The flip-flop 106 receives on its pin 12 (input CK) the clock signal T1. Thus, when the signals SYNC and EOC are both at the high level, the signal DCS ₁₀ is at the high level and the input signal received from pin 12 of inverter 81 is high, flip-flop 106 provides a high level DCMI0 signal on pin 8 (output Q) when the clock signal T1 goes low, if the DCM signal ₁₀ was at low level, or keep it high if it was already at this last level. Each time the DCM signal ₁₀ goes high, the value of the DCM counter 86 increases by one. The logical equation (28) is therefore satisfied.

The flip-flop 107 receives on its pin 12 (input CK) the clock signal T5 and on its pin 10 the signal DCMI0 coming from pin 6 (output Q) of the flip-flop 106. Therefore, if the signal DCM ₁₀ is at the high level when switching to the low level of the clock signal T5, the flip-flop 107 has a DCS signal of high level on its pin 6 (output Q). If the signal DCS ₁₀ is already at the high level, it remains at this last level.

Flip-flop 106 receives on its pin 9 a DCS signal ₁₀ coming from pin 8 (output Q) of flip-flop 107. This signal is at high level when the DCM signal ₁₀ coming from pin 8 of flip-flop 106 is at high level since it is applied to pin 4 of flip-flop 107. The signal DCSI0 only goes high when the clock signal T5 applied to pin 12 (input CK) of flip-flop 107 goes low. It stays at this last level until the signal DCM ₁₀ obtained on pin 6 (output Q) of flip-flop 106 goes high, which passes the signal DCS ₁₀ at high level and DCS ₁₀ signal at low level. Logical equations (30) and (31) are thus satisfied.

When the flip-flop 106 receives on its pins 10 and II high level signals emanating from pins 12 and 2 respectively of the inverter 81, and receives on its pin 9 a DCS signal ₁₀ high level coming from pin 8 (output Q ) of flip-flop 107, flip-flop 106 has a high level DCMI0 signal on its pin 6 (output Q) when the clock signal Tl goes low. In this case it is a logical zero which occupies the tenth bit position in the DCM counter 86. This satisfies the first part of the logical equation (29).

Furthermore, the point counter 79 cannot count when the SYNC or EOC signal is low. As previously mentioned, this occurs when it is desired to interrupt the counting operation performed by this counter so that its value can become equal to that of counter 78.

Although the above description of flip-flops 106 and 107 corresponds to the case in which n = 10, it will be noted that the signals DCMI0 and DCS ₁₀ in principle never pass to the high level during counting because this would indicate that the counter 79 does not have sufficient capacity. However, in the case of all the flip-flops corresponding to flip-flops 106 and 107 for n = 1, 2, 3, 4, 5, 6, 7, 8 and 9, the DCM and DCS signals can normally go to the high level during counting.

Gate 108 of Figure 11 receives respectively on its pins 3 and 5 the clock signal T2 and the EOC signal from flip-flop 55 (see Figure 9). When these two input signals are high, the gate 108 has a low level signal on its pin 6. This last signal is applied to pin 2 (input C) of flip-flop 106 so that the latter can present a high level DCMI0 signal on its pin 6 (output Q) given that its pin 13 (input P) is still high.

The second part of the logic equation (29) is therefore satisfied when the clock signal T2 and the signal EOC are both high because the end of a character occurs. The flip-flop 106 and the flip-flops corresponding to each of the other nine bits in the DCM counter 86 that the point counter 79 includes are set to zero so that the latter counter starts counting again from zero. The second part of the logic equation (29) is therefore satisfied when the counter 79 starts counting again at the start of another character. This reset takes place for the last time when the clock signal T2 appears during the last droplet time relating to the previous character.

The counter 79 includes a door 110 (see FIG. 12) of which all the unused logic inputs are kept at a high logic level. This door can, for example, be of the type sold by Texas Instruments under the reference SN7451 (J).

The gate 110 receives respectively on its pins 2 and 3 a signal GCMH ₁₀ emanating from the rocker 100 (Figure 11) of the counter GCMH 83 and the signal DCM ₁₀ emanating from pin 6 (output Q) of flip-flop 106. When these two signals are at the high level, the gate 110 presents a signal BTT ₁₀ ≠ low level on its pin 6.

Similarly, the flip-flop 110 receives respectively on its pins 4 and 5 a signal GCMH ₁₀ emanating from flip-flop 100 and the DCMI0 signal emanating from pin 8 (output Q) of flip-flop 106. When these signals are both high, the signal BIT ₁₀ ≠ obtained on pin 106 of door 110 is at the low level. The logical equation (33) is therefore satisfied.

Gate 110 receives respectively on its pins 1 and 13 a GCML signal ₁ , emanating from one of the flip-flops, corresponding to flip-flop 92 of FIG. 13, from the GCML counter 82, and a DCM signal, emanating from one of the flip-flops, which corresponds to flip-flop 106 in Figure 11, of the DCM 86 counter. When these two signals are at the high level, a signal BIT ₁ ≠ low level is present on pin 8 of door 110.

Similarly, the gate 110 receives respectively on its pins 10 and 9 a signal GCML ₁ , coming from a flip-flop corresponding to flip-flop 92 of a DCM ₁ signal coming from a flip-flop corresponding to bacule 106. When these two signals are high, the signal BIT ₁ ≠ present on pin 8 of door 110 is low. These signals also satisfy the logic equation (33).

The gate 80 shown in Figure 10 receives respectively on pins 1 to 7 and 10 to 12 the signals BIT ₁ ≠ at BIT ₇ ≠ and BIT ₈ ≠ at BIT ₁₀ ≠. When all these signals are at the high level, the gate 80 has on its pin 9 a signal GCM = _DCM of low level. Therefore, a signal GCM = DCM of high level is obtained on pin 6 of the inverter 81, which makes it possible to satisfy the logic equation (32).

As previously mentioned, the voltage register 64 of FIG. 2 receives the first ten bits coming from the FROS memory 51. The following logical equations can be written in relation to this register:

In the above logical equations relating to register 64, n = 1, 2, 3, 4, 5, 6, 7, 8, 9 or 10.

The register 64 comprises ten flip-flops (one of them is represented at 111 in FIG. 17 for n = 1). The flip-flop 111 is of the same type as the flip-flop 58 of FIG. 5, and all of its unused logic inputs are kept at a high logic level.

The flip-flop 111 receives on each of its pins 3 and 10 the signal RLS = 0 coming from pin 12 of the inverter 69 (Figure 7) that comprises the track length counter 62. Furthermore, the flip-flop 111 receives respectively on its pins 5 and 12 (input CK) a FROS signal from the FROS memory 51 (Figure 2) and the clock signal T5.

When the signals RLS = 0 and FROS ₁ are both at the high level, the flip-flop 111 supplies on its pin 8 (output Q) a signal V ₁ of high level during the passage to the low level of the clock signal T5, thus satisfying the logical equation (34) for n = 1.

The flip-flop 111 receives from the FROS memory 51 a signal FROS ₁ which is applied to its pin 9. Therefore, if the signals RLS = 0 and FROS ₁ are both at the high level, the flip-flop 111 provides a signal V ₁ of high level on its pin 6 (output Q) when the clock signal T5 goes to low level. This satisfies the logical equation (35) for n = 1.

Consequently, when the RLM counter 65 of FIG. 2 which the stroke length counter 62 includes is at a zero value, the state of each of the bits contained in the voltage register 64 is applied to a digital / analog converter 112 , which converts the digital signal received from register 64 into an analog voltage applied to a charge electrode excitation circuit 113, which amplifies the analog voltage received from the converter.

The logic equations relating to a so-called charge electrode voltage gate 115, which determines the moment when the voltage is applied to the converter 112, are the following

The gate 115 determines whether it is the so-called voltage register 64 or a so-called induction compensation read-only memory (GIROS) 116 which must supply the converter 112 with the digital signal representing the voltage which must be applied to the charging electrode. 24. This electrode must in fact receive a voltage making it possible to compensate for the charges induced in the ink droplets 23 which are not used for the purposes of printing by the charged droplets which precede them.

Only the voltages induced by the two charged droplets which precede an unused droplet for printing purposes are used to compensate for the induction. However, the number of previous droplets could possibly be greater than 2, in which case additional circuits would be necessary.

There is shown in Figure 18 an embodiment of the door 115 which uses the use of various logic elements manufactured by the firm Texas Instruments. It is understood that the gate 115 must include elements similar to those represented in FIG. 18 for each of the nine remaining bits, that is to say from the second to the tenth bit, in the same way as those represented in the case where n = ₁ in Figure 18.

Door 115 includes doors 117, 118 and 118 ', an inverter 119 and a door 120. Doors 117 and 118 are both of the same type as door 76 (see Figure 7) used in the RLM 65 meter that the stroke length counter 62 and of which all the unused logic inputs are maintained at a high logic level. Gate 117 receives respectively on its pins 1, 2, 4 and 5 the signals TO, Tl, T2 and T3, which are the inverse of the clock signals T0, Tl, T2 and T3. Whenever any of the signals T0, Tl, T2 and T3 is at the low level, thus indicating that the corresponding reverse clock signal is at the high level (the signal TO, for example, being at the low level when the signal TO is at the high level), the door 117 of FIG. 18 has a high level signal on its pin 6. This signal is applied to pins 1 and 13 of the door 118 and to the pin 2 of the door 118 ' , which is of the same type as door 56 in Figure 5.

The signal V ₁ obtained on pin 8 (output Q) of flip-flop 111 (Figure 17) of register 64 is applied to pin 5 of door 118. The latter receives on its pin 2 the signal RLM = 0 coming from the pin 10 of the inverter 79 (see Figure 7) of the RLM 65 counter that includes the counter 62. The door 118 of Figure 18 receives on its pin 4 a signal V ≠ 1 emanating from pin 9 of the door 120, which is of the same type as gate 59 (FIG. 5) of the PCM counter 53 which the counter 52 comprises and of which all the unused logic inputs are maintained at a high logic level.

When all the signals applied to pins 1, 2, 4 and 5 of door 118 of Figure 18 are at the high level, this door has on its pin 6 a low level signal which is applied to pin 10 of door 118 '. Therefore, when a low level signal is present on pin 10 of door 118 ', the latter has on its pin 8 a CEV signal ₁ of high level. This satisfies the first part of the logical equation (36).

Gate 118 receives on its pin 9 a signal GI ₁ from a register 121 called induction compensation (see Figure 2). Gate 118 receives on its pin 12 the signal RLM = 0 coming from pin 10 of the inverter 69 (see Figure 7) from the counter RLM 65 that comprises the counter 62, and, on its pin 10, a signal V = 1 emanating from pin 8 of the in- pourer 79, which receives on its pin 9 the signal V ≠ 1 coming from pin 9 of the gate 120.

When the signals applied to pins 9, 10, 12 and 13 of door 118 are all high, door 118 has a low level signal on its pin 8, which is connected to pin 9 of door 118 '. When a low level signal is present on pin 9 of the latter door, it has on its pin 8 a CEV ₁ signal of high level. This satisfies the third part of the logical equation (36).

The door 118 'receives on its pin 13 a signal GI ₁ coming from the register 121 of Figure 2. The door 118' receives on its pin 1 the signal RLM # O coming from the pin 8 of the door 75 (see Figure 7) of the RLM counter that the counter 62 contains.

When all the signals applied to pins 1, 2 and 13 of door 118 ′ are at high level, this door provides on its pin 11 a low level signal and therefore has on its pin 8 a CEV ₁ signal of high level . This satisfies the second part of the logical equation (36).

The gate 120 of FIG. 18 receives respectively on its pins 1, 2, 3, 4, 5, 6, 7, 10, 11 and 12 the signals V ₁ , V ₂ , V ₃ , V ₄ , V ₅ , V ₆ , V ₇₁ V ₈ , V ₉ and V ₁₀ . The signal V ₁ is obtained on pin 8 (output Q) of the flip-flop 111 (Figure ₁ 7) of register 64 however that the voltages V ₂ to V ₁₀ are the inverses of the signals relating to bits 2 to 10 which are stored in register 64 and are obtained at the output Q of the flip-flops corresponding to flip-flop 111. When all the input signals applied to pins 1 to 7 and 10 to 12 of the door 120 are at the high level, this door has on its pin 9 a signal V ≠ 1 of low level which is applied to pin 9 of the inverter 119 and converted into a signal V = 1 of high level which is available on pin 8 of the latter. This satisfies the logical equation (37).

It will be noted that the signal V = 1 is at the high level only when the binary value of the register 64 of Figures 2 and 17 is equal to 1, which means that all the bits except the first are at the low level. The signal V = ₁ is used in the EOC flip-flop 55 in FIG. 9 to make the EOC signal go high. The following logical equations are used relative to flip-flop 55:

The flip-flop 55 includes a gate 123 (see FIG. 9), which is of the same type as the gate 79B (see FIG. 10) of the flip-flop SYNC 77 and of which all the unused logic inputs are kept at a high logic level, as well as an inverter 124 (see FIG. 9), which is of the same type as the inverter 57 ′ in FIG. 5. The door 123 receives respectively on its pins 2, 3 and 1 the signal V = ₁ coming from pin 8 of l 'inverter 119, the signal RLM = 0 from pin 10 of the inverter 69, and the clock signal T7.

When all the signals applied to pins 1, 2 and 3 of door 123 are at the high level, the EOC signal present on pin 8 of this door goes to low level. The EOC signal is applied to pin 1 of the inverter 124, where it is inverted, a high level EOC signal being obtained when the clock signal T7, the signal V = ₁ and the signal RLM = 0 are all three at the high level.

This high level EOC signal indicates that the next character can begin at the next droplet time if a high level GP signal from the array 15 of Figure 1 begins to appear during this droplet time. This high level EOC signal is used, as previously mentioned, for the purpose of transferring data from the PROS memory 50 (FIG. 2) to the pointer 52 and for resetting the point counter 79.

The gate 123 of FIG. 9 receives respectively on its pins 12 and 13 the signal EOC, coming from pin 2 of the inverter 124, and a clock signal T4, which is the inverse of the clock signal T4. Therefore, when the EOC signal goes low when the clock signal T7 appears, the signals applied to pins 12 and 13 are at the high level so as to maintain the EOC signal at its high level after the switching to low level of clock signal T7.

During the passage to the high level of the clock signal T4 associated with the next droplet time after the passage to the high level of the signal EOC, the signal T4 present on pin 13 of the door 123 passes to the low level in order to cause the passage to the high level of EOC signal and switching to low level of EOC signal. The flip-flop 55 remains in this state until the next passage at the high level of the signals applied to the terminals 1, 2 and 3 of the gate 123. The flip-flop 55 therefore satisfies the logic equations (38) and (39).

The seven most significant bits obtained at the output of gate 115 (Figure 2) are also transmitted to a so-called first order induction register (FOI) 125, the three most significant bits of this group of seven bits being transmitted to a so-called second order induction register (SOI) 126, which comprises a master register (SOIM) 127 and a slave register (SOIS) 128.

The FOI register 125 comprises seven flip-flops, one of which has been represented at 129 in FIG. 20 in the case where n = 2. Flip-flop 129, which is of the same type as flip-flop 128 (see Figure 5) of the PCM counter 53 and of which all the unused logic inputs are kept at a high logic level, satisfies the following two logic equations in which n = 1, 2 , 3, 4, 5, 6 or 7:

The flip-flop 129 receives on its pin 3 the signal CEV _S coming from the gate 115. When the clock signal T2, which is applied to pin 12 (input CK) of the flip-flop 129, goes to low level and that the signal CEV ₅ is at the high level, the flip-flop 129 receives on its pin 8 (output Q) a JTF ₂ signal of high level. This satisfies logical equation (40), the second bit contained in register 125 being the fifth of the ten bits received from gate 115. This is due to the fact that register 125 stores the digital signals corresponding to the seven bits of weight le higher of the ten bits received from register 64.

If the signal CEV ₅ , which is applied to pin 10 of flip-flop 129 from gate 115, is at the high level, flip-flop 129 provides on its pin 6 (output Q) a JTF ₂ signal of high level. This satisfies the logical equation (41).

The SOIM register 127 (FIG. 2) receives the three most significant bits obtained at the output of gate 115, while the remaining seven most significant bits are applied to the JTF register 125. The two logic equations below are therefore applicable to the SOIM register 127 in the case where n = ₁ , 2 or 3:

FIG. 21 shows a flip-flop 130 forming part of the SOIM register 127, in the case where n = 2 (case corresponding to that of flip-flop 129 in FIG. 20). The flip-flop 130, which is of the same type as flip-flop 58 (Figure 4) of the PCM counter 53 that includes the pointer 52 and whose all unused logic inputs are maintained at a high logic level, receives on its pin 3 the signal CEV ₉ emanating from gate 115. When the latter signal is high and the T2 clock signal applied at pin 12 (input CK) of flip-flop 130 goes low, flip-flop 130 provides a SOIM ₂ signal of high level on its pin 8 (output Q). This satisfies the logical equation (42) for n = 2.

The flip-flop 130 receives on its pin 10 the signal CEVq from the gate 115. When this signal is at the high level and that the clock signal T2 goes to the low level, the flip-flop 130 provides a signal SOIM ₂ of high level on its pin 6 (output Q). This satisfies the logical equation (43) for n = 2.

It is understood that the SOIM register 127 contains two other flip-flops, which are identical to flip-flop 130. These flip-flops correspond to the cases where n = 1 and n = 3.

The three bits contained in the SOIM register 127 are transferred to the SOIS register 128 (FIG. 2) when the clock signal T6 appears. This occurs after the memory 116 has been addressed using the seven bits contained in the JTF register 125 and the three bits contained in the SOIS register 128. Thus, the transfer of the three bits contained in the register 128 is performed one cycle before that of the bits of register 125 since the transfer of the bits of register 127 to register 128 takes place upon the appearance of the clock signal T6 since the transfer of the output of memory 116 to register 121 coincides with the clock signal T4.

The register SOIS 128 comprises three flip-flops, one of which is represented at 131 in Figure 22 for n = 2. The flip-flop 131 is of the same type as the flip-flop 58 (see Figure 5) of the PCM counter 53 that includes the pointer 52 and all of its unused logic inputs are maintained at a high logic level.

The two logical equations below are applicable to the SOIS 128 register of Figure 2 for n = 1, 2 or 3:

The flip-flop 131 receives on its pin 3 the SOIM signal ₂ coming from pin 8 (output Q) of the flip-flop 130 (Figure 21) of the SOIM register 127, and on its pin 12 the clock signal T6. Therefore, when the signal SOIM ₂ is at the high level and the clock signal T6 goes to the low level, the flip-flop 131 presents a signal SOIS ₂ of high level on its pin 8 (output Q). This satisfies logical equation (44) for n = ₂ .

The flip-flop 131 also receives on its pin 10 the SOIM signal ₂ coming from pin 6 (output Q) of the flip-flop 130 (Figure 19) that comprises the SOIM register 127. Consequently, when the signal SOIM ₂ is at the high level and that the clock signal T6 goes low, the flip-flop 131 receives a signal SOIS ₂ of high level on its pin 6 (output Q). This satisfies the logical equation (45).

Each of the three flip-flops (including flip-flop 131) of the SOIS register 128 therefore contains the same bit as the corresponding flip-flop of the SOIM register 127. However, the transfer of the bits of the register 127 to the register 128 is delayed, so that they are applied to the memory 116 a cycle later than the bits of the JTF register 125, the two parts of the address of the memory 116 constituted by the contents of the register 128 and by that of the register 125 respectively concerning the compensation of the voltage induced in a given droplet (which has not received any charge) by the second and by the first charged droplets which precede it.

Register 121 has eight flip-flops (one of which is represented at 132 in Figure 19 for n = 2), each flip-flop corresponding to a different bit in the case where n varies from 1 to 8. Thus, the eight-bit output of the memory 116 of FIG. 2 is transferred to the register 121 when the clock signal T4 goes low. If the value of the RLM counter 65 (FIG. 6) of the track length counter 62 is not zero, the signal RLMiO being at the high level, the gate 115 of FIG. 2 transmits the eight bits of the register 121 to the converter 112.

The flip-flop 132, which is of the same type as the flip-flop 58 of FIG. 4 forming part of the PCM counter 53 that the pointer 52 includes and whose all unused logic inputs are kept at a high logic level, receives on its pin 3 the signal GIROS ₂ supplied by memory 116. When the clock signal T4, which is applied to pin 12 (input CK) of flip-flop 132, goes to low level, signal GIROS ₂ being high, flip-flop 132 has a high level signal GI ₂ on its pin 8 (output Q).

Flip-flop 132 receives a signal GIROS ₂ , which is the inverse of the GIROS ₂ signal, on its pin 10. If the signal GIROS ₂ is at the high level, a signal GI ₂ of high level is obtained on pin 6 (output Q) of the flip-flop 132 when the clock signal T4 goes to the low level. This occurs immediately after application of the previous voltage signal to the converter 112 through the gate 115 since the latter signal is applied during the time interval which passes between the passage to the high level of the signal. clock signal TO and the transition to the low level of the clock signal T3. This time interval is that during which the voltage is applied to the charging electrode 24, the formation of the droplets 23 occurring approximately during the passage to the low level of the clock signal Tl, as shown in FIG. 3. Using the clock signals T2 and T3 after the formation of the droplets to allow the charging electrode 24 (FIG. 2) to continue to receive the required voltage, it is guaranteed that a charge is applied to a droplet 23 even if the formation of the latter takes place after the passage to the low level of the clock signal Tl.

The clock signals are synchronized with the formation of the droplets 23 so that it occurs as precisely as possible between the passage to the high level of the clock signals T1 and T2. One technique for achieving this result is described in the U.S. Patent. No. 4,150,384.

The flip-flop 132 satisfies the following two logical equations for n = 2:

It is understood that similar flip-flops must be used for n = 1, 3, 4, 5, 6, 7 and 8 in order to satisfy the two logical equations (46) and (47).

With regard to the operation of the apparatus of the present invention, the printing of a character requires the transfer to the PROS 50 memory (Figure 2) of an eight-bit character code constituting an address and identifying the character to be printed. There is then obtained at the output of the memory 50 a word of sixteen bits defining the position of the FROS memory 51 where the data used for printing this character begin.

The sixteen-bit word from memory 50 is transferred to the PCM counter 53 of pointer 52 during the last drop time of the previous character, as shown in Figure 3. This occurs when the clock signal T2 goes low , that the signal EOC coming from the flip-flop EOC 55 (Figures 2 and 9) is at the high level, and that the signal GD coming from the flip-flop GD 55 '(see Figures 2 and 16) is at the high level.

This would occur, even if there were no previous characters, for a corresponding drop time immediately before the first drop time of the character to be printed. This would require that the scale 55 causes the EOC signal applied to pin 2 of the inverter 124 to go high, while the clock signal T7 is at the high level during a droplet time corresponding to that preceding the last droplet time of the preceding character. .

In either case, the sixteen-bit word from memory 50 is transferred to the PCM counter 53 during the droplet time preceding the first droplet time of the character to be printed. This word is transferred to the PCS counter 54 of the pointer 52 when the clock signal T5 relating to the last droplet time of the preceding character appears.

The sixteen-bit word contained in the counter 53 is directly transferred to an address of the FROS memory 51. This address identifies the part of the memory 51 from which the sixteen-bit word will be obtained.

Ten of the sixteen bits of this word define a voltage and are transferred to the voltage register 64 when the clock signal T5 appears, relating to the same droplet time as that during which the sixteen-bit word is transferred to the PCM counter. At the same time, the remaining six bits of the word, which define a range length, are transferred to the RLM counter 65 of the range length counter 62. The value of the latter specifies the number of droplet times unused for the purposes of the impression which must pass before the printing of a droplet 23. This value can vary from zero to sixty-three and represents the distance separating the droplet 23 to be printed from the droplet 23 printed or a margin, if it is the first droplet to print. It is understood that one of the droplets 23 may not be printed each time the counter 62 is set to the value sixty-three, for example when the character considered is a dot.

It is also understood that none of the droplets 23 cannot be printed during the time interval during which a character is to be printed. This would correspond, for example, to an empty space between characters. To this end, the PCM counter 53 is set to a value such that the register 64 and the RLM counter 65 are respectively set to a value of one and to a value of zero by the FROS memory 51, and this, permanently.

The dot counter 79 directly counts the droplets 23, except when it is necessary to interrupt this operation to allow the network counter 78 to reach the same value as the counter 79. This only occurs when four consecutive droplets 23 or more should not be used for printing.

The counter 79 is set to zero during the presence of the clock signal T2 during the last droplet time relating to the preceding character. This requires that the EOC signal and the T2 clock signal are both high. The GCML 82 and GCMH 83 counters that the counter 78 includes are also zeroed at this time.

The counter 78 counts from zero to thirty-one, which corresponds, if its reset is taken into account, to the minimum of thirty-two drop times between the pulses relating to the network, since the network 15 ( Figure 1) provides 240 pulses per inch of 2.54 centimeters, (i.e. 94.488 lines per centimeter) and that there is a total of at least 7680 droplet times per linear inch (i.e. 3023.622 droplet times per linear centimeter ) for moving the carriage 12.

The counter 78 counts at the same frequency as that at which the droplets 23 are generated. As previously mentioned, the speed at which the carriage 12 moves (Figure 1) is such that it does not cover the distance separating the pulses generated by the network 15 in thirty-two droplet times. It is therefore necessary that the counter 78 stops counting until the appearance of the signal GD of high level following provided by the rocker GD 55 '. However, the point counter 79 continues its progressive counting.

The counter 79 stops counting when it reaches a value greater than that of the network counter 78 and when the value reached by the RLM counter 65 which the range length counter 62 comprises is greater than three (the RLM signal> 3 is high) to indicate that there are four or more consecutive 23 droplets which should not be used for printing. When this occurs, a high level SYNC signal appears on pin 4 of the inverter 79C (see Figure 9) of the flip-flop 77 to interrupt the operation of the counter 79 (Figure 2) and of the counter 62. This has the effect synchronize the position of the carriage 12 (FIG. 1) and that where the droplets 23 used for the purposes of printing must strike the sheet of paper or other support 14.

As soon as the value of the counter 78 is equal to that of the counter 79, the flip-flop 77 (Figure 10) changes state when the clock signal T7 goes high, so that the SYNC signal goes high and that the SYNC signal goes low. This allows counters 79 and 62 to start counting again.

The deactivation and function of the counter 79 are illustrated in Figure 4. As this figure shows, the value reached by the counter RLM 65 during the first part of the droplet time is equal to x + 1> 4, where x is at least four. The value reached by the GCML 82 counter during the droplet time preceding the first droplet time is equal to thirty-one. The value reached by the GCMH counter 83 during the same time interval is 32m, where m represents the number of times the counter 82 has counted thirty-two droplet times after the counter 83 has been reset.

The value of the DCM counter 86 is equal to the sum of the values of the counters 82 and 83 during the droplet time preceding the first droplet time, ie 32m + 31. This is shown in Figure 4, on which the signal GCM = DCM is at high level during the droplet time which precedes the first droplet time.

During the first droplet time shown in Figure 4, no change in the value of the counter 82 or 83 occurs. This is due to the fact that the counter 82 cannot pass from the value thirty-one to zero before the passage to the high level of the signal GD generated by the flip-flop 55 'during the passage to the high level of one of the signals d 'T2 clock. The value of counter 83 can only be changed when that of counter 82 goes from thirty-one to zero.

During the first droplet time shown in Figure 4, the value of the DCM 86 counter increases by one unit and becomes equal to 32m + 32, while the value of the RLM 65 counter becomes equal to x when the signal appears. T5 clock. At the start of the second droplet time signaled by the appearance of the clock signal TO, the SYNC signal goes high because the signal GCM = DCM is low and the value of the counter RLM 65 is greater than three since x is at least four.

During the second droplet time, the value of the DCM counter 86 cannot increase since the SYNC signal is at the high level. Therefore, during this second droplet time, none of the counters 82, 83 and 86 can count. Furthermore, the value of the counter RLM 65 does not decrease due to the fact that the signal SYNC has gone high when the clock signal TO appears indicating the start of the second droplet time.

In Figure 4, it is assumed that network 15 (Figure 1) generates a high level GP signal during the second droplet time and that this occurred before the appearance of the clock signal T7. The signal GD therefore goes high at the clock instant T7 during the second droplet time.

Therefore, during the third drop time, the value of the counter GCML 82 goes from thirty-one to zero when the clock signal T2 appears because the signal GD supplied by the flip-flop 55 'is at high level. This also has the effect of increasing the value of the GCMH 83 counter by one since the counter 82 has counted thirty-two times. It is understood that the value of the counter 83 increased during the passage to the low level of the clock signal Tl in accordance with the logic equation (22) and the second part of the logic equation (23) however that the value of the counter 82 has changed when switching to the high level of the clock signal T2.

However, the SYNC signal being always at the high level when the T2 clock signal appears during the third droplet time, the DCM counter 86 continues to not count. The value of the counter 86 therefore remains as it was during the second droplet time.

Consequently, the signal GCM = DCM again goes high when the clock signal T2 appears during the third droplet time. Therefore, the SYNC signal supplied by flip-flop 77 goes low when the clock signal T7 appears during this third droplet time. The signal GD emanating from the flip-flop 55 ′ went to the low level when the clock signal T5 goes to the high level.

As a result, since it is the SYNC signal and not the SYNC signal which is again at the high level, the value of the DCM counter 86 can again increase by one unit during the fourth droplet time shown in FIG. 4. Since the value of the RLM 65 counter changes when the clock signal goes high T5, its value remains the same during the second and third droplet times because the SYNC signal is always at the high level during the time interval during which the clock signal T5 is at the high level.

The value of the counter RLM 65 therefore does not change until the clock signal T5 goes high during the fourth droplet time. During this latter time, the value of each of the counters 82 and 86 increases by one.

The DCM counter 86 which comprises the point counter 79 is not set to zero until the appearance of the clock signal T1, the signal EOC being at the high level. The DCS counter 87 which also comprises the counter 79 is set to zero when the clock signal T5 appears during the same drop time, which is the last drop time of the preceding character.

The zero value of the GCML 82 counter is transferred to the GCSL 84 counter at the time when the clock signal T5 goes low. Likewise, the zero value of the GCMH counter 83 is transferred to the GCSH counter 85 when the clock signal T5 which forms part of the last droplet time relating to the preceding character goes low.

The droplets 23 are counted by the counters 79 and 78 as they are generated. However, the counter 78 stops after having counted thirty-one droplets and does not start counting again until the passage to the high level of another signal GD generated by the flip-flop 55 '.

The value of the RLM counter 65 that the track length counter 62 includes is transferred to the RLS counter 66 when the clock signal Tl appears during the first droplet time of the character to be printed. The RLS 66 counter causes a declining count of the RLM 65 counter when the clock signal T5 appears during the first drop time relating to the character to be printed.

When the RLM counter 65 reaches the value zero when one of the clock signals T5 appears, the ten bits contained in the register 64 and representing a voltage are transferred when the clock signals T0 appear , Tl, T2 and T3 during the next droplet time since the signal RLM = 0 goes high during the clock signal T5. Thus, when the signal RLM = 0 goes high, the transfer of these ten bits from the register 64 to the gate 115 causes the application to the charging electrode 24 of the desired voltage which makes it possible to impart to the droplet 23 the required charge. This causes a vertical deflection of the droplet 23 used for printing purposes, so that it strikes the sheet of paper or other support 14 (see Figure 1) at the predetermined location required, this deviation being defined relatively to the path of the droplets which are not used for printing purposes and which are intercepted by the gutter. Furthermore, it will be noted that the value of the counter 65 cannot go from zero to another value without an external signal being applied.

As previously mentioned, one of the droplets 23 may not be printed each time the track length counter 62 is set to 63. Consequently, when one of the droplets 23 does not should not be printed after counting down from counter 62 to zero, the voltage register 64 is at value V = 2. This value is too low for the droplet 23 to avoid being intercepted by the gutter 27.

At the expiration of the clock signal Tl, once the. RLM 65 counter subject to declining counting has reached the value zero, the RLs 66 counter is set to zero. This clock signal T1 is at the high level during the time interval during which the content of the register of voltages 64 is transferred to the charging electrode 24.

When the RLS 66 counter is at zero, the RLS = 0 signal is high. This signal is used to cause an increase of one unit, from the PCS 54 counter, of the PCM counter 53 that the pointer 52 includes. Therefore, when the charging electrode 24 receives a voltage corresponding to the output of the register 64 , the next upper line of the FROS memory 51 is accessed.

Therefore, when the clock signal T5 relating to the cycle during which the charge electrode 24 receives a voltage appears, the register 64 and the track length counter 62 both receive new information from the memory. FROS 51.

The seven most significant bits of the ten bits transmitted to the converter 112 and representing the voltage intended for the charging electrode 24 are applied to the JTF register 125, while the three most significant bits of the ten bits are transferred to the SOIM register 127. This occurs during the presence of the clock signal T2.

The contents of register 125 and that of register 128 are used to access memory 116. However, the data coming from register 128 results from the previous voltage signal applied to converter 112 via gate 115. This signal could come from from register 121 instead of register 64 unless two of the droplets 23 consecutively strike the print medium.

In either case, the memory 116 provides, upon the appearance of the signal T4, an eight-bit output to the register 121. This occurs immediately after the voltage has ceased to be applied to it. charging electrode 24 since the application of this voltage is interrupted when the clock signal T3 goes low. Consequently, eight bits representing the voltage intended for compensating for the charge induced by the last two droplets 23 can be applied to the DAC converter 112 if the latter must not receive the ten bits emanating from register 64.

The FOI register 125 receives only the five most significant bits of the eight bit word emanating from the register 121 since there are no ten bits available. Thus, these last two bits (the two most significant bits coming from the register 64) appear in the form of zeros in the converter 112 and in the FOI register 125.

Since no information relating to the voltage is required from the FROS memory 51 in the case of the droplets 23 which are not used for printing purposes and which are therefore directed towards the gutter 27 (FIG. 1) , Approximately 20% of the bit configurations of register 64 representing the values of the lowest voltages which are applied to the electrode 24, are not used. One of the bit configurations constituting this percentage could therefore be used to control the instant of the passage to the high level of the signal EOC supplied by the flip-flop 55.

Therefore, when the printing of the character must end, the value of register 64 is equal to one, so that V = ₁ . When the register 64 reaches this value and the RLM counter 65 which the track length counter 62 includes reaches the value zero, the clock signal T7 going high, the EOC signal obtained on pin 2 of the inverter 124 (Figure 9) of flip-flop 55 goes high. This result, which is shown in Figure 3, occurs during the final drop times, including the last drop time related to the previous printed character.

The operation of the network counter 78 in FIG. 2 could possibly depend on the effective speed at which the carriage 12 in FIG. 1 is moving instead of to be linked to that of the 19 'oscillator. In such a case, the positioning of the droplets 23 on the print medium could be synchronized with the interpolated position of the carriage 12 each time a series of four droplets 23 is not intended for printing, instead of waiting the appearance of the first series of four droplets immediately after the generation of a pulse by the network 15. This would make it possible to obtain a more uniform readjustment of the horizontal position and to bring the points of impact of the droplets 23 closer to their positions ideal, which would result in a better quality impression. This modification is however not essential to obtain satisfactory operation of the present invention.

The distance between the lines of the network 15 from each other being about 0.0106 cm, a droplet 23 is generated each time the carriage 12 moves a distance of about 0.0003302 cm. This figure is obtained by dividing the distance of 0.0106 cm by 32 droplets generated while the carriage 12 crosses the distance between two adjacent lines of the network 15. Since each of the droplets 23 has a diameter varying from 0.0508 cm to 0.000635 cm in order to produce a dot or inkblot with a diameter of approximately 0.014986 cm when it strikes the print medium 14, a single droplet 23 must strike the medium 14 at a location any vertical between two adjacent lines of the network 15. Each of these lines has a width corresponding approximately to the diameter obtained when two or three droplets 23 strike the print medium 14. Any character can therefore be produced during part of the movement carriage 12 in a given direction along the horizontal axis or in the opposite direction.

As previously mentioned, there are 7,680 droplet times in total per linear inch (i.e. 3023.622 droplet time per linear centimeter) of movement of the carriage 12. In the case of a printing carried out in steps of 12, there is, for the purposes of printing each character, a total of 640 times of droplet. In the case of a 10-step printing, there would be 768 droplet times per character.

There is shown in Figure 28 a character "W" printed in steps of 12. A total of 640 droplet times was therefore available to form the dots 35 on the printing medium 14, these dots being obtained during the impact of the droplets 23 on this support.

There is shown in Figure 29 an enlargement of the part of the character "W" which, in Figure 28, is inside a dotted rectangle, the first droplet time (not shown) starting at the left edge of the region in which the character is to be printed. Each of the points 35, which is formed during the part of the droplet times indicated in FIG. 29, has in its center a reference number corresponding to the droplet time (see FIGS. 28 and 29).

The inclination of the vertical lines in Figure 29 compensates for the movement of the carriage 12 from left to right and allows the droplets 23 generated at different droplet times to strike the print medium 14 at the same horizontal distance from a margin, the vertical lines can therefore be easily formed. This inclination is obtained by slightly moving the deflection plates 25 and 26 counterclockwise with respect to the axis of the ink jet 21 (Figure 1) when the plates 25 and 26 are observed from the position that occupies nozzle 22.

As shown in Figure 29, there are a number of positions in which the RLM counter 65 in the track length counter 62 has a value greater than three, so that synchronization can occur. For example, nine droplets 23 are unused between the drop times 213 and 223, so that synchronization could start at the drop times 214.

It will be noted that each modification of a unit of the binary value of the voltage register 64 corresponds to a modification of the vertical positioning of the droplet 23 of approximately 0.50508 cm, while the droplet time corresponds to a horizontal spacing between droplets 23 of about 0.0003302 cm. In the present context, the term "granular position" refers to each of the 7680 droplet times where the droplets 23 are generated per linear inch (i.e. 3023.622 droplet times per linear centimeter) of movement of the carriage 12 and to each of the 1024 positions defined by the 1024 voltages likely to be stored in the voltage register 64.

Although the present invention envisages the printing of characters only when the carriage 12 moves horizontally from left to right, this is not essential and the printing of characters could also take place during the horizontal displacement of the right carriage to the left.

Although the controller of the present invention uses a sixteen-bit word, it is understood that the word could have more bits. In the latter case, the track length counter 62 could count up to a value greater than 63.

If sufficient bits were available, counter 62 could use a sufficient number of these bits to count the total number of droplet times required to print one of the characters. In this case, the voltage signal supplied by the register 64 would always cause the application of a charge to one of the droplets 23 for the purposes of printing when the counter 62 reaches the value zero, at. the exception of the last time of droplet relating to the characters.

In the present context, the term "character" does not mean only a letter or a number or a particular zone. For example, this term could refer to configurations of any type.

One of the advantages of the present invention is that it makes it possible to obtain a better quality printing. Another advantage of the invention is that it makes it possible to avoid the discontinuous appearance of the printed characters. Another advantage of the invention is that it eliminates the need to print the droplets in an ascending sequence in a monotonous manner. Another advantage of the invention lies in the fact that it does not require any type of printing matrix, and that it is independent of the yield.

Although the essential characteristics of the invention applied to a preferred embodiment of the invention have been described in the foregoing and represented in the drawings, it is obvious that a person skilled in the art can provide all of them. modifications of form or detail which he judges useful, without departing from the scope of said invention.

Claims (8)

1.- Ink-jet printer, of the type comprising a device generating a series of uniformly spaced droplets, a recording surface, means generating a relative movement between the droplet generator and the recording surface in a first direction and means generating a relative movement between the droplet generator and the recording surface in a second direction practically perpendicular to the first direction, characterized in that it comprises: means for printing each droplet at any droplet position of the recording surface in the second direction and in the first direction depending on the position of the previously printed droplet or a margin. 2.- ink projection printer according to claim 1, characterized in that it comprises: means making it possible to selectively charge each of the droplets until it has a predetermined charge, means making it possible to deflect each of the droplets in the second direction as a function of the value of the charge which it carries, and droplet positioning means comprising means for storing information relating to each of the characters to be printed, this information comprising the amplitude of the voltage applied to the charging means for each of the printed droplets forming part of the character as well as the space in the first direction between each droplet and the printed droplet required demment or a margin. 3.- ink projection printer according to claim 1 or 2, characterized in that it comprises means for applying to the charging means, for each of the droplets to be printed, a voltage in accordance with the information contained in the means d storage in order to ensure that each of the droplets has the charge value necessary for them to be deflected in the second direction to the position chosen on the recording surface. 4.- ink jet printer according to one of claims 1 to 3, characterized in that it comprises: means for synchronizing the relative movement between the droplet generator and the recording surface in the first direction with respect to the spacing between one of the droplets to be printed and the previously printed droplet in the first direction at intervals of times chosen according to spacings chosen between adjacent printed droplets. 5.- ink jet printer according to one of claims 1 to 4, characterized in that it comprises: means for compensating for the induction generated between adjacent droplets by selectively applying a voltage to the charging means when a droplet is not to be used for printing and is located at a predetermined distance from the last printed droplet. 6.- ink projection printer according to claim 5, characterized in that said means of compensating induction training include: means sensitive to the voltage applied to the charging means for each of the droplets chosen from a number of previous droplets, means for storing information relating to the different voltages, voltage-sensitive means generating an address in the storage means in order to select therein the information allowing the application to the charging means of a voltage when a droplet not intended to be used for printing purposes found at a predetermined distance from the last printed droplet. 7.- ink projection printer according to claim 5, characterized in that said induction compensation means comprise means for determining the value of the voltage selectively applied for the droplets not used for the purposes of printing in accordance with the voltage applied to the charging means for each of the droplets of a selected number of previous droplets when the droplet not used for printing is at a predetermined distance from the last printed droplet. 8.- ink projection printer according to claim 5, characterized in that it comprises: means for controlling the time during which a voltage is applied to the charging means.

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