DE69838849D1 - Mehrchipmodulstruktur und seine herstellung - Google Patents

Mehrchipmodulstruktur und seine herstellung

Info

Publication number
DE69838849D1
DE69838849D1 DE69838849T DE69838849T DE69838849D1 DE 69838849 D1 DE69838849 D1 DE 69838849D1 DE 69838849 T DE69838849 T DE 69838849T DE 69838849 T DE69838849 T DE 69838849T DE 69838849 D1 DE69838849 D1 DE 69838849D1
Authority
DE
Germany
Prior art keywords
manufacture
modular structure
multiple modular
modular
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE69838849T
Other languages
English (en)
Other versions
DE69838849T2 (de
Inventor
Kenji Sekine
Hiroji Yamada
Matsuo Yamasaki
Osamu Kagaya
Kiichi Yamashita
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from JP25958997A external-priority patent/JP3840761B2/ja
Priority claimed from JP6972798A external-priority patent/JP3815033B2/ja
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Publication of DE69838849D1 publication Critical patent/DE69838849D1/de
Application granted granted Critical
Publication of DE69838849T2 publication Critical patent/DE69838849T2/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

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    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/50Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00
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    • H01L25/00Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
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    • H01L23/538Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H01L23/5389Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates the chips being integrally enclosed by the interconnect and support structures
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    • H01L24/23Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
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DE69838849T 1997-08-19 1998-08-19 Mehrchip-Modulstruktur und deren Herstellung Expired - Lifetime DE69838849T2 (de)

Applications Claiming Priority (7)

Application Number Priority Date Filing Date Title
JP22222997 1997-08-19
JP22222997 1997-08-19
JP25958997A JP3840761B2 (ja) 1997-09-25 1997-09-25 マルチチップモジュールおよびその製造方法
JP25958997 1997-09-25
JP6972798 1998-03-19
JP6972798A JP3815033B2 (ja) 1997-08-19 1998-03-19 マルチチップモジュール用ベース基板の作製方法
PCT/JP1998/003668 WO1999009595A1 (en) 1997-08-19 1998-08-19 Multichip module structure and method for manufacturing the same

Publications (2)

Publication Number Publication Date
DE69838849D1 true DE69838849D1 (de) 2008-01-24
DE69838849T2 DE69838849T2 (de) 2008-12-11

Family

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Family Applications (1)

Application Number Title Priority Date Filing Date
DE69838849T Expired - Lifetime DE69838849T2 (de) 1997-08-19 1998-08-19 Mehrchip-Modulstruktur und deren Herstellung

Country Status (6)

Country Link
US (1) US6495914B1 (de)
EP (1) EP1030369B1 (de)
KR (1) KR100543836B1 (de)
CN (1) CN1167131C (de)
DE (1) DE69838849T2 (de)
WO (1) WO1999009595A1 (de)

Families Citing this family (166)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6826827B1 (en) * 1994-12-29 2004-12-07 Tessera, Inc. Forming conductive posts by selective removal of conductive material
EP1154474A4 (de) * 1999-08-23 2008-07-16 Rohm Co Ltd Halbleiter-bauteil und verfahren zur herstellung hierfür
EP1195810B1 (de) * 2000-03-15 2011-05-11 Sumitomo Electric Industries, Ltd. Herstellungsmethode für ein aluminium-siliziumkarbid-halbleitersubstrat
US6400015B1 (en) * 2000-03-31 2002-06-04 Intel Corporation Method of creating shielded structures to protect semiconductor devices
KR100755832B1 (ko) * 2001-10-18 2007-09-07 엘지전자 주식회사 모듈 패키지 및 모듈 패키징 방법
US6673698B1 (en) 2002-01-19 2004-01-06 Megic Corporation Thin film semiconductor package utilizing a glass substrate with composite polymer/metal interconnect layers
TW503496B (en) 2001-12-31 2002-09-21 Megic Corp Chip packaging structure and manufacturing process of the same
TW517361B (en) * 2001-12-31 2003-01-11 Megic Corp Chip package structure and its manufacture process
TW544882B (en) 2001-12-31 2003-08-01 Megic Corp Chip package structure and process thereof
TW584950B (en) * 2001-12-31 2004-04-21 Megic Corp Chip packaging structure and process thereof
DE10209922A1 (de) 2002-03-07 2003-10-02 Infineon Technologies Ag Elektronisches Modul, Nutzen mit zu vereinzelnden elektronischen Modulen und Verfahren zu deren Herstellung
JP3923368B2 (ja) * 2002-05-22 2007-05-30 シャープ株式会社 半導体素子の製造方法
EP1369931A1 (de) * 2002-06-03 2003-12-10 Hitachi, Ltd. Solarzelle und ihr Herstellungsverfahren sowie Metallplatte dafür
JP3938742B2 (ja) * 2002-11-18 2007-06-27 Necエレクトロニクス株式会社 電子部品装置及びその製造方法
TWI246761B (en) * 2003-05-14 2006-01-01 Siliconware Precision Industries Co Ltd Semiconductor package with build-up layers formed on chip and fabrication method of the semiconductor package
US8641913B2 (en) * 2003-10-06 2014-02-04 Tessera, Inc. Fine pitch microcontacts and method for forming thereof
US7462936B2 (en) 2003-10-06 2008-12-09 Tessera, Inc. Formation of circuitry with modification of feature height
US7495179B2 (en) * 2003-10-06 2009-02-24 Tessera, Inc. Components with posts and pads
US20050168231A1 (en) * 2003-12-24 2005-08-04 Young-Gon Kim Methods and structures for electronic probing arrays
US7709968B2 (en) * 2003-12-30 2010-05-04 Tessera, Inc. Micro pin grid array with pin motion isolation
US8207604B2 (en) * 2003-12-30 2012-06-26 Tessera, Inc. Microelectronic package comprising offset conductive posts on compliant layer
US7176043B2 (en) * 2003-12-30 2007-02-13 Tessera, Inc. Microelectronic packages and methods therefor
US7453157B2 (en) 2004-06-25 2008-11-18 Tessera, Inc. Microelectronic packages and methods therefor
US7076870B2 (en) * 2004-08-16 2006-07-18 Pericom Semiconductor Corp. Manufacturing process for a surface-mount metal-cavity package for an oscillator crystal blank
KR101313391B1 (ko) 2004-11-03 2013-10-01 테세라, 인코포레이티드 적층형 패키징
US7939934B2 (en) * 2005-03-16 2011-05-10 Tessera, Inc. Microelectronic packages and methods therefor
US7230333B2 (en) * 2005-04-21 2007-06-12 International Rectifier Corporation Semiconductor package
US7514769B1 (en) * 2005-08-13 2009-04-07 National Semiconductor Corporation Micro surface mount die package and method
US7687925B2 (en) 2005-09-07 2010-03-30 Infineon Technologies Ag Alignment marks for polarized light lithography and method for use thereof
US8058101B2 (en) * 2005-12-23 2011-11-15 Tessera, Inc. Microelectronic packages and methods therefor
US8067267B2 (en) * 2005-12-23 2011-11-29 Tessera, Inc. Microelectronic assemblies having very fine pitch stacking
DE102006008937B4 (de) * 2006-02-27 2019-02-28 Infineon Technologies Ag Chipkartenmodul
US7569422B2 (en) * 2006-08-11 2009-08-04 Megica Corporation Chip package and method for fabricating the same
US7510401B2 (en) * 2006-10-12 2009-03-31 Tessera, Inc. Microelectronic component with foam-metal posts
US7719121B2 (en) * 2006-10-17 2010-05-18 Tessera, Inc. Microelectronic packages and methods therefor
US20080150101A1 (en) * 2006-12-20 2008-06-26 Tessera, Inc. Microelectronic packages having improved input/output connections and methods therefor
US7893545B2 (en) * 2007-07-18 2011-02-22 Infineon Technologies Ag Semiconductor device
EP2206145A4 (de) 2007-09-28 2012-03-28 Tessera Inc Flip-chip-verbindung mit doppelten pfosten
JP5271562B2 (ja) * 2008-02-15 2013-08-21 本田技研工業株式会社 半導体装置および半導体装置の製造方法
JP5271561B2 (ja) * 2008-02-15 2013-08-21 本田技研工業株式会社 半導体装置および半導体装置の製造方法
JP4484934B2 (ja) * 2008-02-26 2010-06-16 富士通メディアデバイス株式会社 電子部品及びその製造方法
US20110163348A1 (en) * 2008-03-25 2011-07-07 Bridge Semiconductor Corporation Semiconductor chip assembly with bump/base heat spreader and inverted cavity in bump
US9018667B2 (en) * 2008-03-25 2015-04-28 Bridge Semiconductor Corporation Semiconductor chip assembly with post/base heat spreader and dual adhesives
US8067784B2 (en) * 2008-03-25 2011-11-29 Bridge Semiconductor Corporation Semiconductor chip assembly with post/base heat spreader and substrate
US20100072511A1 (en) * 2008-03-25 2010-03-25 Lin Charles W C Semiconductor chip assembly with copper/aluminum post/base heat spreader
US20100052005A1 (en) * 2008-03-25 2010-03-04 Lin Charles W C Semiconductor chip assembly with post/base heat spreader and conductive trace
US20110156090A1 (en) * 2008-03-25 2011-06-30 Lin Charles W C Semiconductor chip assembly with post/base/post heat spreader and asymmetric posts
US8129742B2 (en) * 2008-03-25 2012-03-06 Bridge Semiconductor Corporation Semiconductor chip assembly with post/base heat spreader and plated through-hole
US20090284932A1 (en) * 2008-03-25 2009-11-19 Bridge Semiconductor Corporation Thermally Enhanced Package with Embedded Metal Slug and Patterned Circuitry
US8288792B2 (en) * 2008-03-25 2012-10-16 Bridge Semiconductor Corporation Semiconductor chip assembly with post/base/post heat spreader
US8193556B2 (en) * 2008-03-25 2012-06-05 Bridge Semiconductor Corporation Semiconductor chip assembly with post/base heat spreader and cavity in post
US8354688B2 (en) 2008-03-25 2013-01-15 Bridge Semiconductor Corporation Semiconductor chip assembly with bump/base/ledge heat spreader, dual adhesives and cavity in bump
US8314438B2 (en) * 2008-03-25 2012-11-20 Bridge Semiconductor Corporation Semiconductor chip assembly with bump/base heat spreader and cavity in bump
US8148747B2 (en) * 2008-03-25 2012-04-03 Bridge Semiconductor Corporation Semiconductor chip assembly with post/base/cap heat spreader
US8310043B2 (en) * 2008-03-25 2012-11-13 Bridge Semiconductor Corporation Semiconductor chip assembly with post/base heat spreader with ESD protection layer
US8531024B2 (en) * 2008-03-25 2013-09-10 Bridge Semiconductor Corporation Semiconductor chip assembly with post/base heat spreader and multilevel conductive trace
US20110278638A1 (en) 2008-03-25 2011-11-17 Lin Charles W C Semiconductor chip assembly with post/dielectric/post heat spreader
US8415703B2 (en) * 2008-03-25 2013-04-09 Bridge Semiconductor Corporation Semiconductor chip assembly with post/base/flange heat spreader and cavity in flange
US8269336B2 (en) * 2008-03-25 2012-09-18 Bridge Semiconductor Corporation Semiconductor chip assembly with post/base heat spreader and signal post
US8378372B2 (en) * 2008-03-25 2013-02-19 Bridge Semiconductor Corporation Semiconductor chip assembly with post/base heat spreader and horizontal signal routing
US8324723B2 (en) * 2008-03-25 2012-12-04 Bridge Semiconductor Corporation Semiconductor chip assembly with bump/base heat spreader and dual-angle cavity in bump
US20100181594A1 (en) * 2008-03-25 2010-07-22 Lin Charles W C Semiconductor chip assembly with post/base heat spreader and cavity over post
US8203167B2 (en) * 2008-03-25 2012-06-19 Bridge Semiconductor Corporation Semiconductor chip assembly with post/base heat spreader and adhesive between base and terminal
US8212279B2 (en) * 2008-03-25 2012-07-03 Bridge Semiconductor Corporation Semiconductor chip assembly with post/base heat spreader, signal post and cavity
US8329510B2 (en) * 2008-03-25 2012-12-11 Bridge Semiconductor Corporation Method of making a semiconductor chip assembly with a post/base heat spreader with an ESD protection layer
US8525214B2 (en) 2008-03-25 2013-09-03 Bridge Semiconductor Corporation Semiconductor chip assembly with post/base heat spreader with thermal via
US7948076B2 (en) * 2008-03-25 2011-05-24 Bridge Semiconductor Corporation Semiconductor chip assembly with post/base heat spreader and vertical signal routing
US8232576B1 (en) 2008-03-25 2012-07-31 Bridge Semiconductor Corporation Semiconductor chip assembly with post/base heat spreader and ceramic block in post
US8207553B2 (en) * 2008-03-25 2012-06-26 Bridge Semiconductor Corporation Semiconductor chip assembly with base heat spreader and cavity in base
US8273603B2 (en) * 2008-04-04 2012-09-25 The Charles Stark Draper Laboratory, Inc. Interposers, electronic modules, and methods for forming the same
US8017451B2 (en) 2008-04-04 2011-09-13 The Charles Stark Draper Laboratory, Inc. Electronic modules and methods for forming the same
CN102017133B (zh) * 2008-05-09 2012-10-10 国立大学法人九州工业大学 芯片尺寸两面连接封装件及其制造方法
US8253241B2 (en) 2008-05-20 2012-08-28 Infineon Technologies Ag Electronic module
US20100044860A1 (en) * 2008-08-21 2010-02-25 Tessera Interconnect Materials, Inc. Microelectronic substrate or element having conductive pads and metal posts joined thereto using bond layer
WO2010041630A1 (ja) * 2008-10-10 2010-04-15 日本電気株式会社 半導体装置及びその製造方法
US8324653B1 (en) 2009-08-06 2012-12-04 Bridge Semiconductor Corporation Semiconductor chip assembly with ceramic/metal substrate
CN102009097B (zh) * 2009-09-04 2012-12-12 合谥螺丝五金股份有限公司 金属板材单面卡榫成型方法及具有金属板材单面卡榫的优盘
US8569894B2 (en) 2010-01-13 2013-10-29 Advanced Semiconductor Engineering, Inc. Semiconductor package with single sided substrate design and manufacturing methods thereof
US20110215450A1 (en) * 2010-03-05 2011-09-08 Chi Heejo Integrated circuit packaging system with encapsulation and method of manufacture thereof
US8241956B2 (en) * 2010-03-08 2012-08-14 Stats Chippac, Ltd. Semiconductor device and method of forming wafer level multi-row etched lead package
US8349658B2 (en) * 2010-05-26 2013-01-08 Stats Chippac, Ltd. Semiconductor device and method of forming conductive posts and heat sink over semiconductor die using leadframe
US9269691B2 (en) * 2010-05-26 2016-02-23 Stats Chippac, Ltd. Semiconductor device and method of making an embedded wafer level ball grid array (EWLB) package on package (POP) device with a slotted metal carrier interposer
US8653670B2 (en) * 2010-06-29 2014-02-18 General Electric Company Electrical interconnect for an integrated circuit package and method of making same
US9570376B2 (en) 2010-06-29 2017-02-14 General Electric Company Electrical interconnect for an integrated circuit package and method of making same
US8330272B2 (en) 2010-07-08 2012-12-11 Tessera, Inc. Microelectronic packages with dual or multiple-etched flip-chip connectors
US8482111B2 (en) 2010-07-19 2013-07-09 Tessera, Inc. Stackable molded microelectronic packages
US9159708B2 (en) 2010-07-19 2015-10-13 Tessera, Inc. Stackable molded microelectronic packages with area array unit connectors
US8580607B2 (en) 2010-07-27 2013-11-12 Tessera, Inc. Microelectronic packages with nanoparticle joining
US8076184B1 (en) * 2010-08-16 2011-12-13 Stats Chippac, Ltd. Semiconductor device and method of forming wafer-level multi-row etched leadframe with base leads and embedded semiconductor die
KR101075241B1 (ko) 2010-11-15 2011-11-01 테세라, 인코포레이티드 유전체 부재에 단자를 구비하는 마이크로전자 패키지
US8853558B2 (en) 2010-12-10 2014-10-07 Tessera, Inc. Interconnect structure
US20120146206A1 (en) 2010-12-13 2012-06-14 Tessera Research Llc Pin attachment
US9406658B2 (en) 2010-12-17 2016-08-02 Advanced Semiconductor Engineering, Inc. Embedded component device and manufacturing methods thereof
US9137903B2 (en) 2010-12-21 2015-09-15 Tessera, Inc. Semiconductor chip assembly and method for making same
US8487426B2 (en) * 2011-03-15 2013-07-16 Advanced Semiconductor Engineering, Inc. Semiconductor package with embedded die and manufacturing methods thereof
KR101128063B1 (ko) 2011-05-03 2012-04-23 테세라, 인코포레이티드 캡슐화 층의 표면에 와이어 본드를 구비하는 패키지 적층형 어셈블리
US8618659B2 (en) 2011-05-03 2013-12-31 Tessera, Inc. Package-on-package assembly with wire bonds to encapsulation surface
US20140090234A1 (en) * 2011-05-23 2014-04-03 University Of Massachusetts Apparatus and methods for multi-scale alignment and fastening
US8872318B2 (en) 2011-08-24 2014-10-28 Tessera, Inc. Through interposer wire bond using low CTE interposer with coarse slot apertures
US8836136B2 (en) 2011-10-17 2014-09-16 Invensas Corporation Package-on-package assembly with wire bond vias
US8959757B2 (en) * 2011-12-29 2015-02-24 Rf Micro Devices, Inc. Method of manufacturing an electronic module
US8946757B2 (en) 2012-02-17 2015-02-03 Invensas Corporation Heat spreading substrate with embedded interconnects
US9349706B2 (en) 2012-02-24 2016-05-24 Invensas Corporation Method for package-on-package assembly with wire bonds to encapsulation surface
US8372741B1 (en) 2012-02-24 2013-02-12 Invensas Corporation Method for package-on-package assembly with wire bonds to encapsulation surface
US8835228B2 (en) 2012-05-22 2014-09-16 Invensas Corporation Substrate-less stackable package with wire-bond interconnect
US9391008B2 (en) 2012-07-31 2016-07-12 Invensas Corporation Reconstituted wafer-level package DRAM
US9502390B2 (en) 2012-08-03 2016-11-22 Invensas Corporation BVA interposer
US8912670B2 (en) * 2012-09-28 2014-12-16 Intel Corporation Bumpless build-up layer package including an integrated heat spreader
US9136236B2 (en) 2012-09-28 2015-09-15 Intel Corporation Localized high density substrate routing
US8975738B2 (en) 2012-11-12 2015-03-10 Invensas Corporation Structure for microelectronic packaging with terminals on dielectric mass
US9190380B2 (en) 2012-12-06 2015-11-17 Intel Corporation High density substrate routing in BBUL package
US8878353B2 (en) 2012-12-20 2014-11-04 Invensas Corporation Structure for microelectronic packaging with bond elements to encapsulation surface
TWI540768B (zh) * 2012-12-21 2016-07-01 鴻海精密工業股份有限公司 發光晶片組合及其製造方法
US9136254B2 (en) 2013-02-01 2015-09-15 Invensas Corporation Microelectronic package having wire bond vias and stiffening layer
US9023691B2 (en) 2013-07-15 2015-05-05 Invensas Corporation Microelectronic assemblies with stack terminals coupled by connectors extending through encapsulation
US9034696B2 (en) 2013-07-15 2015-05-19 Invensas Corporation Microelectronic assemblies having reinforcing collars on connectors extending through encapsulation
US8883563B1 (en) 2013-07-15 2014-11-11 Invensas Corporation Fabrication of microelectronic assemblies having stack terminals coupled by connectors extending through encapsulation
US9167710B2 (en) 2013-08-07 2015-10-20 Invensas Corporation Embedded packaging with preformed vias
US9685365B2 (en) 2013-08-08 2017-06-20 Invensas Corporation Method of forming a wire bond having a free end
US20150076714A1 (en) 2013-09-16 2015-03-19 Invensas Corporation Microelectronic element with bond elements to encapsulation surface
US9349703B2 (en) 2013-09-25 2016-05-24 Intel Corporation Method for making high density substrate interconnect using inkjet printing
US9159690B2 (en) 2013-09-25 2015-10-13 Intel Corporation Tall solders for through-mold interconnect
US9087815B2 (en) 2013-11-12 2015-07-21 Invensas Corporation Off substrate kinking of bond wire
US9082753B2 (en) 2013-11-12 2015-07-14 Invensas Corporation Severing bond wire by kinking and twisting
US9379074B2 (en) 2013-11-22 2016-06-28 Invensas Corporation Die stacks with one or more bond via arrays of wire bond wires and with one or more arrays of bump interconnects
US9583456B2 (en) 2013-11-22 2017-02-28 Invensas Corporation Multiple bond via arrays of different wire heights on a same substrate
US9263394B2 (en) 2013-11-22 2016-02-16 Invensas Corporation Multiple bond via arrays of different wire heights on a same substrate
KR102004777B1 (ko) * 2013-12-27 2019-10-01 삼성전기주식회사 패키지 제조 방법 및 그를 이용한 패키지
US9583411B2 (en) 2014-01-17 2017-02-28 Invensas Corporation Fine pitch BVA using reconstituted wafer with area array accessible for testing
US9214454B2 (en) 2014-03-31 2015-12-15 Invensas Corporation Batch process fabrication of package-on-package microelectronic assemblies
US10381326B2 (en) 2014-05-28 2019-08-13 Invensas Corporation Structure and method for integrated circuits packaging with increased density
US9646917B2 (en) 2014-05-29 2017-05-09 Invensas Corporation Low CTE component with wire bond interconnects
US9412714B2 (en) 2014-05-30 2016-08-09 Invensas Corporation Wire bond support structure and microelectronic package including wire bonds therefrom
US9502270B2 (en) 2014-07-08 2016-11-22 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor device packages, packaging methods, and packaged semiconductor devices
US9431319B2 (en) * 2014-08-01 2016-08-30 Linear Technology Corporation Exposed, solderable heat spreader for integrated circuit packages
US9735084B2 (en) 2014-12-11 2017-08-15 Invensas Corporation Bond via array for thermal conductivity
US9888579B2 (en) 2015-03-05 2018-02-06 Invensas Corporation Pressing of wire bond wire tips to provide bent-over tips
WO2016148726A1 (en) * 2015-03-19 2016-09-22 Intel Corporation Radio die package with backside conductive plate
US9502372B1 (en) 2015-04-30 2016-11-22 Invensas Corporation Wafer-level packaging using wire bond wires in place of a redistribution layer
US9761554B2 (en) 2015-05-07 2017-09-12 Invensas Corporation Ball bonding metal wire bond wires to metal pads
US9847230B2 (en) * 2015-06-09 2017-12-19 The Charles Stark Draper Laboratory, Inc. Method and apparatus for using universal cavity wafer in wafer level packaging
US10886250B2 (en) 2015-07-10 2021-01-05 Invensas Corporation Structures and methods for low temperature bonding using nanoparticles
US9633971B2 (en) 2015-07-10 2017-04-25 Invensas Corporation Structures and methods for low temperature bonding using nanoparticles
US9543249B1 (en) * 2015-09-21 2017-01-10 Dyi-chung Hu Package substrate with lateral communication circuitry
US10490528B2 (en) 2015-10-12 2019-11-26 Invensas Corporation Embedded wire bond wires
US9490222B1 (en) 2015-10-12 2016-11-08 Invensas Corporation Wire bond wires for interference shielding
US10332854B2 (en) 2015-10-23 2019-06-25 Invensas Corporation Anchoring structure of fine pitch bva
US10181457B2 (en) 2015-10-26 2019-01-15 Invensas Corporation Microelectronic package for wafer-level chip scale packaging with fan-out
US9735131B2 (en) 2015-11-10 2017-08-15 Taiwan Semiconductor Manufacturing Company, Ltd. Multi-stack package-on-package structures
US9911718B2 (en) 2015-11-17 2018-03-06 Invensas Corporation ‘RDL-First’ packaged microelectronic device for a package-on-package device
US9659848B1 (en) 2015-11-18 2017-05-23 Invensas Corporation Stiffened wires for offset BVA
US9984992B2 (en) 2015-12-30 2018-05-29 Invensas Corporation Embedded wire bond wires for vertical integration with separate surface mount and wire bond mounting surfaces
EP3410476A4 (de) 2016-01-31 2019-09-11 Shindengen Electric Manufacturing Co., Ltd. Halbleitermodul
JP6254299B2 (ja) * 2016-01-31 2017-12-27 新電元工業株式会社 半導体モジュール
US10586757B2 (en) 2016-05-27 2020-03-10 Linear Technology Corporation Exposed solderable heat spreader for flipchip packages
US9935075B2 (en) 2016-07-29 2018-04-03 Invensas Corporation Wire bonding method and apparatus for electromagnetic interference shielding
US10299368B2 (en) 2016-12-21 2019-05-21 Invensas Corporation Surface integrated waveguides and circuit structures therefor
CN108269765B (zh) * 2016-12-30 2021-11-26 意法半导体有限公司 半导体传感器封装体
WO2018211683A1 (ja) * 2017-05-19 2018-11-22 新電元工業株式会社 電子モジュール、接続体の製造方法及び電子モジュールの製造方法
US10206286B2 (en) * 2017-06-26 2019-02-12 Infineon Technologies Austria Ag Embedding into printed circuit board with drilling
TWM555065U (zh) * 2017-09-05 2018-02-01 恆勁科技股份有限公司 電子封裝件及其封裝基板
US20200035614A1 (en) * 2018-07-30 2020-01-30 Powertech Technology Inc. Package structure and manufacturing method thereof
JP6775071B2 (ja) * 2018-10-05 2020-10-28 日本特殊陶業株式会社 配線基板
JP6936839B2 (ja) * 2018-10-05 2021-09-22 日本特殊陶業株式会社 配線基板
US11676955B2 (en) * 2020-06-10 2023-06-13 Micron Technology, Inc. Separation method and assembly for chip-on-wafer processing
CN112038322B (zh) * 2020-08-20 2022-02-22 武汉华星光电半导体显示技术有限公司 薄膜覆晶封装结构以及薄膜覆晶封装方法

Family Cites Families (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5177173A (en) * 1974-12-27 1976-07-03 Tokyo Shibaura Electric Co Handotaisochino tanshikozo
JPS5591844A (en) * 1978-12-28 1980-07-11 Fujitsu Ltd Electronic parts package
JPS61166050A (ja) * 1984-12-07 1986-07-26 Fujitsu Ltd Icパツケ−ジの捺印方法
JPH03155144A (ja) 1989-11-13 1991-07-03 Sharp Corp ベアー半導体icチップ実装方法
JPH0458539A (ja) * 1990-06-27 1992-02-25 Mitsubishi Electric Corp 混成集積回路装置
JPH0547856A (ja) 1991-08-19 1993-02-26 Fujitsu Ltd 半導体装置とその製造方法
JPH06164088A (ja) * 1991-10-31 1994-06-10 Sanyo Electric Co Ltd 混成集積回路装置
US5278446A (en) * 1992-07-06 1994-01-11 Motorola, Inc. Reduced stress plastic package
US6081028A (en) * 1994-03-29 2000-06-27 Sun Microsystems, Inc. Thermal management enhancements for cavity packages
JPH07326708A (ja) * 1994-06-01 1995-12-12 Toppan Printing Co Ltd マルチチップモジュール半導体装置
US5656550A (en) * 1994-08-24 1997-08-12 Fujitsu Limited Method of producing a semicondutor device having a lead portion with outer connecting terminal
US6184575B1 (en) * 1994-08-26 2001-02-06 National Semiconductor Corporation Ultra-thin composite package for integrated circuits
EP0735806B1 (de) * 1995-03-22 1997-09-10 Hitachi, Ltd. Kompaktleiterplatte
US6159770A (en) * 1995-11-08 2000-12-12 Fujitsu Limited Method and apparatus for fabricating semiconductor device

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KR100543836B1 (ko) 2006-01-23
DE69838849T2 (de) 2008-12-11
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US6495914B1 (en) 2002-12-17
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