DE69834702D1 - Packung für eine Halbleiteranordnung, Verfahren zu ihrer Herstellung und Leiterplatte dafür - Google Patents

Packung für eine Halbleiteranordnung, Verfahren zu ihrer Herstellung und Leiterplatte dafür

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Publication number
DE69834702D1
DE69834702D1 DE69834702T DE69834702T DE69834702D1 DE 69834702 D1 DE69834702 D1 DE 69834702D1 DE 69834702 T DE69834702 T DE 69834702T DE 69834702 T DE69834702 T DE 69834702T DE 69834702 D1 DE69834702 D1 DE 69834702D1
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Germany
Prior art keywords
package
production
circuit board
semiconductor device
printed circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE69834702T
Other languages
English (en)
Other versions
DE69834702T2 (de
Inventor
Kazuo Tamaki
Yasuyuki Saza
Yoshihisa Dotta
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sharp Corp
Original Assignee
Sharp Corp
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Publication date
Application filed by Sharp Corp filed Critical Sharp Corp
Publication of DE69834702D1 publication Critical patent/DE69834702D1/de
Application granted granted Critical
Publication of DE69834702T2 publication Critical patent/DE69834702T2/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

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    • H01L23/31Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3121Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
    • H01L23/3128Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation the substrate having spherical bumps for external connection
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    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/50Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/563Encapsulation of active face of flip-chip device, e.g. underfilling or underencapsulation of flip-chip, encapsulation preform on chip or mounting substrate
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EP0915505B1 (de) 2006-05-31
DE69834702T2 (de) 2007-05-03

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