DE69826418D1 - Anordnung zum Abtasten mehrerer Instruktionen in einer Prozessorpipeline - Google Patents

Anordnung zum Abtasten mehrerer Instruktionen in einer Prozessorpipeline

Info

Publication number
DE69826418D1
DE69826418D1 DE69826418T DE69826418T DE69826418D1 DE 69826418 D1 DE69826418 D1 DE 69826418D1 DE 69826418 T DE69826418 T DE 69826418T DE 69826418 T DE69826418 T DE 69826418T DE 69826418 D1 DE69826418 D1 DE 69826418D1
Authority
DE
Germany
Prior art keywords
pipeline
instructions
arrangement
processor pipeline
multiple instructions
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE69826418T
Other languages
English (en)
Other versions
DE69826418T2 (de
Inventor
George Z Chrysos
Jeffrey A Dean
James E Hicks
Daniel L Leibholz
Edward J Mclellan
Carl A Waldspurger
William E Weihl
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
COMPAG COMP CORP
Compaq Computer Corp
Original Assignee
COMPAG COMP CORP
Compaq Computer Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by COMPAG COMP CORP, Compaq Computer Corp filed Critical COMPAG COMP CORP
Publication of DE69826418D1 publication Critical patent/DE69826418D1/de
Application granted granted Critical
Publication of DE69826418T2 publication Critical patent/DE69826418T2/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00Error detection; Error correction; Monitoring
    • G06F11/30Monitoring
    • G06F11/34Recording or statistical evaluation of computer activity, e.g. of down time, of input/output operation ; Recording or statistical evaluation of user activity, e.g. usability assessment
    • G06F11/3466Performance evaluation by tracing or monitoring
    • G06F11/348Circuit details, i.e. tracer hardware
    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00Error detection; Error correction; Monitoring
    • G06F11/30Monitoring
    • G06F11/34Recording or statistical evaluation of computer activity, e.g. of down time, of input/output operation ; Recording or statistical evaluation of user activity, e.g. usability assessment
    • G06F11/3466Performance evaluation by tracing or monitoring
DE69826418T 1997-11-26 1998-11-25 Anordnung zum Abtasten mehrerer Instruktionen in einer Prozessorpipeline Expired - Lifetime DE69826418T2 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US980168 1997-11-26
US08/980,168 US6163840A (en) 1997-11-26 1997-11-26 Method and apparatus for sampling multiple potentially concurrent instructions in a processor pipeline

Publications (2)

Publication Number Publication Date
DE69826418D1 true DE69826418D1 (de) 2004-10-28
DE69826418T2 DE69826418T2 (de) 2005-03-03

Family

ID=25527392

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69826418T Expired - Lifetime DE69826418T2 (de) 1997-11-26 1998-11-25 Anordnung zum Abtasten mehrerer Instruktionen in einer Prozessorpipeline

Country Status (4)

Country Link
US (1) US6163840A (de)
EP (1) EP0919924B1 (de)
JP (1) JP4467094B2 (de)
DE (1) DE69826418T2 (de)

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Also Published As

Publication number Publication date
EP0919924A3 (de) 2000-02-23
US6163840A (en) 2000-12-19
EP0919924B1 (de) 2004-09-22
JPH11272520A (ja) 1999-10-08
EP0919924A2 (de) 1999-06-02
DE69826418T2 (de) 2005-03-03
JP4467094B2 (ja) 2010-05-26

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