DE69805628T2 - Synchroner taktgenerator mit verzögerungsregelschleife - Google Patents

Synchroner taktgenerator mit verzögerungsregelschleife

Info

Publication number
DE69805628T2
DE69805628T2 DE69805628T DE69805628T DE69805628T2 DE 69805628 T2 DE69805628 T2 DE 69805628T2 DE 69805628 T DE69805628 T DE 69805628T DE 69805628 T DE69805628 T DE 69805628T DE 69805628 T2 DE69805628 T2 DE 69805628T2
Authority
DE
Germany
Prior art keywords
delay
circuit
locked loop
clock signal
latch
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE69805628T
Other languages
English (en)
Other versions
DE69805628D1 (de
Inventor
Ronnie M Harrison
Brent Keeth
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Micron Technology Inc
Original Assignee
Micron Technology Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Micron Technology Inc filed Critical Micron Technology Inc
Publication of DE69805628D1 publication Critical patent/DE69805628D1/de
Application granted granted Critical
Publication of DE69805628T2 publication Critical patent/DE69805628T2/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03LAUTOMATIC CONTROL, STARTING, SYNCHRONISATION, OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00Automatic control of frequency or phase; Synchronisation
    • H03L7/06Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08Details of the phase-locked loop
    • H03L7/0805Details of the phase-locked loop the loop being adapted to provide an additional control signal for use outside the loop
    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03LAUTOMATIC CONTROL, STARTING, SYNCHRONISATION, OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00Automatic control of frequency or phase; Synchronisation
    • H03L7/06Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08Details of the phase-locked loop
    • H03L7/081Details of the phase-locked loop provided with an additional controlled phase shifter
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C7/00Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1051Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C7/00Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1051Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
    • G11C7/106Data output latches
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C7/00Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1072Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers for memories with random access ports synchronised on clock signal pulse trains, e.g. synchronous memories, self timed memories
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C7/00Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1078Data input circuits, e.g. write amplifiers, data input buffers, data input registers, data input level conversion circuits
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C7/00Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/22Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management 
    • G11C7/222Clock generating, synchronizing or distributing circuits within memory device
    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03LAUTOMATIC CONTROL, STARTING, SYNCHRONISATION, OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00Automatic control of frequency or phase; Synchronisation
    • H03L7/06Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08Details of the phase-locked loop
    • H03L7/081Details of the phase-locked loop provided with an additional controlled phase shifter
    • H03L7/0812Details of the phase-locked loop provided with an additional controlled phase shifter and where no voltage or current controlled oscillator is used
    • H03L7/0816Details of the phase-locked loop provided with an additional controlled phase shifter and where no voltage or current controlled oscillator is used the controlled phase shifter and the frequency- or phase-detection arrangement being connected to a common input
DE69805628T 1997-02-11 1998-02-11 Synchroner taktgenerator mit verzögerungsregelschleife Expired - Lifetime DE69805628T2 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US08/799,661 US5920518A (en) 1997-02-11 1997-02-11 Synchronous clock generator including delay-locked loop
PCT/US1998/002234 WO1998035446A1 (en) 1997-02-11 1998-02-11 Synchronous clock generator including delay-locked loop

Publications (2)

Publication Number Publication Date
DE69805628D1 DE69805628D1 (de) 2002-07-04
DE69805628T2 true DE69805628T2 (de) 2003-01-30

Family

ID=25176454

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69805628T Expired - Lifetime DE69805628T2 (de) 1997-02-11 1998-02-11 Synchroner taktgenerator mit verzögerungsregelschleife

Country Status (8)

Country Link
US (1) US5920518A (de)
EP (1) EP1002369B1 (de)
JP (1) JP4019126B2 (de)
KR (1) KR100518479B1 (de)
AT (1) ATE218255T1 (de)
AU (1) AU6146398A (de)
DE (1) DE69805628T2 (de)
WO (1) WO1998035446A1 (de)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE102006051292B4 (de) * 2005-10-26 2010-08-19 Samsung Electronics Co., Ltd. Takterzeugungsschaltung, Multiphasen-Takterzeuger, Speicherelement, Verfahren zum Erzeugen von Taktsignalen und Verfahren zum Verriegeln der Phase
US8004335B2 (en) 2008-02-11 2011-08-23 International Business Machines Corporation Phase interpolator system and associated methods

Families Citing this family (55)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5940608A (en) 1997-02-11 1999-08-17 Micron Technology, Inc. Method and apparatus for generating an internal clock signal that is synchronized to an external clock signal
US5946244A (en) 1997-03-05 1999-08-31 Micron Technology, Inc. Delay-locked loop with binary-coupled capacitor
US6173432B1 (en) 1997-06-20 2001-01-09 Micron Technology, Inc. Method and apparatus for generating a sequence of clock signals
US6487647B1 (en) * 1997-12-29 2002-11-26 Intel Corporation Adaptive memory interface timing generation
US6269451B1 (en) 1998-02-27 2001-07-31 Micron Technology, Inc. Method and apparatus for adjusting data timing by delaying clock signal
US6137325A (en) 1998-06-22 2000-10-24 Micron Technology, Inc. Device and methods in a delay locked loop for generating quadrature and other off-phase clocks with improved resolution
US6338127B1 (en) 1998-08-28 2002-01-08 Micron Technology, Inc. Method and apparatus for resynchronizing a plurality of clock signals used to latch respective digital signals, and memory device using same
US6279090B1 (en) 1998-09-03 2001-08-21 Micron Technology, Inc. Method and apparatus for resynchronizing a plurality of clock signals used in latching respective digital signals applied to a packetized memory device
US6349399B1 (en) 1998-09-03 2002-02-19 Micron Technology, Inc. Method and apparatus for generating expect data from a captured bit pattern, and memory device using same
US6580829B1 (en) * 1998-09-25 2003-06-17 Sarnoff Corporation Detecting and coding flash frames in video data
DE19845121C1 (de) * 1998-09-30 2000-03-30 Siemens Ag Integrierte Schaltung mit einstellbaren Verzögerungseinheiten für Taktsignale
US6430696B1 (en) 1998-11-30 2002-08-06 Micron Technology, Inc. Method and apparatus for high speed data capture utilizing bit-to-bit timing correction, and memory device using same
US6374360B1 (en) 1998-12-11 2002-04-16 Micron Technology, Inc. Method and apparatus for bit-to-bit timing correction of a high speed memory bus
US6470060B1 (en) 1999-03-01 2002-10-22 Micron Technology, Inc. Method and apparatus for generating a phase dependent control signal
US6388480B1 (en) 1999-08-30 2002-05-14 Micron Technology, Inc. Method and apparatus for reducing the lock time of DLL
US6643787B1 (en) 1999-10-19 2003-11-04 Rambus Inc. Bus system optimization
US6646953B1 (en) * 2000-07-06 2003-11-11 Rambus Inc. Single-clock, strobeless signaling system
US7051130B1 (en) 1999-10-19 2006-05-23 Rambus Inc. Integrated circuit device that stores a value representative of a drive strength setting
US6321282B1 (en) 1999-10-19 2001-11-20 Rambus Inc. Apparatus and method for topography dependent signaling
US6959062B1 (en) 2000-01-28 2005-10-25 Micron Technology, Inc. Variable delay line
CA2352729A1 (en) 2000-07-13 2002-01-13 Creoscitex Corporation Ltd. Blazed micro-mechanical light modulator and array thereof
KR100401491B1 (ko) * 2000-11-01 2003-10-11 주식회사 하이닉스반도체 데이터 출력 버퍼 제어 회로
US6889336B2 (en) 2001-01-05 2005-05-03 Micron Technology, Inc. Apparatus for improving output skew for synchronous integrate circuits has delay circuit for generating unique clock signal by applying programmable delay to delayed clock signal
US7079775B2 (en) 2001-02-05 2006-07-18 Finisar Corporation Integrated memory mapped controller circuit for fiber optics transceiver
WO2002095943A2 (en) * 2001-05-21 2002-11-28 Vasily Grigorievich Atyunin Programmable self-calibrating vernier and method
US6570813B2 (en) 2001-05-25 2003-05-27 Micron Technology, Inc. Synchronous mirror delay with reduced delay line taps
US6801989B2 (en) 2001-06-28 2004-10-05 Micron Technology, Inc. Method and system for adjusting the timing offset between a clock signal and respective digital signals transmitted along with that clock signal, and memory device and computer system using same
US6876239B2 (en) * 2001-07-11 2005-04-05 Micron Technology, Inc. Delay locked loop “ACTIVE command” reactor
US6838712B2 (en) * 2001-11-26 2005-01-04 Micron Technology, Inc. Per-bit set-up and hold time adjustment for double-data rate synchronous DRAM
US6678205B2 (en) 2001-12-26 2004-01-13 Micron Technology, Inc. Multi-mode synchronous memory device and method of operating and testing same
US6922091B2 (en) 2002-09-03 2005-07-26 Rambus Inc. Locked loop circuit with clock hold function
US7135903B2 (en) * 2002-09-03 2006-11-14 Rambus Inc. Phase jumping locked loop circuit
US6911853B2 (en) * 2002-03-22 2005-06-28 Rambus Inc. Locked loop with dual rail regulation
US6759881B2 (en) * 2002-03-22 2004-07-06 Rambus Inc. System with phase jumping locked loop circuit
US6952123B2 (en) 2002-03-22 2005-10-04 Rambus Inc. System with dual rail regulated locked loop
US6917228B2 (en) * 2002-06-06 2005-07-12 Micron Technology, Inc. Delay locked loop circuit with time delay quantifier and control
US6809990B2 (en) * 2002-06-21 2004-10-26 Micron Technology, Inc. Delay locked loop control circuit
US6680874B1 (en) 2002-08-29 2004-01-20 Micron Technology, Inc. Delay lock loop circuit useful in a synchronous system and associated methods
US7131021B2 (en) * 2002-12-10 2006-10-31 Faraday Technology Corp. Apparatus for delay calibration of a forward clock using three feedback clocks and a state transition table
KR100518226B1 (ko) * 2003-04-23 2005-10-04 주식회사 하이닉스반도체 Ddl 장치의 클락 분주기 및 그 클락 분주 방법
US6873398B2 (en) * 2003-05-21 2005-03-29 Esko-Graphics A/S Method and apparatus for multi-track imaging using single-mode beams and diffraction-limited optics
US7168027B2 (en) 2003-06-12 2007-01-23 Micron Technology, Inc. Dynamic synchronization of data capture on an optical or other high speed communications link
JP4923395B2 (ja) * 2004-08-30 2012-04-25 富士通株式会社 半導体回路、半導体回路特性監視方法、半導体回路試験方法、半導体回路試験装置及び半導体回路試験プログラム
CN101057442B (zh) 2004-09-14 2011-04-13 Nxp股份有限公司 延迟控制电路及方法
DE102004052268B4 (de) * 2004-10-27 2016-03-24 Polaris Innovations Ltd. Halbleiterspeichersystem und Verfahren zur Datenübertragung zwischen einem Speichercontroller und einem Halbleiterspeicher
KR100666931B1 (ko) 2004-12-28 2007-01-10 주식회사 하이닉스반도체 반도체메모리소자
US7471130B2 (en) * 2005-05-19 2008-12-30 Micron Technology, Inc. Graduated delay line for increased clock skew correction circuit operating range
DE102005038736A1 (de) * 2005-08-16 2007-03-01 Infineon Technologies Ag Phasenverschiebungsvorrichtung
KR100714892B1 (ko) * 2005-10-26 2007-05-04 삼성전자주식회사 클럭신호 발생기 및 이를 구비한 위상 및 지연 동기 루프
KR100650845B1 (ko) * 2005-12-27 2006-11-28 주식회사 하이닉스반도체 소비 전력을 감소시키는 버퍼 제어 회로와, 이를 포함하는메모리 모듈용 반도체 메모리 장치 및 그 제어 동작 방법
KR100656456B1 (ko) * 2005-12-27 2006-12-11 주식회사 하이닉스반도체 반도체 메모리의 온 다이 터미네이션 장치 및 방법
US20070205817A1 (en) * 2006-03-03 2007-09-06 Tyler Gomm Method, circuit and system for detecting a locked state of a clock synchronization circuit
JP4282713B2 (ja) * 2006-11-28 2009-06-24 エルピーダメモリ株式会社 キャリブレーション回路を有する半導体装置及びキャリブレーション方法
KR100822307B1 (ko) * 2007-09-20 2008-04-16 주식회사 아나패스 데이터 구동 회로 및 지연 고정 루프
KR101994847B1 (ko) * 2012-05-02 2019-07-01 에스케이하이닉스 주식회사 위상 고정 루프, 이를 포함하는 집적회로 칩 및 테스트 시스템

Family Cites Families (105)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3633174A (en) * 1970-04-14 1972-01-04 Us Navy Memory system having self-adjusting strobe timing
US4096402A (en) * 1975-12-29 1978-06-20 Mostek Corporation MOSFET buffer for TTL logic input and method of operation
US4077016A (en) * 1977-02-22 1978-02-28 Ncr Corporation Apparatus and method for inhibiting false locking of a phase-locked loop
US4404474A (en) * 1981-02-06 1983-09-13 Rca Corporation Active load pulse generating circuit
US4511846A (en) * 1982-05-24 1985-04-16 Fairchild Camera And Instrument Corporation Deskewing time-critical signals in automatic test equipment
US4514647A (en) * 1983-08-01 1985-04-30 At&T Bell Laboratories Chipset synchronization arrangement
US4687951A (en) * 1984-10-29 1987-08-18 Texas Instruments Incorporated Fuse link for varying chip operating parameters
US4600895A (en) * 1985-04-26 1986-07-15 Minnesota Mining And Manufacturing Company Precision phase synchronization of free-running oscillator output signal to reference signal
US4638187A (en) * 1985-10-01 1987-01-20 Vtc Incorporated CMOS output buffer providing high drive current with minimum output signal distortion
GB2184622B (en) * 1985-12-23 1989-10-18 Philips Nv Outputbuffer and control circuit providing limited current rate at the output
JPS6337894A (ja) * 1986-07-30 1988-02-18 Mitsubishi Electric Corp ランダムアクセスメモリ
US4773085A (en) * 1987-06-12 1988-09-20 Bell Communications Research, Inc. Phase and frequency detector circuits
US5086500A (en) * 1987-08-07 1992-02-04 Tektronix, Inc. Synchronized system by adjusting independently clock signals arriving at a plurality of integrated circuits
US4893087A (en) * 1988-01-07 1990-01-09 Motorola, Inc. Low voltage and low power frequency synthesizer
KR0141494B1 (ko) * 1988-01-28 1998-07-15 미다 가쓰시게 레벨시프트회로를 사용한 고속센스 방식의 반도체장치
US4902986B1 (en) * 1989-01-30 1998-09-01 Credence Systems Corp Phased locked loop to provide precise frequency and phase tracking of two signals
US5020023A (en) * 1989-02-23 1991-05-28 International Business Machines Corporation Automatic vernier synchronization of skewed data streams
US4958088A (en) * 1989-06-19 1990-09-18 Micron Technology, Inc. Low power three-stage CMOS input buffer with controlled switching
US5165046A (en) * 1989-11-06 1992-11-17 Micron Technology, Inc. High speed CMOS driver circuit
JP2671538B2 (ja) * 1990-01-17 1997-10-29 松下電器産業株式会社 入力バッファ回路
JP2787725B2 (ja) * 1990-02-14 1998-08-20 第一電子工業株式会社 データ・クロックのタイミング合わせ回路
US5408640A (en) * 1990-02-21 1995-04-18 Digital Equipment Corporation Phase delay compensator using gating signal generated by a synchronizer for loading and shifting of bit pattern to produce clock phases corresponding to frequency changes
US5239206A (en) * 1990-03-06 1993-08-24 Advanced Micro Devices, Inc. Synchronous circuit with clock skew compensating function and circuits utilizing same
US5243703A (en) * 1990-04-18 1993-09-07 Rambus, Inc. Apparatus for synchronously generating clock signals in a data processing system
IL96808A (en) * 1990-04-18 1996-03-31 Rambus Inc Introductory / Origin Circuit Agreed Using High-Performance Brokerage
US5038115A (en) * 1990-05-29 1991-08-06 Myers Glen A Method and apparatus for frequency independent phase tracking of input signals in receiving systems and the like
US5134311A (en) * 1990-06-07 1992-07-28 International Business Machines Corporation Self-adjusting impedance matching driver
EP0476585B1 (de) * 1990-09-18 1998-08-26 Fujitsu Limited Elektronische Anordnung mit einem Bezugsverzögerungsgenerator
US5122690A (en) * 1990-10-16 1992-06-16 General Electric Company Interface circuits including driver circuits with switching noise reduction
US5257294A (en) * 1990-11-13 1993-10-26 National Semiconductor Corporation Phase-locked loop circuit and method
US5128563A (en) * 1990-11-28 1992-07-07 Micron Technology, Inc. CMOS bootstrapped output driver method and circuit
US5281865A (en) * 1990-11-28 1994-01-25 Hitachi, Ltd. Flip-flop circuit
US5150186A (en) * 1991-03-06 1992-09-22 Micron Technology, Inc. CMOS output pull-up driver
US5128560A (en) * 1991-03-22 1992-07-07 Micron Technology, Inc. Boosted supply output driver circuit for driving an all N-channel output stage
US5220208A (en) * 1991-04-29 1993-06-15 Texas Instruments Incorporated Circuitry and method for controlling current in an electronic circuit
US5256989A (en) * 1991-05-03 1993-10-26 Motorola, Inc. Lock detection for a phase lock loop
US5194765A (en) * 1991-06-28 1993-03-16 At&T Bell Laboratories Digitally controlled element sizing
US5276642A (en) * 1991-07-15 1994-01-04 Micron Technology, Inc. Method for performing a split read/write operation in a dynamic random access memory
KR970005124B1 (ko) * 1991-08-14 1997-04-12 가부시끼가이샤 아드반테스트 가변지연회로
US5283631A (en) * 1991-11-01 1994-02-01 Hewlett-Packard Co. Programmable capacitance delay element having inverters controlled by adjustable voltage to offset temperature and voltage supply variations
US5498990A (en) * 1991-11-05 1996-03-12 Monolithic System Technology, Inc. Reduced CMOS-swing clamping circuit for bus lines
US5295164A (en) * 1991-12-23 1994-03-15 Apple Computer, Inc. Apparatus for providing a system clock locked to an external clock over a wide range of frequencies
DE4206082C1 (de) * 1992-02-27 1993-04-08 Siemens Ag, 8000 Muenchen, De
DE4345604B3 (de) * 1992-03-06 2012-07-12 Rambus Inc. Vorrichtung zur Kommunikation mit einem DRAM
US5355391A (en) * 1992-03-06 1994-10-11 Rambus, Inc. High speed bus system
US5278460A (en) * 1992-04-07 1994-01-11 Micron Technology, Inc. Voltage compensating CMOS input buffer
US5390308A (en) * 1992-04-15 1995-02-14 Rambus, Inc. Method and apparatus for address mapping of dynamic random access memory
US5254883A (en) * 1992-04-22 1993-10-19 Rambus, Inc. Electrical current source circuitry for a bus
US5485490A (en) * 1992-05-28 1996-01-16 Rambus, Inc. Method and circuitry for clock synchronization
US5268639A (en) * 1992-06-05 1993-12-07 Rambus, Inc. Testing timing parameters of high speed integrated circuit devices
US5274276A (en) * 1992-06-26 1993-12-28 Micron Technology, Inc. Output driver circuit comprising a programmable circuit for determining the potential at the output node and the method of implementing the circuit
US5473274A (en) * 1992-09-14 1995-12-05 Nec America, Inc. Local clock generator
FR2696061B1 (fr) * 1992-09-22 1994-12-02 Rainard Jean Luc Procédé pour retarder temporellement un signal et circuit à retard correspondant.
EP0596657A3 (de) * 1992-11-05 1994-12-07 American Telephone & Telegraph Normalisierung der sichtbaren Fortpflanzungsverzögerung.
US5311481A (en) * 1992-12-17 1994-05-10 Micron Technology, Inc. Wordline driver circuit having a directly gated pull-down device
JP2792801B2 (ja) * 1992-12-28 1998-09-03 三菱電機株式会社 半導体集積回路並びにその設計方法及び製造方法
US5347559A (en) * 1992-12-30 1994-09-13 Digital Equipment Corporation Apparatus and method of data transfer between systems using different clocks
US5347177A (en) * 1993-01-14 1994-09-13 Lipp Robert J System for interconnecting VLSI circuits with transmission line characteristics
JP2605576B2 (ja) * 1993-04-02 1997-04-30 日本電気株式会社 同期型半導体メモリ
US5488321A (en) * 1993-04-07 1996-01-30 Rambus, Inc. Static high speed comparator
US5347179A (en) * 1993-04-15 1994-09-13 Micron Semiconductor, Inc. Inverting output driver circuit for reducing electron injection into the substrate
US5337285A (en) * 1993-05-21 1994-08-09 Rambus, Inc. Method and apparatus for power control in devices
AU6988494A (en) * 1993-05-28 1994-12-20 Rambus Inc. Method and apparatus for implementing refresh in a synchronous dram system
US5506814A (en) * 1993-05-28 1996-04-09 Micron Technology, Inc. Video random access memory device and method implementing independent two WE nibble control
JP2636677B2 (ja) * 1993-06-02 1997-07-30 日本電気株式会社 半導体集積回路
US5511024A (en) * 1993-06-02 1996-04-23 Rambus, Inc. Dynamic random access memory system
US5428311A (en) * 1993-06-30 1995-06-27 Sgs-Thomson Microelectronics, Inc. Fuse circuitry to control the propagation delay of an IC
US5473639A (en) * 1993-07-26 1995-12-05 Hewlett-Packard Company Clock recovery apparatus with means for sensing an out of lock condition
JP3232351B2 (ja) * 1993-10-06 2001-11-26 三菱電機株式会社 デジタル回路装置
US5451898A (en) * 1993-11-12 1995-09-19 Rambus, Inc. Bias circuit and differential amplifier having stabilized output swing
JPH07153286A (ja) * 1993-11-30 1995-06-16 Sony Corp 半導体不揮発性記憶装置
US5400283A (en) * 1993-12-13 1995-03-21 Micron Semiconductor, Inc. RAM row decode circuitry that utilizes a precharge circuit that is deactivated by a feedback from an activated word line driver
KR0132504B1 (ko) * 1993-12-21 1998-10-01 문정환 데이타 출력버퍼
US5579326A (en) * 1994-01-31 1996-11-26 Sgs-Thomson Microelectronics, Inc. Method and apparatus for programming signal timing
KR100393317B1 (ko) * 1994-02-15 2003-10-23 람버스 인코포레이티드 지연동기루프
EP0668592B1 (de) 1994-02-18 2000-05-17 STMicroelectronics S.r.l. Inneres Taktsteuerungsverfahren und Schaltung für programmierbare Speichern
US5424672A (en) * 1994-02-24 1995-06-13 Micron Semiconductor, Inc. Low current redundancy fuse assembly
US5440514A (en) * 1994-03-08 1995-08-08 Motorola Inc. Write control for a memory using a delay locked loop
US5557224A (en) * 1994-04-15 1996-09-17 International Business Machines Corporation Apparatus and method for generating a phase-controlled clock signal
JP3553639B2 (ja) * 1994-05-12 2004-08-11 アジレント・テクノロジーズ・インク タイミング調整回路
US5457407A (en) * 1994-07-06 1995-10-10 Sony Electronics Inc. Binary weighted reference circuit for a variable impedance output buffer
JP3537500B2 (ja) 1994-08-16 2004-06-14 バー−ブラウン・コーポレーション インバータ装置
JP3176228B2 (ja) * 1994-08-23 2001-06-11 シャープ株式会社 半導体記憶装置
GB9417266D0 (en) * 1994-08-26 1994-10-19 Inmos Ltd Testing a non-volatile memory
JP3013714B2 (ja) * 1994-09-28 2000-02-28 日本電気株式会社 半導体記憶装置
JPH08139572A (ja) * 1994-11-07 1996-05-31 Mitsubishi Electric Corp ラッチ回路
US5497127A (en) * 1994-12-14 1996-03-05 David Sarnoff Research Center, Inc. Wide frequency range CMOS relaxation oscillator with variable hysteresis
US5577236A (en) * 1994-12-30 1996-11-19 International Business Machines Corporation Memory controller for reading data from synchronous RAM
US5578940A (en) * 1995-04-04 1996-11-26 Rambus, Inc. Modular bus with single or double parallel termination
US5621690A (en) * 1995-04-28 1997-04-15 Intel Corporation Nonvolatile memory blocking architecture and redundancy
JP3386924B2 (ja) * 1995-05-22 2003-03-17 株式会社日立製作所 半導体装置
US5581197A (en) * 1995-05-31 1996-12-03 Hewlett-Packard Co. Method of programming a desired source resistance for a driver stage
US5576645A (en) * 1995-06-05 1996-11-19 Hughes Aircraft Company Sample and hold flip-flop for CMOS logic
US5636173A (en) * 1995-06-07 1997-06-03 Micron Technology, Inc. Auto-precharge during bank selection
JP3403551B2 (ja) 1995-07-14 2003-05-06 沖電気工業株式会社 クロック分配回路
US5621340A (en) * 1995-08-02 1997-04-15 Rambus Inc. Differential comparator for amplifying small swing signals to a full swing output
JP3252666B2 (ja) * 1995-08-14 2002-02-04 日本電気株式会社 半導体記憶装置
US5578941A (en) * 1995-08-23 1996-11-26 Micron Technology, Inc. Voltage compensating CMOS input buffer circuit
US5692165A (en) 1995-09-12 1997-11-25 Micron Electronics Inc. Memory controller with low skew control signal
US5594690A (en) * 1995-12-15 1997-01-14 Unisys Corporation Integrated circuit memory having high speed and low power by selectively coupling compensation components to a pulse generator
US5636174A (en) * 1996-01-11 1997-06-03 Cirrus Logic, Inc. Fast cycle time-low latency dynamic random access memories and systems and methods using the same
US5712580A (en) 1996-02-14 1998-01-27 International Business Machines Corporation Linear phase detector for half-speed quadrature clocking architecture
US5627791A (en) * 1996-02-16 1997-05-06 Micron Technology, Inc. Multiple bank memory with auto refresh to specified bank
US5668763A (en) 1996-02-26 1997-09-16 Fujitsu Limited Semiconductor memory for increasing the number of half good memories by selecting and using good memory blocks
US5621739A (en) * 1996-05-07 1997-04-15 Intel Corporation Method and apparatus for buffer self-test and characterization

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE102006051292B4 (de) * 2005-10-26 2010-08-19 Samsung Electronics Co., Ltd. Takterzeugungsschaltung, Multiphasen-Takterzeuger, Speicherelement, Verfahren zum Erzeugen von Taktsignalen und Verfahren zum Verriegeln der Phase
US8004335B2 (en) 2008-02-11 2011-08-23 International Business Machines Corporation Phase interpolator system and associated methods

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EP1002369B1 (de) 2002-05-29
WO1998035446A1 (en) 1998-08-13
JP4019126B2 (ja) 2007-12-12
EP1002369A1 (de) 2000-05-24
DE69805628D1 (de) 2002-07-04
JP2001511285A (ja) 2001-08-07
AU6146398A (en) 1998-08-26
ATE218255T1 (de) 2002-06-15
KR100518479B1 (ko) 2005-10-05
US5920518A (en) 1999-07-06
KR20000071001A (ko) 2000-11-25

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