DE69802927D1 - Redundanzschaltung für programmierbare logikanordnung mit verschachtelten eingangsschaltkreisen - Google Patents
Redundanzschaltung für programmierbare logikanordnung mit verschachtelten eingangsschaltkreisenInfo
- Publication number
- DE69802927D1 DE69802927D1 DE69802927T DE69802927T DE69802927D1 DE 69802927 D1 DE69802927 D1 DE 69802927D1 DE 69802927 T DE69802927 T DE 69802927T DE 69802927 T DE69802927 T DE 69802927T DE 69802927 D1 DE69802927 D1 DE 69802927D1
- Authority
- DE
- Germany
- Prior art keywords
- logic
- column
- programmable logic
- circuitry
- regions
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
- H03K19/173—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components
- H03K19/177—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form
- H03K19/17748—Structural details of configuration resources
- H03K19/17764—Structural details of configuration resources for reliability
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
- H03K19/173—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components
- H03K19/177—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form
- H03K19/17724—Structural details of logic blocks
- H03K19/17728—Reconfigurable logic blocks, e.g. lookup tables
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
- H03K19/173—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components
- H03K19/177—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form
- H03K19/17736—Structural details of routing resources
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
- H03K19/173—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components
- H03K19/177—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form
- H03K19/1778—Structural details for adapting physical parameters
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US4761097P | 1997-05-23 | 1997-05-23 | |
PCT/US1998/010301 WO1998053401A1 (en) | 1997-05-23 | 1998-05-20 | Redundancy circuitry for programmable logic devices with interleaved input circuits |
Publications (2)
Publication Number | Publication Date |
---|---|
DE69802927D1 true DE69802927D1 (de) | 2002-01-24 |
DE69802927T2 DE69802927T2 (de) | 2002-08-08 |
Family
ID=21949943
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
DE69802927T Expired - Lifetime DE69802927T2 (de) | 1997-05-23 | 1998-05-20 | Redundanzschaltung für programmierbare logikanordnung mit verschachtelten eingangsschaltkreisen |
Country Status (5)
Country | Link |
---|---|
US (3) | US6107820A (de) |
EP (1) | EP0983549B1 (de) |
JP (1) | JP3865789B2 (de) |
DE (1) | DE69802927T2 (de) |
WO (1) | WO1998053401A1 (de) |
Families Citing this family (103)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
DE69802927T2 (de) * | 1997-05-23 | 2002-08-08 | Altera Corp A Delaware Corp Sa | Redundanzschaltung für programmierbare logikanordnung mit verschachtelten eingangsschaltkreisen |
US6126451A (en) * | 1997-06-02 | 2000-10-03 | Compaq Computer Corporation | SCSI connector |
US6084427A (en) | 1998-05-19 | 2000-07-04 | Altera Corporation | Programmable logic devices with enhanced multiplexing capabilities |
US6600337B2 (en) | 2000-04-26 | 2003-07-29 | Altera Corporation | Line segmentation in programmable logic devices having redundancy circuitry |
NZ508052A (en) * | 2000-11-09 | 2003-06-30 | Derek Ward | Programmable controller |
EP1227385A3 (de) * | 2001-01-24 | 2005-11-23 | Matsushita Electric Industrial Co., Ltd. | Integrierte Halbleiterschaltung |
US6965249B2 (en) * | 2001-10-15 | 2005-11-15 | Altera Corporation | Programmable logic device with redundant circuitry |
US6803782B2 (en) * | 2002-03-21 | 2004-10-12 | John Conrad Koob | Arrayed processing element redundancy architecture |
FR2846491B1 (fr) * | 2002-10-25 | 2005-08-12 | Atmel Corp | Architecture comprenant des cellules de remplacement pour reparer des erreurs de conception dans des circuits integres apres fabrication |
US7111213B1 (en) | 2002-12-10 | 2006-09-19 | Altera Corporation | Failure isolation and repair techniques for integrated circuits |
US7062685B1 (en) | 2002-12-11 | 2006-06-13 | Altera Corporation | Techniques for providing early failure warning of a programmable circuit |
US7024327B1 (en) | 2002-12-18 | 2006-04-04 | Altera Corporation | Techniques for automatically generating tests for programmable circuits |
US7058534B1 (en) | 2003-03-19 | 2006-06-06 | Altera Corporation | Method and apparatus for application specific test of PLDs |
US7215140B1 (en) | 2003-05-30 | 2007-05-08 | Altera Corporation | Programmable logic device having regions of non-repairable circuitry within an array of repairable circuitry and associated configuration hardware and method |
US6879207B1 (en) * | 2003-12-18 | 2005-04-12 | Nvidia Corporation | Defect tolerant redundancy |
US7180324B2 (en) | 2004-05-28 | 2007-02-20 | Altera Corporation | Redundancy structures and methods in a programmable logic device |
DE602005010639D1 (de) * | 2004-09-03 | 2008-12-11 | Derek Ward | Verbesserungen an numerischen Steuerungen und verwandten elektronischen Geräten |
US7277346B1 (en) | 2004-12-14 | 2007-10-02 | Altera Corporation | Method and system for hard failure repairs in the field |
US7265573B1 (en) | 2004-12-18 | 2007-09-04 | Altera Corporation | Methods and structures for protecting programming data for a programmable logic device |
US7268587B1 (en) | 2005-06-14 | 2007-09-11 | Xilinx, Inc. | Programmable logic block with carry chains providing lookahead functions of different lengths |
US7202698B1 (en) * | 2005-06-14 | 2007-04-10 | Xilinx, Inc. | Integrated circuit having a programmable input structure with bounce capability |
US7265576B1 (en) | 2005-06-14 | 2007-09-04 | Xilinx, Inc. | Programmable lookup table with dual input and output terminals in RAM mode |
US7256612B1 (en) | 2005-06-14 | 2007-08-14 | Xilinx, Inc. | Programmable logic block providing carry chain with programmable initialization values |
US7276934B1 (en) | 2005-06-14 | 2007-10-02 | Xilinx, Inc. | Integrated circuit with programmable routing structure including diagonal interconnect lines |
US7804719B1 (en) | 2005-06-14 | 2010-09-28 | Xilinx, Inc. | Programmable logic block having reduced output delay during RAM write processes when programmed to function in RAM mode |
US7253658B1 (en) | 2005-06-14 | 2007-08-07 | Xilinx, Inc. | Integrated circuit providing direct access to multi-directional interconnect lines in a general interconnect structure |
US7274214B1 (en) | 2005-06-14 | 2007-09-25 | Xilinx, Inc. | Efficient tile layout for a programmable logic device |
US7375552B1 (en) | 2005-06-14 | 2008-05-20 | Xilinx, Inc. | Programmable logic block with dedicated and selectable lookup table outputs coupled to general interconnect structure |
JP4552803B2 (ja) * | 2005-08-10 | 2010-09-29 | ソニー株式会社 | 半導体集積回路 |
US8620980B1 (en) | 2005-09-27 | 2013-12-31 | Altera Corporation | Programmable device with specialized multiplier blocks |
US7644385B1 (en) | 2005-11-07 | 2010-01-05 | Altera Corporation | Programmable logic device with performance variation compensation |
US8266198B2 (en) | 2006-02-09 | 2012-09-11 | Altera Corporation | Specialized processing block for programmable logic device |
US8301681B1 (en) | 2006-02-09 | 2012-10-30 | Altera Corporation | Specialized processing block for programmable logic device |
US8041759B1 (en) | 2006-02-09 | 2011-10-18 | Altera Corporation | Specialized processing block for programmable logic device |
US8266199B2 (en) | 2006-02-09 | 2012-09-11 | Altera Corporation | Specialized processing block for programmable logic device |
US7836117B1 (en) | 2006-04-07 | 2010-11-16 | Altera Corporation | Specialized processing block for programmable logic device |
US7212032B1 (en) * | 2006-04-25 | 2007-05-01 | Altera Corporation | Method and apparatus for monitoring yield of integrated circuits |
US7408380B1 (en) * | 2006-05-16 | 2008-08-05 | Xilinx, Inc. | Method and apparatus for a redundant transceiver architecture |
US7822799B1 (en) | 2006-06-26 | 2010-10-26 | Altera Corporation | Adder-rounder circuitry for specialized processing block in programmable logic device |
US8386550B1 (en) | 2006-09-20 | 2013-02-26 | Altera Corporation | Method for configuring a finite impulse response filter in a programmable logic device |
US7930336B2 (en) | 2006-12-05 | 2011-04-19 | Altera Corporation | Large multiplier for programmable logic device |
US8386553B1 (en) | 2006-12-05 | 2013-02-26 | Altera Corporation | Large multiplier for programmable logic device |
US7814137B1 (en) | 2007-01-09 | 2010-10-12 | Altera Corporation | Combined interpolation and decimation filter for programmable logic device |
US7865541B1 (en) | 2007-01-22 | 2011-01-04 | Altera Corporation | Configuring floating point operations in a programmable logic device |
US8650231B1 (en) | 2007-01-22 | 2014-02-11 | Altera Corporation | Configuring floating point operations in a programmable device |
US8645450B1 (en) | 2007-03-02 | 2014-02-04 | Altera Corporation | Multiplier-accumulator circuitry and methods |
US7724031B2 (en) * | 2007-03-21 | 2010-05-25 | Altera Corporation | Staggered logic array block architecture |
US7995067B2 (en) * | 2007-03-29 | 2011-08-09 | Mobileye Technologies Limited | Cyclical image buffer |
US8516025B2 (en) | 2007-04-17 | 2013-08-20 | Cypress Semiconductor Corporation | Clock driven dynamic datapath chaining |
US8026739B2 (en) | 2007-04-17 | 2011-09-27 | Cypress Semiconductor Corporation | System level interconnect with programmable switching |
US8111577B2 (en) | 2007-04-17 | 2012-02-07 | Cypress Semiconductor Corporation | System comprising a state-monitoring memory element |
US9564902B2 (en) | 2007-04-17 | 2017-02-07 | Cypress Semiconductor Corporation | Dynamically configurable and re-configurable data path |
US7737724B2 (en) | 2007-04-17 | 2010-06-15 | Cypress Semiconductor Corporation | Universal digital block interconnection and channel routing |
US20080263319A1 (en) * | 2007-04-17 | 2008-10-23 | Cypress Semiconductor Corporation | Universal digital block with integrated arithmetic logic unit |
WO2008144546A1 (en) | 2007-05-17 | 2008-11-27 | Octio Geophysical As | Apparatus and method for collecting geophysical information |
US7949699B1 (en) | 2007-08-30 | 2011-05-24 | Altera Corporation | Implementation of decimation filter in integrated circuit device using ram-based data storage |
US7589552B1 (en) | 2007-10-23 | 2009-09-15 | Altera Corporation | Integrated circuit with redundancy |
US8959137B1 (en) | 2008-02-20 | 2015-02-17 | Altera Corporation | Implementing large multipliers in a programmable integrated circuit device |
US8244789B1 (en) | 2008-03-14 | 2012-08-14 | Altera Corporation | Normalization of floating point operations in a programmable integrated circuit device |
US8626815B1 (en) | 2008-07-14 | 2014-01-07 | Altera Corporation | Configuring a programmable integrated circuit device to perform matrix multiplication |
US8255448B1 (en) | 2008-10-02 | 2012-08-28 | Altera Corporation | Implementing division in a programmable integrated circuit device |
US8307023B1 (en) | 2008-10-10 | 2012-11-06 | Altera Corporation | DSP block for implementing large multiplier on a programmable integrated circuit device |
US8706790B1 (en) | 2009-03-03 | 2014-04-22 | Altera Corporation | Implementing mixed-precision floating-point operations in a programmable integrated circuit device |
US8468192B1 (en) | 2009-03-03 | 2013-06-18 | Altera Corporation | Implementing multipliers in a programmable integrated circuit device |
US8645449B1 (en) | 2009-03-03 | 2014-02-04 | Altera Corporation | Combined floating point adder and subtractor |
US8805916B2 (en) | 2009-03-03 | 2014-08-12 | Altera Corporation | Digital signal processing circuitry with redundancy and bidirectional data paths |
US8886696B1 (en) | 2009-03-03 | 2014-11-11 | Altera Corporation | Digital signal processing circuitry with redundancy and ability to support larger multipliers |
US8549055B2 (en) | 2009-03-03 | 2013-10-01 | Altera Corporation | Modular digital signal processing circuitry with optionally usable, dedicated connections between modules of the circuitry |
US8650236B1 (en) | 2009-08-04 | 2014-02-11 | Altera Corporation | High-rate interpolation or decimation filter in integrated circuit device |
US8412756B1 (en) | 2009-09-11 | 2013-04-02 | Altera Corporation | Multi-operand floating point operations in a programmable integrated circuit device |
US8396914B1 (en) | 2009-09-11 | 2013-03-12 | Altera Corporation | Matrix decomposition in an integrated circuit device |
US8539016B1 (en) | 2010-02-09 | 2013-09-17 | Altera Corporation | QR decomposition in an integrated circuit device |
US7948267B1 (en) | 2010-02-09 | 2011-05-24 | Altera Corporation | Efficient rounding circuits and methods in configurable integrated circuit devices |
US8601044B2 (en) | 2010-03-02 | 2013-12-03 | Altera Corporation | Discrete Fourier Transform in an integrated circuit device |
US8458243B1 (en) | 2010-03-03 | 2013-06-04 | Altera Corporation | Digital signal processing circuit blocks with support for systolic finite-impulse-response digital filtering |
US7902855B1 (en) | 2010-03-03 | 2011-03-08 | Altera Corporation | Repairable IO in an integrated circuit |
US8484265B1 (en) | 2010-03-04 | 2013-07-09 | Altera Corporation | Angular range reduction in an integrated circuit device |
US8510354B1 (en) | 2010-03-12 | 2013-08-13 | Altera Corporation | Calculation of trigonometric functions in an integrated circuit device |
US8539014B2 (en) | 2010-03-25 | 2013-09-17 | Altera Corporation | Solving linear matrices in an integrated circuit device |
US8862650B2 (en) | 2010-06-25 | 2014-10-14 | Altera Corporation | Calculation of trigonometric functions in an integrated circuit device |
US8589463B2 (en) | 2010-06-25 | 2013-11-19 | Altera Corporation | Calculation of trigonometric functions in an integrated circuit device |
US8577951B1 (en) | 2010-08-19 | 2013-11-05 | Altera Corporation | Matrix operations in an integrated circuit device |
US8645451B2 (en) | 2011-03-10 | 2014-02-04 | Altera Corporation | Double-clocked specialized processing block in an integrated circuit device |
US9600278B1 (en) | 2011-05-09 | 2017-03-21 | Altera Corporation | Programmable device using fixed and configurable logic to implement recursive trees |
US8812576B1 (en) | 2011-09-12 | 2014-08-19 | Altera Corporation | QR decomposition in an integrated circuit device |
US9053045B1 (en) | 2011-09-16 | 2015-06-09 | Altera Corporation | Computing floating-point polynomials in an integrated circuit device |
US8949298B1 (en) | 2011-09-16 | 2015-02-03 | Altera Corporation | Computing floating-point polynomials in an integrated circuit device |
KR101209824B1 (ko) | 2011-10-12 | 2012-12-07 | 고려대학교 산학협력단 | 블록 인터리빙 장치 |
US8762443B1 (en) | 2011-11-15 | 2014-06-24 | Altera Corporation | Matrix operations in an integrated circuit device |
US9236864B1 (en) | 2012-01-17 | 2016-01-12 | Altera Corporation | Stacked integrated circuit with redundancy in die-to-die interconnects |
US8543634B1 (en) | 2012-03-30 | 2013-09-24 | Altera Corporation | Specialized processing block for programmable integrated circuit device |
US9098332B1 (en) | 2012-06-01 | 2015-08-04 | Altera Corporation | Specialized processing block with fixed- and floating-point structures |
US8996600B1 (en) | 2012-08-03 | 2015-03-31 | Altera Corporation | Specialized processing block for implementing floating-point multiplier with subnormal operation support |
US8704548B1 (en) * | 2012-10-19 | 2014-04-22 | Altera Corporation | Methods and apparatus for building bus interconnection networks using programmable interconnection resources |
US8860460B1 (en) * | 2012-11-05 | 2014-10-14 | Altera Corporation | Programmable integrated circuits with redundant circuitry |
US9207909B1 (en) | 2012-11-26 | 2015-12-08 | Altera Corporation | Polynomial calculations optimized for programmable integrated circuit device structures |
US9189200B1 (en) | 2013-03-14 | 2015-11-17 | Altera Corporation | Multiple-precision processing block in a programmable integrated circuit device |
US9348795B1 (en) | 2013-07-03 | 2016-05-24 | Altera Corporation | Programmable device using fixed and configurable logic to implement floating-point rounding |
US9030227B1 (en) | 2013-08-20 | 2015-05-12 | Altera Corporation | Methods and apparatus for providing redundancy on multi-chip devices |
US9379687B1 (en) | 2014-01-14 | 2016-06-28 | Altera Corporation | Pipelined systolic finite impulse response filter |
US9684488B2 (en) | 2015-03-26 | 2017-06-20 | Altera Corporation | Combined adder and pre-adder for high-radix multiplier circuit |
KR102557310B1 (ko) * | 2016-08-09 | 2023-07-20 | 에스케이하이닉스 주식회사 | 반도체 장치 |
US10942706B2 (en) | 2017-05-05 | 2021-03-09 | Intel Corporation | Implementation of floating-point trigonometric functions in an integrated circuit device |
Family Cites Families (58)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US33521A (en) * | 1861-10-22 | Improved apparatus for heating air for blast-furnaces | ||
US3566153A (en) * | 1969-04-30 | 1971-02-23 | Texas Instruments Inc | Programmable sequential logic |
US3805039A (en) * | 1972-11-30 | 1974-04-16 | Raytheon Co | High reliability system employing subelement redundancy |
US3995261A (en) * | 1975-02-24 | 1976-11-30 | Stanford Research Institute | Reconfigurable memory |
US4020469A (en) * | 1975-04-09 | 1977-04-26 | Frank Manning | Programmable arrays |
US4051354A (en) * | 1975-07-03 | 1977-09-27 | Texas Instruments Incorporated | Fault-tolerant cell addressable array |
US4124899A (en) * | 1977-05-23 | 1978-11-07 | Monolithic Memories, Inc. | Programmable array logic circuit |
DE3015992A1 (de) * | 1980-04-25 | 1981-11-05 | Ibm Deutschland Gmbh, 7000 Stuttgart | Programmierbare logische anordnung |
US4538247A (en) * | 1983-01-14 | 1985-08-27 | Fairchild Research Center | Redundant rows in integrated circuit memories |
US4566102A (en) * | 1983-04-18 | 1986-01-21 | International Business Machines Corporation | Parallel-shift error reconfiguration |
JPS6093700A (ja) * | 1983-10-26 | 1985-05-25 | Hitachi Ltd | ライン切換回路およびそれを用いた半導体記憶装置 |
US4551814A (en) * | 1983-12-12 | 1985-11-05 | Aerojet-General Corporation | Functionally redundant logic network architectures |
US4713792A (en) * | 1985-06-06 | 1987-12-15 | Altera Corporation | Programmable macrocell using eprom or eeprom transistors for architecture control in programmable logic circuits |
US4617479B1 (en) * | 1984-05-03 | 1993-09-21 | Altera Semiconductor Corp. | Programmable logic array device using eprom technology |
US4774421A (en) * | 1984-05-03 | 1988-09-27 | Altera Corporation | Programmable logic array device using EPROM technology |
US4609986A (en) * | 1984-06-14 | 1986-09-02 | Altera Corporation | Programmable logic array device using EPROM technology |
US4598388A (en) * | 1985-01-22 | 1986-07-01 | Texas Instruments Incorporated | Semiconductor memory with redundant column circuitry |
US4706216A (en) * | 1985-02-27 | 1987-11-10 | Xilinx, Inc. | Configurable logic element |
US4677318A (en) * | 1985-04-12 | 1987-06-30 | Altera Corporation | Programmable logic storage element for programmable logic devices |
US4722084A (en) * | 1985-10-02 | 1988-01-26 | Itt Corporation | Array reconfiguration apparatus and methods particularly adapted for use with very large scale integrated circuits |
US4703206A (en) * | 1985-11-19 | 1987-10-27 | Signetics Corporation | Field-programmable logic device with programmable foldback to control number of logic levels |
US4700187A (en) * | 1985-12-02 | 1987-10-13 | Concurrent Logic, Inc. | Programmable, asynchronous logic cell and array |
JPS632351A (ja) * | 1986-06-20 | 1988-01-07 | Sharp Corp | 半導体装置 |
US5187393A (en) * | 1986-09-19 | 1993-02-16 | Actel Corporation | Reconfigurable programmable interconnect architecture |
US5019736A (en) * | 1986-11-07 | 1991-05-28 | Concurrent Logic, Inc. | Programmable logic cell and array |
US4829198A (en) * | 1987-04-10 | 1989-05-09 | International Business Machines Corporation | Fault tolerant logical circuitry |
US4800302A (en) * | 1987-07-17 | 1989-01-24 | Trw Inc. | Redundancy system with distributed mapping |
US4928022A (en) * | 1987-07-17 | 1990-05-22 | Trw Inc. | Redundancy interconnection circuitry |
US4920497A (en) * | 1987-10-27 | 1990-04-24 | State University Of New York | Method for rendering usuable a defective raw programmable logic array and a defective programmable logic array rendered usable by this method |
US4798976A (en) * | 1987-11-13 | 1989-01-17 | International Business Machines Corporation | Logic redundancy circuit scheme |
US4912342A (en) * | 1988-05-05 | 1990-03-27 | Altera Corporation | Programmable logic device with array blocks with programmable clocking |
US4871930A (en) * | 1988-05-05 | 1989-10-03 | Altera Corporation | Programmable logic device with array blocks connected via programmable interconnect |
KR910003594B1 (ko) * | 1988-05-13 | 1991-06-07 | 삼성전자 주식회사 | 스페어컬럼(column)선택방법 및 회로 |
US4899067A (en) * | 1988-07-22 | 1990-02-06 | Altera Corporation | Programmable logic devices with spare circuits for use in replacing defective circuits |
JPH0289299A (ja) * | 1988-09-27 | 1990-03-29 | Nec Corp | 半導体記憶装置 |
US5255228A (en) * | 1989-01-10 | 1993-10-19 | Matsushita Electronics Corporation | Semiconductor memory device with redundancy circuits |
US5471427A (en) * | 1989-06-05 | 1995-11-28 | Mitsubishi Denki Kabushiki Kaisha | Circuit for repairing defective bit in semiconductor memory device and repairing method |
GB8926004D0 (en) * | 1989-11-17 | 1990-01-10 | Inmos Ltd | Repairable memory circuit |
US5005158A (en) * | 1990-01-12 | 1991-04-02 | Sgs-Thomson Microelectronics, Inc. | Redundancy for serial memory |
US5204836A (en) * | 1990-10-30 | 1993-04-20 | Sun Microsystems, Inc. | Method and apparatus for implementing redundancy in parallel memory structures |
US5255227A (en) * | 1991-02-06 | 1993-10-19 | Hewlett-Packard Company | Switched row/column memory redundancy |
US5121006A (en) * | 1991-04-22 | 1992-06-09 | Altera Corporation | Registered logic macrocell with product term allocation and adjacent product term stealing |
US5220214A (en) * | 1991-04-22 | 1993-06-15 | Altera Corporation | Registered logic macrocell with product term allocation and adjacent product term stealing |
US5260610A (en) * | 1991-09-03 | 1993-11-09 | Altera Corporation | Programmable logic element interconnections for programmable logic array integrated circuits |
US5260611A (en) * | 1991-09-03 | 1993-11-09 | Altera Corporation | Programmable logic array having local and long distance conductors |
KR950000275B1 (ko) * | 1992-05-06 | 1995-01-12 | 삼성전자 주식회사 | 반도체 메모리 장치의 컬럼 리던던시 |
US5237219A (en) * | 1992-05-08 | 1993-08-17 | Altera Corporation | Methods and apparatus for programming cellular programmable logic integrated circuits |
JP2909328B2 (ja) * | 1992-11-02 | 1999-06-23 | 株式会社東芝 | フィールドプログラマブルゲートアレイ |
US5498975A (en) * | 1992-11-19 | 1996-03-12 | Altera Corporation | Implementation of redundancy on a programmable logic device |
US5434514A (en) * | 1992-11-19 | 1995-07-18 | Altera Corporation | Programmable logic devices with spare circuits for replacement of defects |
US5483178A (en) * | 1993-03-29 | 1996-01-09 | Altera Corporation | Programmable logic device with logic block outputs coupled to adjacent logic block output multiplexers |
CH688425A5 (fr) * | 1993-05-24 | 1997-09-15 | Suisse Electronique Microtech | Circuit électronique organisé en réseau matriciel de cellules. |
US5369314A (en) * | 1994-02-22 | 1994-11-29 | Altera Corporation | Programmable logic device with redundant circuitry |
US5426379A (en) * | 1994-07-29 | 1995-06-20 | Xilinx, Inc. | Field programmable gate array with built-in bitstream data expansion |
US5670895A (en) * | 1995-10-19 | 1997-09-23 | Altera Corporation | Routing connections for programmable logic array integrated circuits |
US5592102A (en) * | 1995-10-19 | 1997-01-07 | Altera Corporation | Means and apparatus to minimize the effects of silicon processing defects in programmable logic devices |
DE69802927T2 (de) * | 1997-05-23 | 2002-08-08 | Altera Corp A Delaware Corp Sa | Redundanzschaltung für programmierbare logikanordnung mit verschachtelten eingangsschaltkreisen |
JP3130269B2 (ja) | 1997-05-30 | 2001-01-31 | 愛三工業株式会社 | 燃料供給装置 |
-
1998
- 1998-05-20 DE DE69802927T patent/DE69802927T2/de not_active Expired - Lifetime
- 1998-05-20 JP JP55057098A patent/JP3865789B2/ja not_active Expired - Fee Related
- 1998-05-20 US US09/082,081 patent/US6107820A/en not_active Expired - Lifetime
- 1998-05-20 WO PCT/US1998/010301 patent/WO1998053401A1/en active IP Right Grant
- 1998-05-20 EP EP98923566A patent/EP0983549B1/de not_active Expired - Lifetime
-
2000
- 2000-03-17 US US09/527,903 patent/US6222382B1/en not_active Expired - Lifetime
-
2001
- 2001-02-28 US US09/795,870 patent/US6337578B2/en not_active Expired - Lifetime
Also Published As
Publication number | Publication date |
---|---|
DE69802927T2 (de) | 2002-08-08 |
US6337578B2 (en) | 2002-01-08 |
EP0983549A1 (de) | 2000-03-08 |
US6222382B1 (en) | 2001-04-24 |
JP2001526866A (ja) | 2001-12-18 |
US6107820A (en) | 2000-08-22 |
US20010006347A1 (en) | 2001-07-05 |
EP0983549B1 (de) | 2001-12-12 |
WO1998053401A1 (en) | 1998-11-26 |
JP3865789B2 (ja) | 2007-01-10 |
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