DE69802631D1 - Differentielle CMOS Logikfamilie - Google Patents
Differentielle CMOS LogikfamilieInfo
- Publication number
- DE69802631D1 DE69802631D1 DE69802631T DE69802631T DE69802631D1 DE 69802631 D1 DE69802631 D1 DE 69802631D1 DE 69802631 T DE69802631 T DE 69802631T DE 69802631 T DE69802631 T DE 69802631T DE 69802631 D1 DE69802631 D1 DE 69802631D1
- Authority
- DE
- Germany
- Prior art keywords
- cmos logic
- logic family
- differential cmos
- differential
- family
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
- H03K19/08—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices
- H03K19/094—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices using field-effect transistors
- H03K19/09432—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices using field-effect transistors with coupled sources or source coupled logic
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/20—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits characterised by logic function, e.g. AND, OR, NOR, NOT circuits
- H03K19/21—EXCLUSIVE-OR circuits, i.e. giving output if input signal exists at only one input; COINCIDENCE circuits, i.e. giving output only if all input signals are identical
- H03K19/215—EXCLUSIVE-OR circuits, i.e. giving output if input signal exists at only one input; COINCIDENCE circuits, i.e. giving output only if all input signals are identical using field-effect transistors
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
- H03K3/02—Generators characterised by the type of circuit or by the means used for producing pulses
- H03K3/027—Generators characterised by the type of circuit or by the means used for producing pulses by the use of logic circuits, with internal or external positive feedback
- H03K3/037—Bistable circuits
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US08/914,195 US6008670A (en) | 1997-08-19 | 1997-08-19 | Differential CMOS logic family |
Publications (2)
Publication Number | Publication Date |
---|---|
DE69802631D1 true DE69802631D1 (de) | 2002-01-10 |
DE69802631T2 DE69802631T2 (de) | 2002-05-23 |
Family
ID=25434030
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
DE69802631T Expired - Fee Related DE69802631T2 (de) | 1997-08-19 | 1998-03-26 | Differentielle CMOS Logikfamilie |
Country Status (3)
Country | Link |
---|---|
US (1) | US6008670A (de) |
EP (1) | EP0898370B1 (de) |
DE (1) | DE69802631T2 (de) |
Families Citing this family (20)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5978379A (en) | 1997-01-23 | 1999-11-02 | Gadzoox Networks, Inc. | Fiber channel learning bridge, learning half bridge, and protocol |
US6188339B1 (en) * | 1998-01-23 | 2001-02-13 | Fuji Photo Film Co., Ltd. | Differential multiplexer and differential logic circuit |
US7430171B2 (en) | 1998-11-19 | 2008-09-30 | Broadcom Corporation | Fibre channel arbitrated loop bufferless switch circuitry to increase bandwidth without significant increase in cost |
US6424194B1 (en) | 1999-06-28 | 2002-07-23 | Broadcom Corporation | Current-controlled CMOS logic family |
JP2002185260A (ja) * | 2000-12-19 | 2002-06-28 | Canon Inc | 増幅器及び撮像装置 |
US6617926B2 (en) * | 2001-06-29 | 2003-09-09 | Intel Corporation | Tail current node equalization for a variable offset amplifier |
US7239636B2 (en) | 2001-07-23 | 2007-07-03 | Broadcom Corporation | Multiple virtual channels for use in network devices |
US6731136B2 (en) | 2001-11-01 | 2004-05-04 | Hewlett-Packard Development Company, L.P. | Differential CMOS logic with dynamic bias |
US7295555B2 (en) | 2002-03-08 | 2007-11-13 | Broadcom Corporation | System and method for identifying upper layer protocol message boundaries |
US6566912B1 (en) * | 2002-04-30 | 2003-05-20 | Applied Micro Circuits Corporation | Integrated XOR/multiplexer for high speed phase detection |
US7346701B2 (en) | 2002-08-30 | 2008-03-18 | Broadcom Corporation | System and method for TCP offload |
US7934021B2 (en) | 2002-08-29 | 2011-04-26 | Broadcom Corporation | System and method for network interfacing |
US7411959B2 (en) | 2002-08-30 | 2008-08-12 | Broadcom Corporation | System and method for handling out-of-order frames |
US8180928B2 (en) | 2002-08-30 | 2012-05-15 | Broadcom Corporation | Method and system for supporting read operations with CRC for iSCSI and iSCSI chimney |
US7313623B2 (en) | 2002-08-30 | 2007-12-25 | Broadcom Corporation | System and method for TCP/IP offload independent of bandwidth delay product |
DE10324049B4 (de) * | 2003-05-27 | 2006-10-26 | Infineon Technologies Ag | Integrierte Schaltung und Verfahren zum Betreiben der integrierten Schaltung |
WO2006012362A2 (en) * | 2004-07-06 | 2006-02-02 | Bae Systems Information And Electronic Systems Integration Inc | Single-level parallel-gated carry/majority circuits and systems therefrom |
US7088138B2 (en) * | 2004-08-31 | 2006-08-08 | Intel Corporation | Symmetric and non-stacked XOR circuit |
US20110193598A1 (en) * | 2010-02-11 | 2011-08-11 | Texas Instruments Incorporated | Efficient retimer for clock dividers |
US10840907B1 (en) | 2019-11-19 | 2020-11-17 | Honeywell International Inc. | Source-coupled logic with reference controlled inputs |
Family Cites Families (11)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4686392A (en) * | 1985-10-30 | 1987-08-11 | International Business Machines Corporation | Multi-functional differential cascode voltage switch logic |
US5218246A (en) * | 1990-09-14 | 1993-06-08 | Acer, Incorporated | MOS analog XOR amplifier |
US5149992A (en) * | 1991-04-30 | 1992-09-22 | The State Of Oregon Acting By And Through The State Board Of Higher Education On Behalf Of Oregon State University | MOS folded source-coupled logic |
US5124588A (en) * | 1991-05-01 | 1992-06-23 | North American Philips Corporation | Programmable combinational logic circuit |
US5216295A (en) * | 1991-08-30 | 1993-06-01 | General Instrument Corp. | Current mode logic circuits employing IGFETS |
EP0548551A1 (de) * | 1991-12-26 | 1993-06-30 | Nec Corporation | Logische Schaltung mit hoher Geschwindigkeit und geringem Leistungsverbrauch |
US5298810A (en) * | 1992-09-11 | 1994-03-29 | Cypress Semiconductor Corporation | BiCMOS CMOS/ECL data multiplexer |
JP2630272B2 (ja) * | 1994-08-25 | 1997-07-16 | 日本電気株式会社 | 半導体集積回路 |
JP2728013B2 (ja) * | 1995-03-10 | 1998-03-18 | 日本電気株式会社 | BiCMOS論理ゲート回路 |
JPH08335860A (ja) * | 1995-06-08 | 1996-12-17 | Mitsubishi Electric Corp | 差動ラッチ回路 |
US5798658A (en) * | 1995-06-15 | 1998-08-25 | Werking; Paul M. | Source-coupled logic with reference controlled inputs |
-
1997
- 1997-08-19 US US08/914,195 patent/US6008670A/en not_active Expired - Fee Related
-
1998
- 1998-03-26 DE DE69802631T patent/DE69802631T2/de not_active Expired - Fee Related
- 1998-03-26 EP EP98105542A patent/EP0898370B1/de not_active Expired - Lifetime
Also Published As
Publication number | Publication date |
---|---|
US6008670A (en) | 1999-12-28 |
DE69802631T2 (de) | 2002-05-23 |
EP0898370A1 (de) | 1999-02-24 |
EP0898370B1 (de) | 2001-11-28 |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
8364 | No opposition during term of opposition | ||
8327 | Change in the person/name/address of the patent owner |
Owner name: AVAGO TECHNOLOGIES GENERAL IP ( SINGAPORE) PTE. LT |
|
8339 | Ceased/non-payment of the annual fee |