DE69732736D1 - Vielfaden-Busmaster - Google Patents

Vielfaden-Busmaster

Info

Publication number
DE69732736D1
DE69732736D1 DE69732736T DE69732736T DE69732736D1 DE 69732736 D1 DE69732736 D1 DE 69732736D1 DE 69732736 T DE69732736 T DE 69732736T DE 69732736 T DE69732736 T DE 69732736T DE 69732736 D1 DE69732736 D1 DE 69732736D1
Authority
DE
Germany
Prior art keywords
bus master
much thread
thread bus
much
master
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE69732736T
Other languages
English (en)
Other versions
DE69732736T2 (de
Inventor
John M Maclaren
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Compaq Computer Corp
Original Assignee
Compaq Computer Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Compaq Computer Corp filed Critical Compaq Computer Corp
Application granted granted Critical
Publication of DE69732736D1 publication Critical patent/DE69732736D1/de
Publication of DE69732736T2 publication Critical patent/DE69732736T2/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/36—Handling requests for interconnection or transfer for access to common bus or bus system
    • G06F13/362—Handling requests for interconnection or transfer for access to common bus or bus system with centralised access control
    • G06F13/364—Handling requests for interconnection or transfer for access to common bus or bus system with centralised access control using independent requests or grants, e.g. using separated request and grant lines
DE69732736T 1996-06-05 1997-06-04 Vielfaden-Busmaster Expired - Lifetime DE69732736T2 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US08/659,355 US6052513A (en) 1996-06-05 1996-06-05 Multi-threaded bus master
US659355 1996-06-05

Publications (2)

Publication Number Publication Date
DE69732736D1 true DE69732736D1 (de) 2005-04-21
DE69732736T2 DE69732736T2 (de) 2005-08-04

Family

ID=24645068

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69732736T Expired - Lifetime DE69732736T2 (de) 1996-06-05 1997-06-04 Vielfaden-Busmaster

Country Status (4)

Country Link
US (1) US6052513A (de)
EP (1) EP0811925B1 (de)
JP (1) JPH1055335A (de)
DE (1) DE69732736T2 (de)

Families Citing this family (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6275888B1 (en) * 1997-11-19 2001-08-14 Micron Technology, Inc. Method for configuring peer-to-peer bus bridges in a computer system using shadow configuration registers
US6345330B2 (en) * 1998-05-01 2002-02-05 Acqis Technology, Inc. Communication channel and interface devices for bridging computer interface buses
US6321335B1 (en) 1998-10-30 2001-11-20 Acqis Technology, Inc. Password protected modular computer method and device
US6643777B1 (en) 1999-05-14 2003-11-04 Acquis Technology, Inc. Data security method and device for computer modules
US6718415B1 (en) * 1999-05-14 2004-04-06 Acqis Technology, Inc. Computer system and method including console housing multiple computer modules having independent processing units, mass storage devices, and graphics controllers
US7114011B2 (en) * 2001-08-30 2006-09-26 Intel Corporation Multiprocessor-scalable streaming data server arrangement
US6832286B2 (en) * 2002-06-25 2004-12-14 Hewlett-Packard Development Company, L.P. Memory auto-precharge
DE10234933A1 (de) * 2002-07-31 2004-03-18 Advanced Micro Devices, Inc., Sunnyvale Pufferung von Non-Posted-Lesebefehlen und Antworten
US7990724B2 (en) 2006-12-19 2011-08-02 Juhasz Paul R Mobile motherboard
US8643168B1 (en) * 2012-10-16 2014-02-04 Lattice Semiconductor Corporation Integrated circuit package with input capacitance compensation
US10037150B2 (en) * 2016-07-15 2018-07-31 Advanced Micro Devices, Inc. Memory controller with virtual controller mode
CN110399325B (zh) * 2019-07-30 2023-05-30 江西理工大学 一种基于iic总线协议的改进型ip核

Family Cites Families (50)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5569830A (en) * 1978-11-20 1980-05-26 Toshiba Corp Intelligent terminal
EP0334627A3 (de) * 1988-03-23 1991-06-12 Du Pont Pixel Systems Limited Multiprozessorbauweise
JPH03188546A (ja) * 1989-12-18 1991-08-16 Fujitsu Ltd バスインターフェイス制御方式
US5454093A (en) * 1991-02-25 1995-09-26 International Business Machines Corporation Buffer bypass for quick data access
US5483641A (en) * 1991-12-17 1996-01-09 Dell Usa, L.P. System for scheduling readahead operations if new request is within a proximity of N last read requests wherein N is dependent on independent activities
JPH0789340B2 (ja) * 1992-01-02 1995-09-27 インターナショナル・ビジネス・マシーンズ・コーポレイション バス間インターフェースにおいてアドレス・ロケーションの判定を行なう方法及び装置
CA2080210C (en) * 1992-01-02 1998-10-27 Nader Amini Bidirectional data storage facility for bus interface unit
US5491811A (en) * 1992-04-20 1996-02-13 International Business Machines Corporation Cache system using mask bits to recorder the sequences for transfers of data through cache to system memory
US5579530A (en) * 1992-06-11 1996-11-26 Intel Corporation Method and apparatus for dynamically allocating access time to a resource shared between a peripheral bus and a host bus by dynamically controlling the size of burst data transfers on the peripheral bus
JP2531903B2 (ja) * 1992-06-22 1996-09-04 インターナショナル・ビジネス・マシーンズ・コーポレイション コンピュ―タ・システムおよびシステム拡張装置
US5519839A (en) * 1992-10-02 1996-05-21 Compaq Computer Corp. Double buffering operations between the memory bus and the expansion bus of a computer system
US5535395A (en) * 1992-10-02 1996-07-09 Compaq Computer Corporation Prioritization of microprocessors in multiprocessor computer systems
US5463753A (en) * 1992-10-02 1995-10-31 Compaq Computer Corp. Method and apparatus for reducing non-snoop window of a cache controller by delaying host bus grant signal to the cache controller
US5381528A (en) * 1992-10-15 1995-01-10 Maxtor Corporation Demand allocation of read/write buffer partitions favoring sequential read cache
US5522050A (en) * 1993-05-28 1996-05-28 International Business Machines Corporation Bus-to-bus bridge for a multiple bus information handling system that optimizes data transfers between a system bus and a peripheral bus
US5396602A (en) * 1993-05-28 1995-03-07 International Business Machines Corp. Arbitration logic for multiple bus computer system
US5623633A (en) * 1993-07-27 1997-04-22 Dell Usa, L.P. Cache-based computer system employing a snoop control circuit with write-back suppression
US5613075A (en) * 1993-11-12 1997-03-18 Intel Corporation Method and apparatus for providing deterministic read access to main memory in a computer system
US5455915A (en) * 1993-12-16 1995-10-03 Intel Corporation Computer system with bridge circuitry having input/output multiplexers and third direct unidirectional path for data transfer between buses operating at different rates
US5559800A (en) * 1994-01-19 1996-09-24 Research In Motion Limited Remote control of gateway functions in a wireless data communication network
US5471590A (en) * 1994-01-28 1995-11-28 Compaq Computer Corp. Bus master arbitration circuitry having improved prioritization
US5535341A (en) * 1994-02-24 1996-07-09 Intel Corporation Apparatus and method for determining the status of data buffers in a bridge between two buses during a flush operation
SG47015A1 (en) * 1994-02-24 1998-03-20 Intel Corp Apparatus and method for prefetching data to load buffers in a bridge between two buses in a computer
US5530933A (en) * 1994-02-24 1996-06-25 Hewlett-Packard Company Multiprocessor system for maintaining cache coherency by checking the coherency in the order of the transactions being issued on the bus
TW400483B (en) * 1994-03-01 2000-08-01 Intel Corp High performance symmetric arbitration protocol with support for I/O requirements
US5528766A (en) * 1994-03-24 1996-06-18 Hewlett-Packard Company Multiple arbitration scheme
US5586297A (en) * 1994-03-24 1996-12-17 Hewlett-Packard Company Partial cache line write transactions in a computing system with a write back cache
US5623700A (en) * 1994-04-06 1997-04-22 Dell, Usa L.P. Interface circuit having zero latency buffer memory and cache memory information transfer
US5535340A (en) * 1994-05-20 1996-07-09 Intel Corporation Method and apparatus for maintaining transaction ordering and supporting deferred replies in a bus bridge
US5546546A (en) * 1994-05-20 1996-08-13 Intel Corporation Method and apparatus for maintaining transaction ordering and arbitrating in a bus bridge
US5687347A (en) * 1994-09-19 1997-11-11 Matsushita Electric Industrial Co., Ltd. Data providing device, file server device, and data transfer control method
US5548730A (en) * 1994-09-20 1996-08-20 Intel Corporation Intelligent bus bridge for input/output subsystems in a computer system
US5524235A (en) * 1994-10-14 1996-06-04 Compaq Computer Corporation System for arbitrating access to memory with dynamic priority assignment
US5553265A (en) * 1994-10-21 1996-09-03 International Business Machines Corporation Methods and system for merging data during cache checking and write-back cycles for memory reads and writes
US5555383A (en) * 1994-11-07 1996-09-10 International Business Machines Corporation Peripheral component interconnect bus system having latency and shadow timers
US5664124A (en) * 1994-11-30 1997-09-02 International Business Machines Corporation Bridge between two buses of a computer system that latches signals from the bus for use on the bridge and responds according to the bus protocols
US5625779A (en) * 1994-12-30 1997-04-29 Intel Corporation Arbitration signaling mechanism to prevent deadlock guarantee access latency, and guarantee acquisition latency for an expansion bridge
US5594882A (en) * 1995-01-04 1997-01-14 Intel Corporation PCI split transactions utilizing dual address cycle
US5568619A (en) * 1995-01-05 1996-10-22 International Business Machines Corporation Method and apparatus for configuring a bus-to-bus bridge
US5630094A (en) * 1995-01-20 1997-05-13 Intel Corporation Integrated bus bridge and memory controller that enables data streaming to a shared memory of a computer system using snoop ahead transactions
US5596729A (en) * 1995-03-03 1997-01-21 Compaq Computer Corporation First arbiter coupled to a first bus receiving requests from devices coupled to a second bus and controlled by a second arbiter on said second bus
US5664150A (en) * 1995-03-21 1997-09-02 International Business Machines Corporation Computer system with a device for selectively blocking writebacks of data from a writeback cache to memory
US5619661A (en) * 1995-06-05 1997-04-08 Vlsi Technology, Inc. Dynamic arbitration system and method
US5634138A (en) * 1995-06-07 1997-05-27 Emulex Corporation Burst broadcasting on a peripheral component interconnect bus
US5694556A (en) * 1995-06-07 1997-12-02 International Business Machines Corporation Data processing system including buffering mechanism for inbound and outbound reads and posted writes
US5710906A (en) * 1995-07-07 1998-01-20 Opti Inc. Predictive snooping of cache memory for master-initiated accesses
US5649175A (en) * 1995-08-10 1997-07-15 Cirrus Logic, Inc. Method and apparatus for acquiring bus transaction address and command information with no more than zero-hold-time and with fast device acknowledgement
US5632021A (en) * 1995-10-25 1997-05-20 Cisco Systems Inc. Computer system with cascaded peripheral component interconnect (PCI) buses
US5673399A (en) * 1995-11-02 1997-09-30 International Business Machines, Corporation System and method for enhancement of system bus to mezzanine bus transactions
US5717876A (en) * 1996-02-26 1998-02-10 International Business Machines Corporation Method for avoiding livelock on bus bridge receiving multiple requests

Also Published As

Publication number Publication date
EP0811925A2 (de) 1997-12-10
JPH1055335A (ja) 1998-02-24
EP0811925A3 (de) 1999-02-10
DE69732736T2 (de) 2005-08-04
EP0811925B1 (de) 2005-03-16
US6052513A (en) 2000-04-18

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Legal Events

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8364 No opposition during term of opposition