DE69724572D1 - Verfahren und Vorrichtung zur Vorladung von verschiedenen vorgegebenen Adressenübersetzungsattributen - Google Patents

Verfahren und Vorrichtung zur Vorladung von verschiedenen vorgegebenen Adressenübersetzungsattributen

Info

Publication number
DE69724572D1
DE69724572D1 DE69724572T DE69724572T DE69724572D1 DE 69724572 D1 DE69724572 D1 DE 69724572D1 DE 69724572 T DE69724572 T DE 69724572T DE 69724572 T DE69724572 T DE 69724572T DE 69724572 D1 DE69724572 D1 DE 69724572D1
Authority
DE
Germany
Prior art keywords
address translation
various predefined
predefined address
translation attributes
preloading
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE69724572T
Other languages
English (en)
Other versions
DE69724572T2 (de
Inventor
Koichi Yamada
Gary N Hammond
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Intel Corp
Original Assignee
Intel Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Intel Corp filed Critical Intel Corp
Application granted granted Critical
Publication of DE69724572D1 publication Critical patent/DE69724572D1/de
Publication of DE69724572T2 publication Critical patent/DE69724572T2/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02Addressing or allocation; Relocation
    • G06F12/08Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/10Address translation
    • G06F12/1027Address translation using associative or pseudo-associative address translation means, e.g. translation look-aside buffer [TLB]
    • G06F12/1036Address translation using associative or pseudo-associative address translation means, e.g. translation look-aside buffer [TLB] for multiple virtual address spaces, e.g. segmentation
    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F2212/00Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
    • G06F2212/65Details of virtual memory and virtual address translation
    • G06F2212/654Look-ahead translation
DE69724572T 1996-12-23 1997-05-23 Verfahren und Vorrichtung zur Vorladung von verschiedenen vorgegebenen Adressenübersetzungsattributen Expired - Lifetime DE69724572T2 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US771845 1985-08-30
US08/771,845 US5918251A (en) 1996-12-23 1996-12-23 Method and apparatus for preloading different default address translation attributes

Publications (2)

Publication Number Publication Date
DE69724572D1 true DE69724572D1 (de) 2003-10-09
DE69724572T2 DE69724572T2 (de) 2004-04-08

Family

ID=25093117

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69724572T Expired - Lifetime DE69724572T2 (de) 1996-12-23 1997-05-23 Verfahren und Vorrichtung zur Vorladung von verschiedenen vorgegebenen Adressenübersetzungsattributen

Country Status (5)

Country Link
US (1) US5918251A (de)
EP (1) EP0851357B1 (de)
JP (1) JP3998787B2 (de)
CN (1) CN1153145C (de)
DE (1) DE69724572T2 (de)

Families Citing this family (79)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6041366A (en) * 1998-02-02 2000-03-21 International Business Machines Corporation System and method for dynamic specification of input/output attributes
US6205531B1 (en) * 1998-07-02 2001-03-20 Silicon Graphics Incorporated Method and apparatus for virtual address translation
US7941647B2 (en) 1999-01-28 2011-05-10 Ati Technologies Ulc Computer for executing two instruction sets and adds a macroinstruction end marker for performing iterations after loop termination
US8127121B2 (en) 1999-01-28 2012-02-28 Ati Technologies Ulc Apparatus for executing programs for a first computer architechture on a computer of a second architechture
US8074055B1 (en) 1999-01-28 2011-12-06 Ati Technologies Ulc Altering data storage conventions of a processor when execution flows from first architecture code to second architecture code
US7275246B1 (en) * 1999-01-28 2007-09-25 Ati International Srl Executing programs for a first computer architecture on a computer of a second architecture
US8121828B2 (en) 1999-01-28 2012-02-21 Ati Technologies Ulc Detecting conditions for transfer of execution from one computer instruction stream to another and executing transfer on satisfaction of the conditions
US6301648B1 (en) * 1999-08-18 2001-10-09 Ati International Srl Method and apparatus for processing memory accesses utilizing a TLB
US6393544B1 (en) * 1999-10-31 2002-05-21 Institute For The Development Of Emerging Architectures, L.L.C. Method and apparatus for calculating a page table index from a virtual address
US6560689B1 (en) * 2000-03-31 2003-05-06 Intel Corporation TLB using region ID prevalidation
US6622225B1 (en) 2000-08-31 2003-09-16 Hewlett-Packard Development Company, L.P. System for minimizing memory bank conflicts in a computer system
US6654858B1 (en) 2000-08-31 2003-11-25 Hewlett-Packard Development Company, L.P. Method for reducing directory writes and latency in a high performance, directory-based, coherency protocol
US6668335B1 (en) 2000-08-31 2003-12-23 Hewlett-Packard Company, L.P. System for recovering data in a multiprocessor system comprising a conduction path for each bit between processors where the paths are grouped into separate bundles and routed along different paths
US7099913B1 (en) 2000-08-31 2006-08-29 Hewlett-Packard Development Company, L.P. Speculative directory writes in a directory based cache coherent nonuniform memory access protocol
US6738836B1 (en) 2000-08-31 2004-05-18 Hewlett-Packard Development Company, L.P. Scalable efficient I/O port protocol
US7213087B1 (en) 2000-08-31 2007-05-01 Hewlett-Packard Development Company, L.P. Mechanism to control the allocation of an N-source shared buffer
US6662265B1 (en) 2000-08-31 2003-12-09 Hewlett-Packard Development Company, L.P. Mechanism to track all open pages in a DRAM memory system
US6779142B1 (en) 2000-08-31 2004-08-17 Hewlett-Packard Development Company, L.P. Apparatus and method for interfacing a high speed scan-path with slow-speed test equipment
US6704817B1 (en) * 2000-08-31 2004-03-09 Hewlett-Packard Development Company, L.P. Computer architecture and system for efficient management of bi-directional bus
US6567900B1 (en) 2000-08-31 2003-05-20 Hewlett-Packard Development Company, L.P. Efficient address interleaving with simultaneous multiple locality options
US6751721B1 (en) * 2000-08-31 2004-06-15 Hewlett-Packard Development Company, L.P. Broadcast invalidate scheme
US6546453B1 (en) 2000-08-31 2003-04-08 Compaq Information Technologies Group, L.P. Proprammable DRAM address mapping mechanism
US6961781B1 (en) 2000-08-31 2005-11-01 Hewlett-Packard Development Company, L.P. Priority rules for reducing network message routing latency
US6715057B1 (en) 2000-08-31 2004-03-30 Hewlett-Packard Development Company, L.P. Efficient translation lookaside buffer miss processing in computer systems with a large range of page sizes
US6633960B1 (en) * 2000-08-31 2003-10-14 Hewlett-Packard Development Company, L.P. Scalable directory based cache coherence protocol
US6681295B1 (en) 2000-08-31 2004-01-20 Hewlett-Packard Development Company, L.P. Fast lane prefetching
US6671822B1 (en) 2000-08-31 2003-12-30 Hewlett-Packard Development Company, L.P. Method and system for absorbing defects in high performance microprocessor with a large n-way set associative cache
US6754739B1 (en) 2000-08-31 2004-06-22 Hewlett-Packard Development Company Computer resource management and allocation system
US6546465B1 (en) 2000-08-31 2003-04-08 Hewlett-Packard Development Company, L.P. Chaining directory reads and writes to reduce DRAM bandwidth in a directory based CC-NUMA protocol
US6678840B1 (en) 2000-08-31 2004-01-13 Hewlett-Packard Development Company, Lp. Fault containment and error recovery in a scalable multiprocessor
US6636955B1 (en) 2000-08-31 2003-10-21 Hewlett-Packard Development Company, L.P. Mechanism for synchronizing multiple skewed source-synchronous data channels with automatic initialization feature
US6662319B1 (en) * 2000-08-31 2003-12-09 Hewlett-Packard Development Company, L.P. Special encoding of known bad data
DE10131124A1 (de) * 2001-06-28 2003-01-23 Infineon Technologies Ag Konfigurierbare Adressierungsvorrichtung
GB2378779B (en) * 2001-08-14 2005-02-02 Advanced Risc Mach Ltd Accessing memory units in a data processing apparatus
US6782446B2 (en) * 2001-08-22 2004-08-24 Intel Corporation Method to prevent corruption of page tables during flash EEPROM programming
US7124273B2 (en) * 2002-02-25 2006-10-17 Intel Corporation Method and apparatus for translating guest physical addresses in a virtual machine environment
US7581010B2 (en) * 2003-07-14 2009-08-25 Microsoft Corporation Virtual connectivity with local connection translation
US20050160229A1 (en) * 2004-01-16 2005-07-21 International Business Machines Corporation Method and apparatus for preloading translation buffers
US7206916B2 (en) * 2004-03-08 2007-04-17 Sun Microsystems, Inc. Partial address compares stored in translation lookaside buffer
JP4233492B2 (ja) * 2004-06-02 2009-03-04 富士通マイクロエレクトロニクス株式会社 アドレス変換装置
US7424584B2 (en) * 2004-08-12 2008-09-09 International Business Machines Corporation Key-controlled object-based memory protection
US7617380B2 (en) * 2005-08-25 2009-11-10 Broadcom Corporation System and method for synchronizing translation lookaside buffer access in a multithread processor
EP2477109B1 (de) 2006-04-12 2016-07-13 Soft Machines, Inc. Vorrichtung und Verfahren zur Verarbeitung einer Anweisungsmatrix zur Spezifizierung von parallelen und abhängigen Betriebsabläufen
US7886112B2 (en) * 2006-05-24 2011-02-08 Sony Computer Entertainment Inc. Methods and apparatus for providing simultaneous software/hardware cache fill
EP2523101B1 (de) 2006-11-14 2014-06-04 Soft Machines, Inc. Vorrichtung und Verfahren zum Verarbeiten von komplexen Anweisungsformaten in einer Multi-Thread-Architektur, die verschiedene Kontextschaltungsmodi und Visualisierungsschemen unterstützt
US8799620B2 (en) * 2007-06-01 2014-08-05 Intel Corporation Linear to physical address translation with support for page attributes
US9244855B2 (en) * 2007-12-31 2016-01-26 Intel Corporation Method, system, and apparatus for page sizing extension
US8533429B2 (en) * 2009-06-24 2013-09-10 Panasonic Corporation Memory access control device, integrated circuit, memory access control method, and data processing device
US8364933B2 (en) * 2009-12-18 2013-01-29 International Business Machines Corporation Software assisted translation lookaside buffer search mechanism
US8694755B1 (en) * 2010-03-17 2014-04-08 Ambarella, Inc. Virtual memory management for real-time embedded devices
EP2616928B1 (de) 2010-09-17 2016-11-02 Soft Machines, Inc. Mehrfach verzweigte einzelzyklus-vorhersage mit einem latenten cache für frühe und entfernte verzweigungsvorhersage
WO2012135041A2 (en) 2011-03-25 2012-10-04 Soft Machines, Inc. Register file segments for supporting code block execution by using virtual cores instantiated by partitionable engines
WO2012135031A2 (en) 2011-03-25 2012-10-04 Soft Machines, Inc. Executing instruction sequence code blocks by using virtual cores instantiated by partitionable engines
EP2689326B1 (de) 2011-03-25 2022-11-16 Intel Corporation Speicherfragmente zur unterstützung einer codeblockausführung mittels durch partitionierbare engines realisierter virtueller kerne
CN103649932B (zh) 2011-05-20 2017-09-26 英特尔公司 资源的分散分配以及用于支持由多个引擎执行指令序列的互连结构
WO2012162189A1 (en) 2011-05-20 2012-11-29 Soft Machines, Inc. An interconnect structure to support the execution of instruction sequences by a plurality of engines
US20150039859A1 (en) 2011-11-22 2015-02-05 Soft Machines, Inc. Microprocessor accelerated code optimizer
KR101703401B1 (ko) 2011-11-22 2017-02-06 소프트 머신즈, 인크. 다중 엔진 마이크로프로세서용 가속 코드 최적화기
US9378150B2 (en) * 2012-02-28 2016-06-28 Apple Inc. Memory management unit with prefetch ability
US8930674B2 (en) 2012-03-07 2015-01-06 Soft Machines, Inc. Systems and methods for accessing a unified translation lookaside buffer
US9430410B2 (en) 2012-07-30 2016-08-30 Soft Machines, Inc. Systems and methods for supporting a plurality of load accesses of a cache in a single cycle
US9740612B2 (en) 2012-07-30 2017-08-22 Intel Corporation Systems and methods for maintaining the coherency of a store coalescing cache and a load cache
US9916253B2 (en) 2012-07-30 2018-03-13 Intel Corporation Method and apparatus for supporting a plurality of load accesses of a cache in a single cycle to maintain throughput
US9229873B2 (en) 2012-07-30 2016-01-05 Soft Machines, Inc. Systems and methods for supporting a plurality of load and store accesses of a cache
US9710399B2 (en) 2012-07-30 2017-07-18 Intel Corporation Systems and methods for flushing a cache with modified data
US9678882B2 (en) 2012-10-11 2017-06-13 Intel Corporation Systems and methods for non-blocking implementation of cache flush instructions
CN103116555B (zh) * 2013-03-05 2014-03-05 中国人民解放军国防科学技术大学 基于多体并行缓存结构的数据访问方法
US9904625B2 (en) 2013-03-15 2018-02-27 Intel Corporation Methods, systems and apparatus for predicting the way of a set associative cache
US9891924B2 (en) 2013-03-15 2018-02-13 Intel Corporation Method for implementing a reduced size register view data structure in a microprocessor
KR102083390B1 (ko) 2013-03-15 2020-03-02 인텔 코포레이션 네이티브 분산된 플래그 아키텍처를 이용하여 게스트 중앙 플래그 아키텍처를 에뮬레이션하는 방법
WO2014150806A1 (en) 2013-03-15 2014-09-25 Soft Machines, Inc. A method for populating register view data structure by using register template snapshots
US10275255B2 (en) 2013-03-15 2019-04-30 Intel Corporation Method for dependency broadcasting through a source organized source view data structure
WO2014150991A1 (en) 2013-03-15 2014-09-25 Soft Machines, Inc. A method for implementing a reduced size register view data structure in a microprocessor
US10140138B2 (en) 2013-03-15 2018-11-27 Intel Corporation Methods, systems and apparatus for supporting wide and efficient front-end operation with guest-architecture emulation
US9569216B2 (en) 2013-03-15 2017-02-14 Soft Machines, Inc. Method for populating a source view data structure by using register template snapshots
US9811342B2 (en) 2013-03-15 2017-11-07 Intel Corporation Method for performing dual dispatch of blocks and half blocks
US9886279B2 (en) 2013-03-15 2018-02-06 Intel Corporation Method for populating and instruction view data structure by using register template snapshots
KR102063656B1 (ko) 2013-03-15 2020-01-09 소프트 머신즈, 인크. 블록들로 그룹화된 멀티스레드 명령어들을 실행하기 위한 방법
WO2014150971A1 (en) 2013-03-15 2014-09-25 Soft Machines, Inc. A method for dependency broadcasting through a block organized source view data structure

Family Cites Families (22)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0175398A3 (de) * 1984-08-17 1989-08-30 Koninklijke Philips Electronics N.V. Datenverarbeitungsanordnung mit einem Speicherzugriffssteuergerät welches zur Kombination von Deskriptor-Bits aus verschiedenen mit virtuellen Adressen verbundenen Deskriptoren vorgesehen ist
US5060137A (en) * 1985-06-28 1991-10-22 Hewlett-Packard Company Explicit instructions for control of translation lookaside buffers
US4774659A (en) * 1986-04-16 1988-09-27 Astronautics Corporation Of America Computer system employing virtual memory
US4881075A (en) * 1987-10-15 1989-11-14 Digital Equipment Corporation Method and apparatus for adaptive data compression
US4980816A (en) * 1987-12-18 1990-12-25 Nec Corporation Translation look-aside buffer control system with multiple prioritized buffers
US5179674A (en) * 1988-07-25 1993-01-12 Digital Equipment Corporation Method and apparatus for predicting valid performance of virtual-address to physical-address translations
US5058003A (en) * 1988-12-15 1991-10-15 International Business Machines Corporation Virtual storage dynamic address translation mechanism for multiple-sized pages
JPH02205953A (ja) * 1989-02-03 1990-08-15 Nec Corp アドレス変換装置
US5307477A (en) * 1989-12-01 1994-04-26 Mips Computer Systems, Inc. Two-level cache memory system
US5412787A (en) * 1990-11-21 1995-05-02 Hewlett-Packard Company Two-level TLB having the second level TLB implemented in cache tag RAMs
EP0506236A1 (de) * 1991-03-13 1992-09-30 International Business Machines Corporation Adressübersetzungseinrichtung
RU1804645C (ru) * 1991-03-27 1993-03-23 Институт Точной Механики И Вычислительной Техники Им.С.А.Лебедева Центральный процессор
US5278963A (en) * 1991-06-21 1994-01-11 International Business Machines Corporation Pretranslation of virtual addresses prior to page crossing
US5465337A (en) * 1992-08-13 1995-11-07 Sun Microsystems, Inc. Method and apparatus for a memory management unit supporting multiple page sizes
US5493660A (en) * 1992-10-06 1996-02-20 Hewlett-Packard Company Software assisted hardware TLB miss handler
US5442766A (en) * 1992-10-09 1995-08-15 International Business Machines Corporation Method and system for distributed instruction address translation in a multiscalar data processing system
US5479627A (en) * 1993-09-08 1995-12-26 Sun Microsystems, Inc. Virtual address to physical address translation cache that supports multiple page sizes
US5526504A (en) * 1993-12-15 1996-06-11 Silicon Graphics, Inc. Variable page size translation lookaside buffer
US5561814A (en) * 1993-12-22 1996-10-01 Intel Corporation Methods and apparatus for determining memory operating characteristics for given memory locations via assigned address ranges
US5652872A (en) * 1994-03-08 1997-07-29 Exponential Technology, Inc. Translator having segment bounds encoding for storage in a TLB
JP3740195B2 (ja) * 1994-09-09 2006-02-01 株式会社ルネサステクノロジ データ処理装置
US5809563A (en) * 1996-11-12 1998-09-15 Institute For The Development Of Emerging Architectures, Llc Method and apparatus utilizing a region based page table walk bit

Also Published As

Publication number Publication date
EP0851357B1 (de) 2003-09-03
US5918251A (en) 1999-06-29
DE69724572T2 (de) 2004-04-08
EP0851357A1 (de) 1998-07-01
JP3998787B2 (ja) 2007-10-31
CN1153145C (zh) 2004-06-09
CN1192009A (zh) 1998-09-02
JPH10228419A (ja) 1998-08-25

Similar Documents

Publication Publication Date Title
DE69724572D1 (de) Verfahren und Vorrichtung zur Vorladung von verschiedenen vorgegebenen Adressenübersetzungsattributen
DE69323863D1 (de) Verfahren und Vorrichtung zur Adressübersetzung
DE69732853D1 (de) Verfahren und vorrichtung zur zuordnung von ip-adressen
DE69907878D1 (de) Verfahren und vorrichtung zur elektrokoagulation von flüssigkeiten
DE69732447D1 (de) Verfahren und Vorrichtung zur Wiedergabe von schriftartfreien, strukturierten Dokumenten
DE69737115D1 (de) Verfahren und Vorrichtung zur Wiedergabe von schriftartfreien, strukturierten Dokumenten
DE69827656D1 (de) Vorrichtung und verfahren zur bestueckung von bauteilen
DE59707814D1 (de) Verfahren und vorrichtung zur verteilung von sendungen
DE69739437D1 (de) Vorrichtung und Verfahren zur Texteingabe
DE69736655D1 (de) Vorrichtung und Verfahren zur Texteingabe
DE69822687D1 (de) Vorrichtung und Verfahren zur Zusammenfassung
DE69718628T2 (de) Vorrichtung und verfahren zur reduktion von gleichkanalstörungen
DE69940804D1 (de) Verfahren und vorrichtung zur unterdrückung von abklingartefakten
DE69812098D1 (de) Verfahren und vorrichtung zur verwaltung von hash-codierten objekten
DE69803160T2 (de) Verfahren und vorrichtung zur bestückung von elektronischen bauteilen
DE69700993T2 (de) Verfahren und vorrichtung zur befestigung von bauelementen
DE69719477T2 (de) Vorrichtung und Verfahren zur Eingabe von Buchstaben
DE69719784D1 (de) Vorrichtung und verfahren zur markierung von defekten
DE69719208T2 (de) Verfahren und vorrichtung zur veränderung von datentabellen
DE69720262D1 (de) Vorrichtung und verfahren zur handhabung von rohren
DE69705679T2 (de) Verfahren und Vorrichtung zur Trocknung von flachen Gegenständen
ATA49098A (de) Verfahren und vorrichtung zur entstörung von umrichtern
DE69702054D1 (de) Verfahren zur zuführung von bauteilen und vorrichtung
DE69424292D1 (de) Verfahren und vorrichtung zur übertragung von videotextseiten
DE69732180D1 (de) Verfahren und vorrichtung zur bestückung von elektronischen bauelementen

Legal Events

Date Code Title Description
8364 No opposition during term of opposition