DE69719221T2 - Skalierbarer doppelparalleler digitaler signalprozessor - Google Patents

Skalierbarer doppelparalleler digitaler signalprozessor

Info

Publication number
DE69719221T2
DE69719221T2 DE69719221T DE69719221T DE69719221T2 DE 69719221 T2 DE69719221 T2 DE 69719221T2 DE 69719221 T DE69719221 T DE 69719221T DE 69719221 T DE69719221 T DE 69719221T DE 69719221 T2 DE69719221 T2 DE 69719221T2
Authority
DE
Germany
Prior art keywords
digital signal
signal processor
parallel digital
scalable double
scalable
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE69719221T
Other languages
English (en)
Other versions
DE69719221D1 (de
Inventor
Harold Blount
Alexander Tulai
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Microsemi Semiconductor ULC
Original Assignee
Zarlink Semoconductor Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Zarlink Semoconductor Inc filed Critical Zarlink Semoconductor Inc
Application granted granted Critical
Publication of DE69719221D1 publication Critical patent/DE69719221D1/de
Publication of DE69719221T2 publication Critical patent/DE69719221T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30003—Arrangements for executing specific machine instructions
    • G06F9/30007—Arrangements for executing specific machine instructions to perform operations on data operands
    • G06F9/30036—Instructions to perform operations on packed data, e.g. vector, tile or matrix operations
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00—Digital computers in general; Data processing equipment in general
    • G06F15/76—Architectures of general purpose stored program computers
    • G06F15/80—Architectures of general purpose stored program computers comprising an array of processing units with common control, e.g. single instruction multiple data processors
    • G06F15/8007—Architectures of general purpose stored program computers comprising an array of processing units with common control, e.g. single instruction multiple data processors single instruction multiple data [SIMD] multiprocessors
    • G06F15/8015—One dimensional arrays, e.g. rings, linear arrays, buses
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30094—Condition code generation, e.g. Carry, Zero flag
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline, look ahead
    • G06F9/3877—Concurrent instruction execution, e.g. pipeline, look ahead using a slave processor, e.g. coprocessor
    • G06F9/3879—Concurrent instruction execution, e.g. pipeline, look ahead using a slave processor, e.g. coprocessor for non-native instruction execution, e.g. executing a command; for Java instruction set
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline, look ahead
    • G06F9/3877—Concurrent instruction execution, e.g. pipeline, look ahead using a slave processor, e.g. coprocessor
    • G06F9/3879—Concurrent instruction execution, e.g. pipeline, look ahead using a slave processor, e.g. coprocessor for non-native instruction execution, e.g. executing a command; for Java instruction set
    • G06F9/3881—Arrangements for communication of instructions and data
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline, look ahead
    • G06F9/3885—Concurrent instruction execution, e.g. pipeline, look ahead using a plurality of independent parallel functional units
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline, look ahead
    • G06F9/3885—Concurrent instruction execution, e.g. pipeline, look ahead using a plurality of independent parallel functional units
    • G06F9/3887—Concurrent instruction execution, e.g. pipeline, look ahead using a plurality of independent parallel functional units controlled by a single instruction for multiple data lanes [SIMD]
DE69719221T 1996-03-11 1997-03-10 Skalierbarer doppelparalleler digitaler signalprozessor Expired - Fee Related DE69719221T2 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US08/613,331 US5960209A (en) 1996-03-11 1996-03-11 Scaleable digital signal processor with parallel architecture
PCT/CA1997/000164 WO1997034226A1 (en) 1996-03-11 1997-03-10 Scaleable double parallel digital signal processor

Publications (2)

Publication Number Publication Date
DE69719221D1 DE69719221D1 (de) 2003-03-27
DE69719221T2 true DE69719221T2 (de) 2003-12-18

Family

ID=24456885

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69719221T Expired - Fee Related DE69719221T2 (de) 1996-03-11 1997-03-10 Skalierbarer doppelparalleler digitaler signalprozessor

Country Status (5)

Country Link
US (1) US5960209A (de)
EP (1) EP0976037B1 (de)
CA (1) CA2248711A1 (de)
DE (1) DE69719221T2 (de)
WO (1) WO1997034226A1 (de)

Families Citing this family (17)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0992895A1 (de) * 1998-10-06 2000-04-12 Texas Instruments Inc. Hardwarebeschleuniger für Datenbearbeitungssystem
JP3667585B2 (ja) * 2000-02-23 2005-07-06 エヌイーシーコンピュータテクノ株式会社 分散メモリ型並列計算機及びそのデータ転送終了確認方法
US6865663B2 (en) * 2000-02-24 2005-03-08 Pts Corporation Control processor dynamically loading shadow instruction register associated with memory entry of coprocessor in flexible coupling mode
US7047196B2 (en) 2000-06-08 2006-05-16 Agiletv Corporation System and method of voice recognition near a wireline node of a network supporting cable television and/or video delivery
AU2001222161A1 (en) * 2000-07-28 2002-02-13 Delvalley Limited A data processor
DE10059026A1 (de) * 2000-11-28 2002-06-13 Infineon Technologies Ag Einheit zur Verteilung und Verarbeitung von Datenpaketen
US8095370B2 (en) 2001-02-16 2012-01-10 Agiletv Corporation Dual compression voice recordation non-repudiation system
US6886092B1 (en) * 2001-11-19 2005-04-26 Xilinx, Inc. Custom code processing in PGA by providing instructions from fixed logic processor portion to programmable dedicated processor portion
DE10256586A1 (de) * 2002-12-04 2004-06-17 Philips Intellectual Property & Standards Gmbh Datenverarbeitungseinrichtung mit Mikroprozessor und mit zusätzlicher Recheneinheit sowie zugeordnetes Verfahren
JP2005078177A (ja) * 2003-08-28 2005-03-24 Nec Electronics Corp 並列演算装置
WO2005103922A2 (en) * 2004-03-26 2005-11-03 Atmel Corporation Dual-processor complex domain floating-point dsp system on chip
ITMI20040600A1 (it) * 2004-03-26 2004-06-26 Atmel Corp Sistema dsp su chip a doppio processore a virgola mobile nel dominio complesso
US20070300042A1 (en) * 2006-06-27 2007-12-27 Moyer William C Method and apparatus for interfacing a processor and coprocessor
US7925862B2 (en) * 2006-06-27 2011-04-12 Freescale Semiconductor, Inc. Coprocessor forwarding load and store instructions with displacement to main processor for cache coherent execution when program counter value falls within predetermined ranges
US7805590B2 (en) * 2006-06-27 2010-09-28 Freescale Semiconductor, Inc. Coprocessor receiving target address to process a function and to send data transfer instructions to main processor for execution to preserve cache coherence
US20080235493A1 (en) * 2007-03-23 2008-09-25 Qualcomm Incorporated Instruction communication techniques for multi-processor system
US8938590B2 (en) * 2008-10-18 2015-01-20 Micron Technology, Inc. Indirect register access method and system

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4862407A (en) * 1987-10-05 1989-08-29 Motorola, Inc. Digital signal processing apparatus
US5239654A (en) * 1989-11-17 1993-08-24 Texas Instruments Incorporated Dual mode SIMD/MIMD processor providing reuse of MIMD instruction memories as data memories when operating in SIMD mode
US5187791A (en) * 1990-01-26 1993-02-16 Apple Computer, Inc. Microprocessor with improved interrupt response with data saving dependent upon processor status using status flag
US5189598A (en) * 1990-08-14 1993-02-23 Dallas Semiconductor Corporation Dual function microboard with a row of connectors on two edges
GB9019025D0 (en) * 1990-08-31 1990-10-17 Ncr Co Work station having multiprocessing capability
US5488693A (en) * 1992-06-24 1996-01-30 At&T Corp. Protocol with control bits and bytes for controlling the order of communications between a master processor and plural slave processors
WO1994027216A1 (en) * 1993-05-14 1994-11-24 Massachusetts Institute Of Technology Multiprocessor coupling system with integrated compile and run time scheduling for parallelism

Also Published As

Publication number Publication date
CA2248711A1 (en) 1997-09-18
EP0976037B1 (de) 2003-02-19
EP0976037A1 (de) 2000-02-02
DE69719221D1 (de) 2003-03-27
WO1997034226A1 (en) 1997-09-18
US5960209A (en) 1999-09-28

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee