DE69709172T2 - Optimierte lötverbindungen für oberflächenmontierte chips - Google Patents

Optimierte lötverbindungen für oberflächenmontierte chips

Info

Publication number
DE69709172T2
DE69709172T2 DE69709172T DE69709172T DE69709172T2 DE 69709172 T2 DE69709172 T2 DE 69709172T2 DE 69709172 T DE69709172 T DE 69709172T DE 69709172 T DE69709172 T DE 69709172T DE 69709172 T2 DE69709172 T2 DE 69709172T2
Authority
DE
Germany
Prior art keywords
surface mounted
soldering connections
mounted chips
optimized
optimized soldering
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE69709172T
Other languages
English (en)
Other versions
DE69709172D1 (de
Inventor
Keith Mcmillan
Amir Jairazbhoy
Yi-Hsin Pao
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Ford Global Technologies LLC
Original Assignee
Ford Global Technologies LLC
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Ford Global Technologies LLC filed Critical Ford Global Technologies LLC
Publication of DE69709172D1 publication Critical patent/DE69709172D1/de
Application granted granted Critical
Publication of DE69709172T2 publication Critical patent/DE69709172T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/30Assembling printed circuits with electric components, e.g. with resistor
    • H05K3/32Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
    • H05K3/34Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
    • H05K3/341Surface mounted components
    • H05K3/3431Leadless components
    • H05K3/3442Leadless components having edge contacts, e.g. leadless chip capacitors, chip carriers
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09Shape and layout
    • H05K2201/09209Shape and layout details of conductors
    • H05K2201/09372Pads and lands
    • H05K2201/09427Special relation between the location or dimension of a pad or land and the location or dimension of a terminal
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09Shape and layout
    • H05K2201/09209Shape and layout details of conductors
    • H05K2201/09654Shape and layout details of conductors covering at least two types of conductors provided for in H05K2201/09218 - H05K2201/095
    • H05K2201/09781Dummy conductors, i.e. not used for normal transport of current; Dummy electrodes of components
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/10Details of components or other objects attached to or integrated in a printed circuit board
    • H05K2201/10613Details of electrical connections of non-printed components, e.g. special leads
    • H05K2201/10621Components characterised by their electrical contacts
    • H05K2201/10636Leadless chip, e.g. chip capacitor or resistor
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2203/00Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
    • H05K2203/04Soldering or other types of metallurgic bonding
    • H05K2203/0465Shape of solder, e.g. differing from spherical shape, different shapes due to different solder pads
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2203/00Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
    • H05K2203/30Details of processes not otherwise provided for in H05K2203/01 - H05K2203/17
    • H05K2203/306Lifting the component during or after mounting; Increasing the gap between component and PCB
    • YGENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02PCLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
    • Y02P70/00Climate change mitigation technologies in the production process for final industrial or consumer products
    • Y02P70/50Manufacturing or production processes characterised by the final manufactured product
DE69709172T 1997-01-16 1997-12-29 Optimierte lötverbindungen für oberflächenmontierte chips Expired - Fee Related DE69709172T2 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US08/786,389 US5936846A (en) 1997-01-16 1997-01-16 Optimized solder joints and lifter pads for improving the solder joint life of surface mount chips
PCT/IB1997/001602 WO1998032314A2 (en) 1997-01-16 1997-12-29 Solder joints for surface mount chips

Publications (2)

Publication Number Publication Date
DE69709172D1 DE69709172D1 (de) 2002-01-24
DE69709172T2 true DE69709172T2 (de) 2002-05-02

Family

ID=25138437

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69709172T Expired - Fee Related DE69709172T2 (de) 1997-01-16 1997-12-29 Optimierte lötverbindungen für oberflächenmontierte chips

Country Status (10)

Country Link
US (1) US5936846A (de)
EP (1) EP0953277B1 (de)
JP (1) JP2001508949A (de)
CN (1) CN1245007A (de)
BR (1) BR9714289A (de)
CA (1) CA2278019A1 (de)
DE (1) DE69709172T2 (de)
ES (1) ES2167797T3 (de)
PT (1) PT953277E (de)
WO (1) WO1998032314A2 (de)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE102009060060A1 (de) * 2009-12-22 2011-06-30 Rohde & Schwarz GmbH & Co. KG, 81671 Halteelement zur unverlierbaren Montage einer Schraube

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EP1014767A1 (de) * 1998-12-23 2000-06-28 Lucent Technologies Inc. Entlastung thermischer Spannungen für oberflächenmontierte Bauelemente unter Verwendung der Füllung von Durchgangslöchern
KR100843737B1 (ko) * 2002-05-10 2008-07-04 페어차일드코리아반도체 주식회사 솔더 조인트의 신뢰성이 개선된 반도체 패키지
US7049051B2 (en) * 2003-01-23 2006-05-23 Akustica, Inc. Process for forming and acoustically connecting structures on a substrate
TWI243462B (en) * 2004-05-14 2005-11-11 Advanced Semiconductor Eng Semiconductor package including passive component
JP4557676B2 (ja) * 2004-10-27 2010-10-06 京セラ株式会社 半導体装置の実装構造
DE102005017527A1 (de) * 2005-04-15 2006-11-02 Osram Opto Semiconductors Gmbh Oberflächenmontierbares optoelektronisches Bauelement
DE102006054085A1 (de) * 2006-11-16 2008-05-29 Epcos Ag Bauelement-Anordnung
US7893545B2 (en) * 2007-07-18 2011-02-22 Infineon Technologies Ag Semiconductor device
US7830022B2 (en) * 2007-10-22 2010-11-09 Infineon Technologies Ag Semiconductor package
US8399995B2 (en) * 2009-01-16 2013-03-19 Infineon Technologies Ag Semiconductor device including single circuit element for soldering
JP5552882B2 (ja) * 2010-04-26 2014-07-16 株式会社デンソー 表面実装型半導体パッケージの実装構造
JP5389748B2 (ja) * 2010-06-18 2014-01-15 日本メクトロン株式会社 電子部品の表面実装方法、及び該方法を用いて作製されたプリント回路板
US8604356B1 (en) * 2010-11-12 2013-12-10 Amkor Technology, Inc. Electronic assembly having increased standoff height
CN102522347B (zh) * 2011-12-23 2015-04-29 清华大学 一种制备焊料凸块的方法
JP2014110370A (ja) * 2012-12-04 2014-06-12 Seiko Epson Corp ベース基板、実装構造体、モジュール、電子機器、および移動体
JP5646021B2 (ja) * 2012-12-18 2014-12-24 積水化学工業株式会社 半導体パッケージ
US9622356B2 (en) * 2013-03-14 2017-04-11 Lockheed Martin Corporation Electronic package mounting
US9237655B1 (en) 2013-03-15 2016-01-12 Lockheed Martin Corporation Material deposition on circuit card assemblies
AT515071B1 (de) * 2013-09-03 2019-03-15 Zkw Group Gmbh Verfahren zum positionsstabilen Verlöten
JP6481446B2 (ja) * 2014-06-13 2019-03-13 株式会社村田製作所 積層コンデンサの実装構造体
US9634053B2 (en) * 2014-12-09 2017-04-25 Taiwan Semiconductor Manufacturing Co., Ltd. Image sensor chip sidewall interconnection
CN113694796B (zh) * 2021-10-14 2022-02-08 深圳市澳华集团股份有限公司 一种肠道免疫增强剂生产用溶解装置及其使用方法
US11839031B2 (en) * 2022-04-06 2023-12-05 Western Digital Technologies, Inc. Micro solder joint and stencil aperture design

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DE3536431A1 (de) * 1985-10-12 1987-04-16 Standard Elektrik Lorenz Ag Loeten von oberflaechenmontierbaren bauelementen
DE3684602D1 (de) * 1986-10-08 1992-04-30 Ibm Verfahren zum herstellen von loetkontakten fuer ein keramisches modul ohne steckerstifte.
US4749120A (en) * 1986-12-18 1988-06-07 Matsushita Electric Industrial Co., Ltd. Method of connecting a semiconductor device to a wiring board
US4760948A (en) * 1986-12-23 1988-08-02 Rca Corporation Leadless chip carrier assembly and method
DE3810653C1 (de) * 1988-03-29 1989-05-18 Dieter Dr.-Ing. Friedrich
JPH01251789A (ja) * 1988-03-31 1989-10-06 Toshiba Corp プリント基板
JP2761113B2 (ja) * 1991-02-25 1998-06-04 松下電工株式会社 プリント配線板
DE4137045A1 (de) * 1991-11-11 1993-05-13 Siemens Ag Verfahren zur herstellung von lotflaechen auf einer leiterplatte und lotpastenfolie zur durchfuehrung des verfahrens
US5315070A (en) * 1991-12-02 1994-05-24 Siemens Aktiengesellschaft Printed wiring board to which solder has been applied
CA2089435C (en) * 1992-02-14 1997-12-09 Kenzi Kobayashi Semiconductor device
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GB9302228D0 (en) * 1993-02-05 1993-03-24 Ncr Int Inc Method of forming discrete solder portions on respective contact pads of a printed circuit board
JP3152834B2 (ja) * 1993-06-24 2001-04-03 株式会社東芝 電子回路装置
US5400950A (en) * 1994-02-22 1995-03-28 Delco Electronics Corporation Method for controlling solder bump height for flip chip integrated circuit devices
US5639013A (en) * 1994-12-23 1997-06-17 Ford Motor Company Optimally shaped solder joints for improved reliability and space savings
US5726861A (en) * 1995-01-03 1998-03-10 Ostrem; Fred E. Surface mount component height control

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE102009060060A1 (de) * 2009-12-22 2011-06-30 Rohde & Schwarz GmbH & Co. KG, 81671 Halteelement zur unverlierbaren Montage einer Schraube

Also Published As

Publication number Publication date
DE69709172D1 (de) 2002-01-24
JP2001508949A (ja) 2001-07-03
EP0953277A2 (de) 1999-11-03
WO1998032314A3 (en) 1999-06-03
WO1998032314A2 (en) 1998-07-23
CN1245007A (zh) 2000-02-16
US5936846A (en) 1999-08-10
CA2278019A1 (en) 1998-07-23
BR9714289A (pt) 2000-04-25
ES2167797T3 (es) 2002-05-16
PT953277E (pt) 2002-06-28
EP0953277B1 (de) 2001-12-12

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8327 Change in the person/name/address of the patent owner

Owner name: FORD GLOBAL TECHNOLOGIES, LLC (N.D.GES.D. STAATES

8339 Ceased/non-payment of the annual fee