DE69706910T2 - Herstellungsverfahren einer T-förmigen Gate-Elektrode in einem Halbleiterbauelement, und die T-förmige Gate-Elektrode - Google Patents

Herstellungsverfahren einer T-förmigen Gate-Elektrode in einem Halbleiterbauelement, und die T-förmige Gate-Elektrode

Info

Publication number
DE69706910T2
DE69706910T2 DE69706910T DE69706910T DE69706910T2 DE 69706910 T2 DE69706910 T2 DE 69706910T2 DE 69706910 T DE69706910 T DE 69706910T DE 69706910 T DE69706910 T DE 69706910T DE 69706910 T2 DE69706910 T2 DE 69706910T2
Authority
DE
Germany
Prior art keywords
gate electrode
shaped gate
manufacturing
semiconductor device
shaped
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE69706910T
Other languages
English (en)
Other versions
DE69706910D1 (de
Inventor
Hidehiko Sasaki
Yasushi Yokoi
Koji Monden
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Murata Manufacturing Co Ltd
Original Assignee
Murata Manufacturing Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Murata Manufacturing Co Ltd filed Critical Murata Manufacturing Co Ltd
Application granted granted Critical
Publication of DE69706910D1 publication Critical patent/DE69706910D1/de
Publication of DE69706910T2 publication Critical patent/DE69706910T2/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66848—Unipolar field-effect transistors with a Schottky gate, i.e. MESFET
    • H01L29/66856—Unipolar field-effect transistors with a Schottky gate, i.e. MESFET with an active layer made of a group 13/15 material
    • H01L29/66863—Lateral single gate transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
    • H01L21/0271—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers
    • H01L21/0272—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers for lift-off processes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
    • H01L21/285—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation
    • H01L21/28506—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers
    • H01L21/28575—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising AIIIBV compounds
    • H01L21/28581—Deposition of Schottky electrodes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
    • H01L21/285—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation
    • H01L21/28506—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers
    • H01L21/28575—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising AIIIBV compounds
    • H01L21/28587—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising AIIIBV compounds characterised by the sectional shape, e.g. T, inverted T
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S438/00—Semiconductor device manufacturing: process
    • Y10S438/942—Masking
    • Y10S438/948—Radiation resist
    • Y10S438/949—Energy beam treating radiation resist on semiconductor
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S438/00—Semiconductor device manufacturing: process
    • Y10S438/942—Masking
    • Y10S438/948—Radiation resist
    • Y10S438/951—Lift-off
DE69706910T 1996-04-10 1997-04-04 Herstellungsverfahren einer T-förmigen Gate-Elektrode in einem Halbleiterbauelement, und die T-förmige Gate-Elektrode Expired - Lifetime DE69706910T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP8088010A JPH09283621A (ja) 1996-04-10 1996-04-10 半導体装置のｔ型ゲート電極形成方法およびその構造

Publications (2)

Publication Number Publication Date
DE69706910D1 DE69706910D1 (de) 2001-10-31
DE69706910T2 true DE69706910T2 (de) 2002-03-28

Family

ID=13930864

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69706910T Expired - Lifetime DE69706910T2 (de) 1996-04-10 1997-04-04 Herstellungsverfahren einer T-förmigen Gate-Elektrode in einem Halbleiterbauelement, und die T-förmige Gate-Elektrode

Country Status (5)

Country Link
US (1) US5804474A (de)
EP (1) EP0801418B1 (de)
JP (1) JPH09283621A (de)
KR (1) KR100239994B1 (de)
DE (1) DE69706910T2 (de)

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EP1303792B1 (de) 2000-07-16 2012-10-03 Board Of Regents, The University Of Texas System Hoch auflösende ausrichtungsverfahren und entsprechende systeme für die präge-lithographie
EP2270592B1 (de) 2000-07-17 2015-09-02 Board of Regents, The University of Texas System Verfahren zur Bildung einer Struktur auf einem Substrat
US6524937B1 (en) * 2000-08-23 2003-02-25 Tyco Electronics Corp. Selective T-gate process
JP2004523906A (ja) * 2000-10-12 2004-08-05 ボード・オブ・リージエンツ，ザ・ユニバーシテイ・オブ・テキサス・システム 室温かつ低圧マイクロおよびナノ転写リソグラフィのためのテンプレート
JP2003240997A (ja) * 2002-02-21 2003-08-27 Fujitsu Ltd 空間反射型構造を有する光集積回路の製造方法
JP3742030B2 (ja) 2002-04-23 2006-02-01 富士通株式会社 平面光導波回路デバイスの製造方法
US7077992B2 (en) 2002-07-11 2006-07-18 Molecular Imprints, Inc. Step and repeat imprint lithography processes
US6932934B2 (en) * 2002-07-11 2005-08-23 Molecular Imprints, Inc. Formation of discontinuous films during an imprint lithography process
US8349241B2 (en) 2002-10-04 2013-01-08 Molecular Imprints, Inc. Method to arrange features on a substrate to replicate features having minimal dimensional variability
US6871558B2 (en) 2002-12-12 2005-03-29 Molecular Imprints, Inc. Method for determining characteristics of substrate employing fluid geometries
US7906180B2 (en) * 2004-02-27 2011-03-15 Molecular Imprints, Inc. Composition for an etching mask comprising a silicon-containing material
US7803308B2 (en) 2005-12-01 2010-09-28 Molecular Imprints, Inc. Technique for separating a mold from solidified imprinting material
US7906058B2 (en) 2005-12-01 2011-03-15 Molecular Imprints, Inc. Bifurcated contact printing technique
MY144847A (en) 2005-12-08 2011-11-30 Molecular Imprints Inc Method and system for double-sided patterning of substrates
US7670530B2 (en) 2006-01-20 2010-03-02 Molecular Imprints, Inc. Patterning substrates employing multiple chucks
US7802978B2 (en) 2006-04-03 2010-09-28 Molecular Imprints, Inc. Imprinting of partial fields at the edge of the wafer
US8142850B2 (en) 2006-04-03 2012-03-27 Molecular Imprints, Inc. Patterning a plurality of fields on a substrate to compensate for differing evaporation times
US8850980B2 (en) 2006-04-03 2014-10-07 Canon Nanotechnologies, Inc. Tessellated patterns in imprint lithography
JP5306989B2 (ja) 2006-04-03 2013-10-02 モレキュラー・インプリンツ・インコーポレーテッド 複数のフィールド及びアライメント・マークを有する基板を同時にパターニングする方法
US7547398B2 (en) 2006-04-18 2009-06-16 Molecular Imprints, Inc. Self-aligned process for fabricating imprint templates containing variously etched features
US8012395B2 (en) 2006-04-18 2011-09-06 Molecular Imprints, Inc. Template having alignment marks formed of contrast material
JP2010067692A (ja) * 2008-09-09 2010-03-25 Toshiba Corp 半導体装置及び半導体装置の製造方法
KR20110133828A (ko) * 2010-06-07 2011-12-14 삼성전자주식회사 포토레지스트 패턴 형성 방법
JP2013258368A (ja) * 2012-06-14 2013-12-26 Toshiba Corp 半導体装置
US11682721B2 (en) * 2021-01-20 2023-06-20 Raytheon Company Asymmetrically angled gate structure and method for making same
US11881506B2 (en) * 2021-07-27 2024-01-23 Globalfoundries U.S. Inc. Gate structures with air gap isolation features

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US4253888A (en) * 1978-06-16 1981-03-03 Matsushita Electric Industrial Co., Ltd. Pretreatment of photoresist masking layers resulting in higher temperature device processing
US4497684A (en) * 1983-02-22 1985-02-05 Amdahl Corporation Lift-off process for depositing metal on a substrate
JPS63137481A (ja) * 1986-11-28 1988-06-09 Nec Corp 半導体装置の製造方法
US5171718A (en) * 1987-11-27 1992-12-15 Sony Corporation Method for forming a fine pattern by using a patterned resist layer
JPH07111966B2 (ja) * 1989-12-22 1995-11-29 株式会社東芝 半導体装置の製造方法
JPH04360543A (ja) * 1991-06-06 1992-12-14 Mitsubishi Electric Corp 化合物半導体装置の製造方法
JP2735718B2 (ja) * 1991-10-29 1998-04-02 三菱電機株式会社 化合物半導体装置及びその製造方法
US5300403A (en) * 1992-06-18 1994-04-05 International Business Machines Corporation Line width control in a radiation sensitive polyimide
JP3119957B2 (ja) * 1992-11-30 2000-12-25 株式会社東芝 半導体装置の製造方法
JPH0815161B2 (ja) * 1993-03-03 1996-02-14 日本電気株式会社 半導体装置の製造方法
JP2565119B2 (ja) * 1993-11-30 1996-12-18 日本電気株式会社 パターン形成方法
JP3077524B2 (ja) * 1994-09-12 2000-08-14 株式会社村田製作所 半導体装置の製造方法
KR0135024B1 (en) * 1994-11-15 1998-04-20 Korea Electronics Telecomm Fabrication method of self-aligned t-gare gaas metal semiconductor field effect transistor
US5648198A (en) * 1994-12-13 1997-07-15 Kabushiki Kaisha Toshiba Resist hardening process having improved thermal stability

Also Published As

Publication number Publication date
DE69706910D1 (de) 2001-10-31
EP0801418B1 (de) 2001-09-26
EP0801418A3 (de) 1998-07-29
EP0801418A2 (de) 1997-10-15
US5804474A (en) 1998-09-08
JPH09283621A (ja) 1997-10-31
KR100239994B1 (ko) 2000-01-15

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