DE69702858T2 - Halbleiterspeicherprüfgerät mit redundanzanalyse - Google Patents

Halbleiterspeicherprüfgerät mit redundanzanalyse

Info

Publication number
DE69702858T2
DE69702858T2 DE69702858T DE69702858T DE69702858T2 DE 69702858 T2 DE69702858 T2 DE 69702858T2 DE 69702858 T DE69702858 T DE 69702858T DE 69702858 T DE69702858 T DE 69702858T DE 69702858 T2 DE69702858 T2 DE 69702858T2
Authority
DE
Germany
Prior art keywords
semiconductor memory
test device
memory test
redundancy analysis
redundancy
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE69702858T
Other languages
English (en)
Other versions
DE69702858D1 (de
Inventor
G Ramseyer
A Michaelson
H Augarten
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Teradyne Inc
Original Assignee
Teradyne Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Teradyne Inc filed Critical Teradyne Inc
Application granted granted Critical
Publication of DE69702858D1 publication Critical patent/DE69702858D1/de
Publication of DE69702858T2 publication Critical patent/DE69702858T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/70—Masking faults in memories by using spares or by reconfiguring
    • G11C29/72—Masking faults in memories by using spares or by reconfiguring with optimized replacement algorithms
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
    • G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
    • G11C29/44—Indication or identification of errors, e.g. for repair
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/3181—Functional testing
    • G01R31/319—Tester hardware, i.e. output processing circuits
    • G01R31/3193—Tester hardware, i.e. output processing circuits with comparison between actual response and known fault free response
    • G01R31/31937—Timing aspects, e.g. measuring propagation delay
DE69702858T 1996-07-18 1997-06-25 Halbleiterspeicherprüfgerät mit redundanzanalyse Expired - Fee Related DE69702858T2 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US08/683,397 US5754556A (en) 1996-07-18 1996-07-18 Semiconductor memory tester with hardware accelerators
PCT/US1997/011090 WO1998003979A1 (en) 1996-07-18 1997-06-25 Semiconductor memory tester with redundancy analysis

Publications (2)

Publication Number Publication Date
DE69702858D1 DE69702858D1 (de) 2000-09-21
DE69702858T2 true DE69702858T2 (de) 2001-04-05

Family

ID=24743887

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69702858T Expired - Fee Related DE69702858T2 (de) 1996-07-18 1997-06-25 Halbleiterspeicherprüfgerät mit redundanzanalyse

Country Status (6)

Country Link
US (1) US5754556A (de)
EP (1) EP0912979B1 (de)
JP (1) JP3879087B2 (de)
KR (1) KR100444427B1 (de)
DE (1) DE69702858T2 (de)
WO (1) WO1998003979A1 (de)

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US6442724B1 (en) 1999-04-02 2002-08-27 Teradyne, Inc. Failure capture apparatus and method for automatic test equipment
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JP4230061B2 (ja) * 1999-07-21 2009-02-25 株式会社アドバンテスト 不良救済解析器を搭載したメモリ試験装置
US8135842B1 (en) 1999-08-16 2012-03-13 Nvidia Corporation Internet jack
US6536005B1 (en) 1999-10-26 2003-03-18 Teradyne, Inc. High-speed failure capture apparatus and method for automatic test equipment
DE19963689A1 (de) * 1999-12-29 2001-07-12 Infineon Technologies Ag Schaltungsanordnung eines integrierten Halbleiterspeichers zum Speichern von Adressen fehlerhafter Speicherzellen
US6499120B1 (en) * 1999-12-30 2002-12-24 Infineon Technologies Richmond, Lp Usage of redundancy data for displaying failure bit maps for semiconductor devices
US6842844B1 (en) * 2000-02-24 2005-01-11 Agere Systems Inc. Parameter memory for hardware accelerator
DE10016719A1 (de) * 2000-04-04 2001-10-11 Infineon Technologies Ag Integrierter Speicher und Verfahren zur Funktionsprüfung von Speicherzellen eines integrierten Speichers
US6499118B1 (en) * 2000-05-17 2002-12-24 Teradyne, Inc. Redundancy analysis method and apparatus for ATE
US6795942B1 (en) * 2000-07-06 2004-09-21 Lsi Logic Corporation Built-in redundancy analysis for memories with row and column repair
US7039717B2 (en) * 2000-11-10 2006-05-02 Nvidia Corporation Internet modem streaming socket method
US7379475B2 (en) * 2002-01-25 2008-05-27 Nvidia Corporation Communications processor
US6717869B2 (en) * 2002-04-25 2004-04-06 D.S.P. Group Ltd. Integrated circuit having redundant, self-organized architecture for improving yield
DE10307027A1 (de) * 2003-02-20 2004-09-09 Infineon Technologies Ag Verfahren und Testeinrichtung zum Ermitteln einer Reparaturlösung für einen Speicherbaustein
DE10337284B4 (de) * 2003-08-13 2014-03-20 Qimonda Ag Integrierter Speicher mit einer Schaltung zum Funktionstest des integrierten Speichers sowie Verfahren zum Betrieb des integrierten Speichers
US7260631B1 (en) 2003-12-19 2007-08-21 Nvidia Corporation System and method for receiving iSCSI protocol data units
US7624198B1 (en) 2003-12-19 2009-11-24 Nvidia Corporation Sequence tagging system and method for transport offload engine data lists
US8549170B2 (en) * 2003-12-19 2013-10-01 Nvidia Corporation Retransmission system and method for a transport offload engine
US8065439B1 (en) 2003-12-19 2011-11-22 Nvidia Corporation System and method for using metadata in the context of a transport offload engine
US8176545B1 (en) 2003-12-19 2012-05-08 Nvidia Corporation Integrated policy checking system and method
US7899913B2 (en) * 2003-12-19 2011-03-01 Nvidia Corporation Connection management system and method for a transport offload engine
US7206872B2 (en) * 2004-02-20 2007-04-17 Nvidia Corporation System and method for insertion of markers into a data stream
US7249306B2 (en) * 2004-02-20 2007-07-24 Nvidia Corporation System and method for generating 128-bit cyclic redundancy check values with 32-bit granularity
US7698413B1 (en) 2004-04-12 2010-04-13 Nvidia Corporation Method and apparatus for accessing and maintaining socket control information for high speed network connections
US7079054B2 (en) * 2004-06-04 2006-07-18 Broadcom Corporation V.42bis standalone hardware accelerator and architecture of construction
DE102004042252A1 (de) * 2004-09-01 2005-11-10 Infineon Technologies Ag Integrierte Speicherschaltung und Verfahren zum Komprimieren von Fehlerdaten
US7957379B2 (en) * 2004-10-19 2011-06-07 Nvidia Corporation System and method for processing RX packets in high speed network applications using an RX FIFO buffer
US7395465B2 (en) * 2006-01-13 2008-07-01 International Business Machines Corporation Memory array repair where repair logic cannot operate at same operating condition as array
US7444566B2 (en) * 2006-03-06 2008-10-28 Verigy (Singapore) Pte. Ltd. Memory device fail summary data reduction for improved redundancy analysis
US20080270854A1 (en) 2007-04-24 2008-10-30 Micron Technology, Inc. System and method for running test and redundancy analysis in parallel
US8977912B2 (en) * 2007-05-07 2015-03-10 Macronix International Co., Ltd. Method and apparatus for repairing memory
US9275168B2 (en) * 2013-07-19 2016-03-01 International Business Machines Corporation Hardware projection of fixed and variable length columns of database tables
US9235564B2 (en) 2013-07-19 2016-01-12 International Business Machines Corporation Offloading projection of fixed and variable length database columns

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US4876685A (en) * 1987-06-08 1989-10-24 Teradyne, Inc. Failure information processing in automatic memory tester
DE3728521A1 (de) * 1987-08-26 1989-03-09 Siemens Ag Anordnung und verfahren zur feststellung und lokalisierung von fehlerhaften schaltkreisen eines speicherbausteins
JP2938470B2 (ja) * 1989-06-01 1999-08-23 三菱電機株式会社 半導体記憶装置
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US5577050A (en) * 1994-12-28 1996-11-19 Lsi Logic Corporation Method and apparatus for configurable build-in self-repairing of ASIC memories design

Also Published As

Publication number Publication date
KR20000067917A (ko) 2000-11-25
KR100444427B1 (ko) 2004-08-16
US5754556A (en) 1998-05-19
WO1998003979A1 (en) 1998-01-29
JP2000515290A (ja) 2000-11-14
JP3879087B2 (ja) 2007-02-07
DE69702858D1 (de) 2000-09-21
EP0912979B1 (de) 2000-08-16
EP0912979A1 (de) 1999-05-06

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Legal Events

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8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee