DE69631406D1 - Verriegelungsschaltung zum Empfangen von Signalen mit niedriger Amplitude - Google Patents

Verriegelungsschaltung zum Empfangen von Signalen mit niedriger Amplitude

Info

Publication number
DE69631406D1
DE69631406D1 DE69631406T DE69631406T DE69631406D1 DE 69631406 D1 DE69631406 D1 DE 69631406D1 DE 69631406 T DE69631406 T DE 69631406T DE 69631406 T DE69631406 T DE 69631406T DE 69631406 D1 DE69631406 D1 DE 69631406D1
Authority
DE
Germany
Prior art keywords
latch circuit
low amplitude
amplitude signals
receiving low
receiving
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE69631406T
Other languages
English (en)
Other versions
DE69631406T2 (de
Inventor
Hiroyuki Takahashi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Electronics Corp
Original Assignee
NEC Electronics Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Electronics Corp filed Critical NEC Electronics Corp
Publication of DE69631406D1 publication Critical patent/DE69631406D1/de
Application granted granted Critical
Publication of DE69631406T2 publication Critical patent/DE69631406T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/08—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices
    • H03K19/094—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices using field-effect transistors
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
    • H03K3/02—Generators characterised by the type of circuit or by the means used for producing pulses
    • H03K3/353—Generators characterised by the type of circuit or by the means used for producing pulses by the use, as active elements, of field-effect transistors with internal or external positive feedback
    • H03K3/356—Bistable circuits
    • H03K3/356069—Bistable circuits using additional transistors in the feedback circuit
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
    • H03K3/02—Generators characterised by the type of circuit or by the means used for producing pulses
    • H03K3/021—Generators characterised by the type of circuit or by the means used for producing pulses by the use, as active elements, of more than one type of element or means, e.g. BIMOS, composite devices such as IGBT
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
    • H03K3/02—Generators characterised by the type of circuit or by the means used for producing pulses
    • H03K3/353—Generators characterised by the type of circuit or by the means used for producing pulses by the use, as active elements, of field-effect transistors with internal or external positive feedback
    • H03K3/356—Bistable circuits
    • H03K3/356017—Bistable circuits using additional transistors in the input circuit
    • H03K3/356034—Bistable circuits using additional transistors in the input circuit the input circuit having a differential configuration
    • H03K3/356043—Bistable circuits using additional transistors in the input circuit the input circuit having a differential configuration with synchronous operation
DE69631406T 1995-11-17 1996-11-14 Halteschaltung zum Empfangen von Signalen mit niedriger Amplitude Expired - Fee Related DE69631406T2 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP32362795 1995-11-17
JP32362795A JP3149759B2 (ja) 1995-11-17 1995-11-17 ラッチ回路

Publications (2)

Publication Number Publication Date
DE69631406D1 true DE69631406D1 (de) 2004-03-04
DE69631406T2 DE69631406T2 (de) 2004-12-02

Family

ID=18156851

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69631406T Expired - Fee Related DE69631406T2 (de) 1995-11-17 1996-11-14 Halteschaltung zum Empfangen von Signalen mit niedriger Amplitude

Country Status (5)

Country Link
US (1) US5877642A (de)
EP (1) EP0774836B1 (de)
JP (1) JP3149759B2 (de)
KR (1) KR100242905B1 (de)
DE (1) DE69631406T2 (de)

Families Citing this family (26)

* Cited by examiner, † Cited by third party
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US5978379A (en) 1997-01-23 1999-11-02 Gadzoox Networks, Inc. Fiber channel learning bridge, learning half bridge, and protocol
GB9708865D0 (en) * 1997-04-30 1997-06-25 Phoenix Vlsi Consultants Ltd ECL-CMOS converter
US6100716A (en) * 1998-09-17 2000-08-08 Nortel Networks Corporation Voltage excursion detection apparatus
US7430171B2 (en) 1998-11-19 2008-09-30 Broadcom Corporation Fibre channel arbitrated loop bufferless switch circuitry to increase bandwidth without significant increase in cost
US6911855B2 (en) * 1999-06-28 2005-06-28 Broadcom Corporation Current-controlled CMOS circuit using higher voltage supply in low voltage CMOS process
US6424194B1 (en) 1999-06-28 2002-07-23 Broadcom Corporation Current-controlled CMOS logic family
US6340899B1 (en) * 2000-02-24 2002-01-22 Broadcom Corporation Current-controlled CMOS circuits with inductive broadbanding
DE10038905C2 (de) * 2000-08-09 2003-04-17 Atmel Germany Gmbh Verfahren zur Erhöhung der Grenzfrequenz bei Flip-Flops
US7239636B2 (en) 2001-07-23 2007-07-03 Broadcom Corporation Multiple virtual channels for use in network devices
US7295555B2 (en) 2002-03-08 2007-11-13 Broadcom Corporation System and method for identifying upper layer protocol message boundaries
US7411959B2 (en) 2002-08-30 2008-08-12 Broadcom Corporation System and method for handling out-of-order frames
US7346701B2 (en) 2002-08-30 2008-03-18 Broadcom Corporation System and method for TCP offload
US7934021B2 (en) 2002-08-29 2011-04-26 Broadcom Corporation System and method for network interfacing
US7313623B2 (en) 2002-08-30 2007-12-25 Broadcom Corporation System and method for TCP/IP offload independent of bandwidth delay product
US8180928B2 (en) 2002-08-30 2012-05-15 Broadcom Corporation Method and system for supporting read operations with CRC for iSCSI and iSCSI chimney
DE60330836D1 (de) * 2003-02-05 2010-02-25 Alcatel Lucent ECL-Schaltung mit gesteuerter Stromquelle
US7202706B1 (en) 2003-04-10 2007-04-10 Pmc-Sierra, Inc. Systems and methods for actively-peaked current-mode logic
US7106104B2 (en) * 2003-10-30 2006-09-12 International Business Machines Corporation Integrated line driver
US7362174B2 (en) * 2005-07-29 2008-04-22 Broadcom Corporation Current-controlled CMOS (C3MOS) wideband input data amplifier for reduced differential and common-mode reflection
US7598811B2 (en) * 2005-07-29 2009-10-06 Broadcom Corporation Current-controlled CMOS (C3MOS) fully differential integrated wideband amplifier/equalizer with adjustable gain and frequency response without additional power or loading
US7598788B2 (en) * 2005-09-06 2009-10-06 Broadcom Corporation Current-controlled CMOS (C3MOS) fully differential integrated delay cell with variable delay and high bandwidth
US7336114B2 (en) * 2006-04-05 2008-02-26 Wionics Research High-speed latching technique and application to frequency dividers
US20090302916A1 (en) * 2008-06-05 2009-12-10 Sarabjeet Singh Low Power and Full Swing Pseudo CML Latched Logic-Gates
US9728967B2 (en) * 2014-03-24 2017-08-08 Advanced Fusion Systems Llc System for improving power factor in an AC power system
CN105391426B (zh) * 2015-12-15 2018-05-11 成都振芯科技股份有限公司 能接收毫伏级信号的高速锁存器
JP6789434B1 (ja) 2020-06-27 2020-11-25 堤 康博 包丁ホルダ及び包丁ホルダ装置

Family Cites Families (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6387014A (ja) * 1986-09-30 1988-04-18 Sony Corp ラツチドコンパレ−タ
JPS6474823A (en) * 1987-09-17 1989-03-20 Fujitsu Ltd Emitter follower circuit
US4970406A (en) * 1987-12-30 1990-11-13 Gazelle Microcircuits, Inc. Resettable latch circuit
JPH0777346B2 (ja) * 1988-12-28 1995-08-16 株式会社東芝 論理レベル変換回路
US5216298A (en) * 1989-12-14 1993-06-01 Mitsubishi Denki Kabushiki Kaisha ECL input buffer for BiCMOS
JPH03201719A (ja) * 1989-12-28 1991-09-03 Matsushita Electric Ind Co Ltd Ｅｃｌ回路
US5148061A (en) * 1991-02-27 1992-09-15 Motorola, Inc. ECL to CMOS translation and latch logic circuit
EP0501085B1 (de) * 1991-02-28 1996-10-02 International Business Machines Corporation Pegelschieberschaltung für schnelle leistungsarme ECL nach CMOS-Eingangspuffern in biCMOS-Technik
JP2747467B2 (ja) * 1991-08-19 1998-05-06 日本電信電話株式会社 スタティック型フリップフロップ回路
JP2546489B2 (ja) * 1993-04-23 1996-10-23 日本電気株式会社 レベル変換回路

Also Published As

Publication number Publication date
JPH09148893A (ja) 1997-06-06
EP0774836A3 (de) 1997-08-06
KR970031344A (ko) 1997-06-26
US5877642A (en) 1999-03-02
KR100242905B1 (ko) 2000-02-01
EP0774836B1 (de) 2004-01-28
EP0774836A2 (de) 1997-05-21
JP3149759B2 (ja) 2001-03-26
DE69631406T2 (de) 2004-12-02

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee