DE69627565D1 - Verpacken von Multi-Chip-Modulen ohne Drahtverbindung - Google Patents

Verpacken von Multi-Chip-Modulen ohne Drahtverbindung

Info

Publication number
DE69627565D1
DE69627565D1 DE69627565T DE69627565T DE69627565D1 DE 69627565 D1 DE69627565 D1 DE 69627565D1 DE 69627565 T DE69627565 T DE 69627565T DE 69627565 T DE69627565 T DE 69627565T DE 69627565 D1 DE69627565 D1 DE 69627565D1
Authority
DE
Germany
Prior art keywords
packaging
wire connection
chip modules
modules
chip
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE69627565T
Other languages
English (en)
Other versions
DE69627565T2 (de
Inventor
Yinon Degani
Thomas D Dudderar
Byung J Han
Alan M Lyons
King L Tai
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
AT&T Corp
Original Assignee
AT&T Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by AT&T Corp filed Critical AT&T Corp
Publication of DE69627565D1 publication Critical patent/DE69627565D1/de
Application granted granted Critical
Publication of DE69627565T2 publication Critical patent/DE69627565T2/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/12—Mountings, e.g. non-detachable insulating substrates
    • H01L23/13—Mountings, e.g. non-detachable insulating substrates characterised by the shape
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/12—Mountings, e.g. non-detachable insulating substrates
    • H01L23/14—Mountings, e.g. non-detachable insulating substrates characterised by the material or its electrical properties
    • H01L23/147—Semiconductor insulating substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/4985—Flexible insulating substrates
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    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16135—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/16145—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
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    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
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    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
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    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
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    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
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    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
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    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484—Connecting portions
    • H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
    • H01L2224/48465—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73207—Bump and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
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    • H01L2924/01019—Potassium [K]
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    • H01L2924/01—Chemical elements
    • H01L2924/01078—Platinum [Pt]
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
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    • H01L2924/01079—Gold [Au]
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    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013—Alloys
    • H01L2924/0132—Binary Alloys
    • H01L2924/01322—Eutectic Alloys, i.e. obtained by a liquid transforming into two solid phases
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    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/102—Material of the semiconductor or solid state bodies
    • H01L2924/1025—Semiconducting materials
    • H01L2924/10251—Elemental semiconductors, i.e. Group IV
    • H01L2924/10253—Silicon [Si]
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    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/1515—Shape
    • H01L2924/15151—Shape the die mounting substrate comprising an aperture, e.g. for underfilling, outgassing, window type wire connections
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
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    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
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    • H01L2924/153—Connection portion
    • H01L2924/1532—Connection portion the connection portion being formed on the die mounting surface of the substrate
    • H01L2924/15321—Connection portion the connection portion being formed on the die mounting surface of the substrate being a ball array, e.g. BGA
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    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/156—Material
    • H01L2924/157—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
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    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/161—Cap
    • H01L2924/1615—Shape
    • H01L2924/16152—Cap comprising a cavity for hosting the device, e.g. U-shaped cap
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    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
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    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/1901—Structure
    • H01L2924/1904—Component type
    • H01L2924/19041—Component type being a capacitor
DE69627565T 1995-02-24 1996-02-14 Verpacken von Multi-Chip-Modulen ohne Drahtverbindung Expired - Lifetime DE69627565T2 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US393628 1995-02-24
US08/393,628 US5608262A (en) 1995-02-24 1995-02-24 Packaging multi-chip modules without wire-bond interconnection

Publications (2)

Publication Number Publication Date
DE69627565D1 true DE69627565D1 (de) 2003-05-28
DE69627565T2 DE69627565T2 (de) 2004-02-12

Family

ID=23555559

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69627565T Expired - Lifetime DE69627565T2 (de) 1995-02-24 1996-02-14 Verpacken von Multi-Chip-Modulen ohne Drahtverbindung

Country Status (8)

Country Link
US (1) US5608262A (de)
EP (1) EP0729180B1 (de)
JP (1) JP3209320B2 (de)
KR (1) KR100380950B1 (de)
CA (1) CA2166926C (de)
DE (1) DE69627565T2 (de)
SG (1) SG38976A1 (de)
TW (1) TW376574B (de)

Families Citing this family (204)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2728392A1 (fr) * 1994-12-16 1996-06-21 Bull Sa Procede et support de connexion d'un circuit integre a un autre support par l'intermediaire de boules
JP3014029B2 (ja) * 1995-06-16 2000-02-28 日本電気株式会社 半導体素子の実装方法
JPH0964244A (ja) * 1995-08-17 1997-03-07 Hitachi Ltd 半導体装置およびその製造方法
JP3332308B2 (ja) * 1995-11-07 2002-10-07 新光電気工業株式会社 半導体装置及びその製造方法
JP3527350B2 (ja) * 1996-02-01 2004-05-17 株式会社ルネサステクノロジ 半導体装置
US6682954B1 (en) 1996-05-29 2004-01-27 Micron Technology, Inc. Method for employing piggyback multiple die #3
JPH1032221A (ja) * 1996-07-12 1998-02-03 Nec Corp プリント配線基板
US6075711A (en) * 1996-10-21 2000-06-13 Alpine Microsystems, Inc. System and method for routing connections of integrated circuits
US5815372A (en) * 1997-03-25 1998-09-29 Intel Corporation Packaging multiple dies on a ball grid array substrate
US5889654A (en) * 1997-04-09 1999-03-30 International Business Machines Corporation Advanced chip packaging structure for memory card applications
US5869889A (en) * 1997-04-21 1999-02-09 Lsi Logic Corporation Thin power tape ball grid array package
JP2001507520A (ja) * 1997-05-23 2001-06-05 アルパイン・マイクロシステムズ・インコーポレイテッド 集積回路パッケージングのための構造体及び方法
US6208018B1 (en) * 1997-05-29 2001-03-27 Micron Technology, Inc. Piggyback multiple dice assembly
US5790384A (en) * 1997-06-26 1998-08-04 International Business Machines Corporation Bare die multiple dies for direct attach
US5869894A (en) * 1997-07-18 1999-02-09 Lucent Technologies Inc. RF IC package
US5963429A (en) * 1997-08-20 1999-10-05 Sulzer Intermedics Inc. Printed circuit substrate with cavities for encapsulating integrated circuits
US5798567A (en) * 1997-08-21 1998-08-25 Hewlett-Packard Company Ball grid array integrated circuit package which employs a flip chip integrated circuit and decoupling capacitors
CA2218307C (en) * 1997-10-10 2006-01-03 Gennum Corporation Three dimensional packaging configuration for multi-chip module assembly
US6441487B2 (en) 1997-10-20 2002-08-27 Flip Chip Technologies, L.L.C. Chip scale package using large ductile solder balls
US6117382A (en) * 1998-02-05 2000-09-12 Micron Technology, Inc. Method for encasing array packages
US6369444B1 (en) * 1998-05-19 2002-04-09 Agere Systems Guardian Corp. Packaging silicon on silicon multichip modules
US5977640A (en) * 1998-06-26 1999-11-02 International Business Machines Corporation Highly integrated chip-on-chip packaging
US6084308A (en) * 1998-06-30 2000-07-04 National Semiconductor Corporation Chip-on-chip integrated circuit package and method for making the same
WO2000004595A2 (en) * 1998-07-20 2000-01-27 Intel Corporation Land-side mounting of components to an integrated circuit package
US6154370A (en) * 1998-07-21 2000-11-28 Lucent Technologies Inc. Recessed flip-chip package
US6160715A (en) * 1998-09-08 2000-12-12 Lucent Technologies Inc. Translator for recessed flip-chip package
US6175158B1 (en) * 1998-09-08 2001-01-16 Lucent Technologies Inc. Interposer for recessed flip-chip package
US6154371A (en) * 1998-09-30 2000-11-28 Cisco Technology, Inc. Printed circuit board assembly and method
US6329713B1 (en) * 1998-10-21 2001-12-11 International Business Machines Corporation Integrated circuit chip carrier assembly comprising a stiffener attached to a dielectric substrate
US6184465B1 (en) * 1998-11-12 2001-02-06 Micron Technology, Inc. Semiconductor package
US6869870B2 (en) * 1998-12-21 2005-03-22 Megic Corporation High performance system-on-chip discrete components using post passivation process
US7531417B2 (en) * 1998-12-21 2009-05-12 Megica Corporation High performance system-on-chip passive device using post passivation process
US8178435B2 (en) 1998-12-21 2012-05-15 Megica Corporation High performance system-on-chip inductor using post passivation process
US8421158B2 (en) * 1998-12-21 2013-04-16 Megica Corporation Chip structure with a passive device and method for forming the same
US6303423B1 (en) * 1998-12-21 2001-10-16 Megic Corporation Method for forming high performance system-on-chip using post passivation process
US6965165B2 (en) 1998-12-21 2005-11-15 Mou-Shiung Lin Top layers of metal for high performance IC's
JP2000223657A (ja) * 1999-02-03 2000-08-11 Rohm Co Ltd 半導体装置およびそれに用いる半導体チップ
JP2000252414A (ja) * 1999-03-04 2000-09-14 Mitsubishi Electric Corp 半導体装置
US6268660B1 (en) * 1999-03-05 2001-07-31 International Business Machines Corporation Silicon packaging with through wafer interconnects
US6215193B1 (en) * 1999-04-21 2001-04-10 Advanced Semiconductor Engineering, Inc. Multichip modules and manufacturing method therefor
US6498708B2 (en) * 1999-05-27 2002-12-24 Emerson Electric Co. Method and apparatus for mounting printed circuit board components
KR100393095B1 (ko) * 1999-06-12 2003-07-31 앰코 테크놀로지 코리아 주식회사 반도체패키지와 그 제조방법
US6049275A (en) * 1999-06-15 2000-04-11 Hou; Chien Tzu Security mechanism for an IC packing box
WO2000079592A1 (en) * 1999-06-17 2000-12-28 Hitachi, Ltd. Semiconductor device and electronic device
US6232667B1 (en) * 1999-06-29 2001-05-15 International Business Machines Corporation Technique for underfilling stacked chips on a cavity MLC module
US6297551B1 (en) * 1999-09-22 2001-10-02 Agere Systems Guardian Corp. Integrated circuit packages with improved EMI characteristics
US6559531B1 (en) 1999-10-14 2003-05-06 Sun Microsystems, Inc. Face to face chips
US6483101B1 (en) * 1999-12-08 2002-11-19 Amkor Technology, Inc. Molded image sensor package having lens holder
US6369448B1 (en) * 2000-01-21 2002-04-09 Lsi Logic Corporation Vertically integrated flip chip semiconductor package
US6414396B1 (en) * 2000-01-24 2002-07-02 Amkor Technology, Inc. Package for stacked integrated circuits
JP3996315B2 (ja) * 2000-02-21 2007-10-24 松下電器産業株式会社 半導体装置およびその製造方法
JP3417380B2 (ja) 2000-04-05 2003-06-16 株式会社村田製作所 非可逆回路素子および通信装置
US6916121B2 (en) * 2001-08-03 2005-07-12 National Semiconductor Corporation Optical sub-assembly for optoelectronic modules
US6642613B1 (en) * 2000-05-09 2003-11-04 National Semiconductor Corporation Techniques for joining an opto-electronic module to a semiconductor package
US6707140B1 (en) 2000-05-09 2004-03-16 National Semiconductor Corporation Arrayable, scaleable, and stackable molded package configuration
US6767140B2 (en) * 2000-05-09 2004-07-27 National Semiconductor Corporation Ceramic optical sub-assembly for opto-electronic module utilizing LTCC (low-temperature co-fired ceramic) technology
US6624507B1 (en) 2000-05-09 2003-09-23 National Semiconductor Corporation Miniature semiconductor package for opto-electronic devices
US6765275B1 (en) * 2000-05-09 2004-07-20 National Semiconductor Corporation Two-layer electrical substrate for optical devices
US7247932B1 (en) * 2000-05-19 2007-07-24 Megica Corporation Chip package with capacitor
US6546620B1 (en) 2000-06-29 2003-04-15 Amkor Technology, Inc. Flip chip integrated circuit and passive chip component package fabrication method
US6356453B1 (en) * 2000-06-29 2002-03-12 Amkor Technology, Inc. Electronic package having flip chip integrated circuit and passive chip component
JP3829050B2 (ja) * 2000-08-29 2006-10-04 松下電器産業株式会社 一体型電子部品
TW569403B (en) * 2001-04-12 2004-01-01 Siliconware Precision Industries Co Ltd Multi-chip module and its manufacturing method
JP4497683B2 (ja) * 2000-09-11 2010-07-07 ローム株式会社 集積回路装置
KR100508261B1 (ko) * 2000-10-04 2005-08-18 앰코 테크놀로지 코리아 주식회사 반도체 패키지 및 그 제조방법
JP4505983B2 (ja) * 2000-12-01 2010-07-21 日本電気株式会社 半導体装置
KR100705248B1 (ko) * 2000-12-04 2007-04-06 앰코 테크놀로지 코리아 주식회사 반도체 패키지 및 그 제조방법
KR20020058201A (ko) * 2000-12-29 2002-07-12 마이클 디. 오브라이언 반도체패키지 및 그 제조 방법
US6894399B2 (en) 2001-04-30 2005-05-17 Intel Corporation Microelectronic device having signal distribution functionality on an interfacial layer thereof
US6888240B2 (en) * 2001-04-30 2005-05-03 Intel Corporation High performance, low cost microelectronic circuit package with interposer
US6610560B2 (en) 2001-05-11 2003-08-26 Siliconware Precision Industries Co., Ltd. Chip-on-chip based multi-chip module with molded underfill and method of fabricating the same
US20020167804A1 (en) * 2001-05-14 2002-11-14 Intel Corporation Polymeric encapsulation material with fibrous filler for use in microelectronic circuit packaging
US7071024B2 (en) * 2001-05-21 2006-07-04 Intel Corporation Method for packaging a microelectronic device using on-die bond pad expansion
US6730536B1 (en) 2001-06-28 2004-05-04 Amkor Technology, Inc. Pre-drilled image sensor package fabrication method
US6548759B1 (en) 2001-06-28 2003-04-15 Amkor Technology, Inc. Pre-drilled image sensor package
US6486545B1 (en) * 2001-07-26 2002-11-26 Amkor Technology, Inc. Pre-drilled ball grid array package
US7023705B2 (en) 2001-08-03 2006-04-04 National Semiconductor Corporation Ceramic optical sub-assembly for optoelectronic modules
US7269027B2 (en) * 2001-08-03 2007-09-11 National Semiconductor Corporation Ceramic optical sub-assembly for optoelectronic modules
US6856007B2 (en) * 2001-08-28 2005-02-15 Tessera, Inc. High-frequency chip packages
US7176506B2 (en) * 2001-08-28 2007-02-13 Tessera, Inc. High frequency chip packages with connecting elements
DE10142655A1 (de) * 2001-08-31 2003-04-03 Epcos Ag Bauelementanordnung
US6759275B1 (en) * 2001-09-04 2004-07-06 Megic Corporation Method for making high-performance RF integrated circuits
US7183658B2 (en) 2001-09-05 2007-02-27 Intel Corporation Low cost microelectronic circuit package
US20030057544A1 (en) * 2001-09-13 2003-03-27 Nathan Richard J. Integrated assembly protocol
US6613606B1 (en) * 2001-09-17 2003-09-02 Magic Corporation Structure of high performance combo chip and processing method
US6847105B2 (en) 2001-09-21 2005-01-25 Micron Technology, Inc. Bumping technology in stacked die configurations
US6973225B2 (en) * 2001-09-24 2005-12-06 National Semiconductor Corporation Techniques for attaching rotated photonic devices to an optical sub-assembly in an optoelectronic package
US20030059976A1 (en) * 2001-09-24 2003-03-27 Nathan Richard J. Integrated package and methods for making same
US6942018B2 (en) * 2001-09-28 2005-09-13 The Board Of Trustees Of The Leland Stanford Junior University Electroosmotic microchannel cooling system
US7134486B2 (en) * 2001-09-28 2006-11-14 The Board Of Trustees Of The Leeland Stanford Junior University Control of electrolysis gases in electroosmotic pump systems
GB0128351D0 (en) * 2001-11-27 2002-01-16 Koninkl Philips Electronics Nv Multi-chip module semiconductor devices
US6606251B1 (en) 2002-02-07 2003-08-12 Cooligy Inc. Power conditioning module
US20030153119A1 (en) * 2002-02-14 2003-08-14 Nathan Richard J. Integrated circuit package and method for fabrication
US6767765B2 (en) * 2002-03-27 2004-07-27 Intel Corporation Methods and apparatus for disposing a thermal interface material between a heat source and a heat dissipation device
US20030183934A1 (en) * 2002-03-29 2003-10-02 Barrett Joseph C. Method and apparatus for stacking multiple die in a flip chip semiconductor package
US6903458B1 (en) * 2002-06-20 2005-06-07 Richard J. Nathan Embedded carrier for an integrated circuit chip
JP4601892B2 (ja) * 2002-07-04 2010-12-22 ラムバス・インコーポレーテッド 半導体装置および半導体チップのバンプ製造方法
US6885107B2 (en) * 2002-08-29 2005-04-26 Micron Technology, Inc. Flip-chip image sensor packages and methods of fabrication
US6879040B2 (en) * 2002-09-18 2005-04-12 Agilent Technologies, Inc. Surface mountable electronic device
US7400036B2 (en) * 2002-12-16 2008-07-15 Avago Technologies General Ip Pte Ltd Semiconductor chip package with a package substrate and a lid cover
US6833628B2 (en) * 2002-12-17 2004-12-21 Delphi Technologies, Inc. Mutli-chip module
JP4110992B2 (ja) * 2003-02-07 2008-07-02 セイコーエプソン株式会社 半導体装置、電子デバイス、電子機器、半導体装置の製造方法および電子デバイスの製造方法
US7754537B2 (en) * 2003-02-25 2010-07-13 Tessera, Inc. Manufacture of mountable capped chips
US20040217471A1 (en) * 2003-02-27 2004-11-04 Tessera, Inc. Component and assemblies with ends offset downwardly
US8368150B2 (en) * 2003-03-17 2013-02-05 Megica Corporation High performance IC chip having discrete decoupling capacitors attached to its IC surface
TWI230447B (en) * 2003-04-25 2005-04-01 Advanced Semiconductor Eng Multi-chips package
TWI236763B (en) * 2003-05-27 2005-07-21 Megic Corp High performance system-on-chip inductor using post passivation process
US6972480B2 (en) 2003-06-16 2005-12-06 Shellcase Ltd. Methods and apparatus for packaging integrated circuit devices
WO2005004195A2 (en) * 2003-07-03 2005-01-13 Shellcase Ltd. Method and apparatus for packaging integrated circuit devices
US6873040B2 (en) * 2003-07-08 2005-03-29 Texas Instruments Incorporated Semiconductor packages for enhanced number of terminals, speed and power performance
US6985668B2 (en) * 2003-07-15 2006-01-10 National Semiconductor Corporation Multi-purpose optical light pipe
US7156562B2 (en) * 2003-07-15 2007-01-02 National Semiconductor Corporation Opto-electronic module form factor having adjustable optical plane height
CN100514580C (zh) * 2003-08-26 2009-07-15 宇芯（毛里求斯）控股有限公司 可颠倒无引线封装及其堆叠
US20050067681A1 (en) * 2003-09-26 2005-03-31 Tessera, Inc. Package having integral lens and wafer-scale fabrication method therefor
WO2005031862A1 (en) * 2003-09-26 2005-04-07 Tessera, Inc. Structure and method of making sealed capped chips
US20050093175A1 (en) * 2003-11-03 2005-05-05 Martin Reiss Arrangement for improving the reliability of semiconductor modules
US20050139984A1 (en) * 2003-12-19 2005-06-30 Tessera, Inc. Package element and packaged chip having severable electrically conductive ties
US7521785B2 (en) * 2003-12-23 2009-04-21 Tessera, Inc. Packaged systems with MRAM
TWI233170B (en) * 2004-02-05 2005-05-21 United Microelectronics Corp Ultra-thin wafer level stack packaging method and structure using thereof
US20050189622A1 (en) * 2004-03-01 2005-09-01 Tessera, Inc. Packaged acoustic and electromagnetic transducer chips
US7355282B2 (en) * 2004-09-09 2008-04-08 Megica Corporation Post passivation interconnection process and structures
US8008775B2 (en) 2004-09-09 2011-08-30 Megica Corporation Post passivation interconnection structures
JP4146826B2 (ja) * 2004-09-14 2008-09-10 カシオマイクロニクス株式会社 配線基板及び半導体装置
TWI393228B (zh) * 2004-12-14 2013-04-11 Freescale Semiconductor Inc 覆晶及焊線封裝半導體
JP4581768B2 (ja) * 2005-03-16 2010-11-17 ソニー株式会社 半導体装置の製造方法
US8143095B2 (en) * 2005-03-22 2012-03-27 Tessera, Inc. Sequential fabrication of vertical conductive interconnects in capped chips
US8384189B2 (en) * 2005-03-29 2013-02-26 Megica Corporation High performance system-on-chip using post passivation process
US8130560B1 (en) 2006-11-13 2012-03-06 Google Inc. Multi-rank partial width memory modules
US7386656B2 (en) 2006-07-31 2008-06-10 Metaram, Inc. Interface circuit system and method for performing power management operations in conjunction with only a portion of a memory circuit
US8060774B2 (en) 2005-06-24 2011-11-15 Google Inc. Memory systems and memory modules
US8327104B2 (en) 2006-07-31 2012-12-04 Google Inc. Adjusting the timing of signals associated with a memory system
US8081474B1 (en) 2007-12-18 2011-12-20 Google Inc. Embossed heat spreader
US10013371B2 (en) 2005-06-24 2018-07-03 Google Llc Configurable memory circuit system and method
US8397013B1 (en) 2006-10-05 2013-03-12 Google Inc. Hybrid memory module
WO2007002324A2 (en) * 2005-06-24 2007-01-04 Metaram, Inc. An integrated memory core and memory interface circuit
US8089795B2 (en) 2006-02-09 2012-01-03 Google Inc. Memory module with memory stack and interface with enhanced capabilities
US8055833B2 (en) 2006-10-05 2011-11-08 Google Inc. System and method for increasing capacity, performance, and flexibility of flash storage
US8111566B1 (en) 2007-11-16 2012-02-07 Google, Inc. Optimal channel design for memory devices for providing a high-speed memory interface
US9171585B2 (en) 2005-06-24 2015-10-27 Google Inc. Configurable memory circuit system and method
US8041881B2 (en) * 2006-07-31 2011-10-18 Google Inc. Memory device with emulated characteristics
US8438328B2 (en) 2008-02-21 2013-05-07 Google Inc. Emulation of abstracted DIMMs using abstracted DRAMs
US8386722B1 (en) 2008-06-23 2013-02-26 Google Inc. Stacked DIMM memory interface
US8077535B2 (en) 2006-07-31 2011-12-13 Google Inc. Memory refresh apparatus and method
US8244971B2 (en) * 2006-07-31 2012-08-14 Google Inc. Memory circuit system and method
US8090897B2 (en) 2006-07-31 2012-01-03 Google Inc. System and method for simulating an aspect of a memory circuit
US9507739B2 (en) 2005-06-24 2016-11-29 Google Inc. Configurable memory circuit system and method
US8359187B2 (en) 2005-06-24 2013-01-22 Google Inc. Simulating a different number of memory circuit devices
US7609567B2 (en) * 2005-06-24 2009-10-27 Metaram, Inc. System and method for simulating an aspect of a memory circuit
US8335894B1 (en) 2008-07-25 2012-12-18 Google Inc. Configurable memory system with interface circuit
US20080028136A1 (en) * 2006-07-31 2008-01-31 Schakel Keith R Method and apparatus for refresh management of memory modules
US9542352B2 (en) * 2006-02-09 2017-01-10 Google Inc. System and method for reducing command scheduling constraints of memory circuits
US8796830B1 (en) 2006-09-01 2014-08-05 Google Inc. Stackable low-profile lead frame package
US20080082763A1 (en) * 2006-10-02 2008-04-03 Metaram, Inc. Apparatus and method for power management of memory circuits by a system or component thereof
CN1901161B (zh) * 2005-07-22 2010-10-27 米辑电子股份有限公司 连续电镀制作线路组件的方法及线路组件结构
GB2444663B (en) 2005-09-02 2011-12-07 Metaram Inc Methods and apparatus of stacking drams
US7943431B2 (en) * 2005-12-02 2011-05-17 Unisem (Mauritius) Holdings Limited Leadless semiconductor package and method of manufacture
US7402442B2 (en) * 2005-12-21 2008-07-22 International Business Machines Corporation Physically highly secure multi-chip assembly
US7304382B2 (en) * 2006-01-11 2007-12-04 Staktek Group L.P. Managed memory component
US20070190747A1 (en) * 2006-01-23 2007-08-16 Tessera Technologies Hungary Kft. Wafer level packaging to lidded chips
US7936062B2 (en) * 2006-01-23 2011-05-03 Tessera Technologies Ireland Limited Wafer level chip packaging
US9632929B2 (en) 2006-02-09 2017-04-25 Google Inc. Translating an address associated with a command communicated between a system and memory circuits
US20080002460A1 (en) * 2006-03-01 2008-01-03 Tessera, Inc. Structure and method of making lidded chips
US7663232B2 (en) * 2006-03-07 2010-02-16 Micron Technology, Inc. Elongated fasteners for securing together electronic components and substrates, semiconductor device assemblies including such fasteners, and accompanying systems
US7304859B2 (en) * 2006-03-30 2007-12-04 Stats Chippac Ltd. Chip carrier and fabrication method
US7724589B2 (en) 2006-07-31 2010-05-25 Google Inc. System and method for delaying a signal communicated from a system to at least one of a plurality of memory circuits
JP2008042077A (ja) * 2006-08-09 2008-02-21 Renesas Technology Corp 半導体装置及びその製造方法
US20080123318A1 (en) * 2006-11-08 2008-05-29 Atmel Corporation Multi-component electronic package with planarized embedded-components substrate
CN101211882B (zh) * 2006-12-31 2010-12-08 北京华旗资讯数码科技有限公司 印刷电路板与元件模块的封装结构及封装方法
US8604605B2 (en) 2007-01-05 2013-12-10 Invensas Corp. Microelectronic assembly with multi-layer support structure
US7863189B2 (en) * 2007-01-05 2011-01-04 International Business Machines Corporation Methods for fabricating silicon carriers with conductive through-vias with low stress and low defect density
US7965520B2 (en) * 2007-01-22 2011-06-21 Sony Ericsson Mobile Communications Ab Electronic device with flip module having low height
DE102007006462A1 (de) * 2007-02-05 2008-08-14 Siemens Ag Elektronische Schaltungsanordnung mit einer ersten und zweiten Leiterplatte
US9466545B1 (en) 2007-02-21 2016-10-11 Amkor Technology, Inc. Semiconductor package in package
US20080284037A1 (en) 2007-05-15 2008-11-20 Andry Paul S Apparatus and Methods for Constructing Semiconductor Chip Packages with Silicon Space Transformer Carriers
US8209479B2 (en) 2007-07-18 2012-06-26 Google Inc. Memory circuit system and method
US8080874B1 (en) 2007-09-14 2011-12-20 Google Inc. Providing additional space between an integrated circuit and a circuit board for positioning a component therebetween
US7915724B2 (en) * 2007-09-28 2011-03-29 Stats Chippac Ltd. Integrated circuit packaging system with base structure device
US8258614B2 (en) * 2007-11-12 2012-09-04 Stats Chippac Ltd. Integrated circuit package system with package integration
JP2009302212A (ja) 2008-06-11 2009-12-24 Fujitsu Microelectronics Ltd 半導体装置及びその製造方法
US8836115B1 (en) 2008-07-31 2014-09-16 Amkor Technology, Inc. Stacked inverted flip chip package and fabrication method
US8076587B2 (en) * 2008-09-26 2011-12-13 Siemens Energy, Inc. Printed circuit board for harsh environments
US20100244276A1 (en) * 2009-03-25 2010-09-30 Lsi Corporation Three-dimensional electronics package
US8804368B2 (en) * 2009-04-30 2014-08-12 Sony Corporation Downward-facing optical component module
EP2441007A1 (de) 2009-06-09 2012-04-18 Google, Inc. Programmierung von dimm-abschlusswiderstandswerten
US8227904B2 (en) 2009-06-24 2012-07-24 Intel Corporation Multi-chip package and method of providing die-to-die interconnects in same
CN102130098B (zh) 2010-01-20 2015-11-25 飞思卡尔半导体公司 双管芯半导体封装
US8278756B2 (en) * 2010-02-24 2012-10-02 Inpaq Technology Co., Ltd. Single chip semiconductor coating structure and manufacturing method thereof
US8590387B2 (en) * 2011-03-31 2013-11-26 DePuy Synthes Products, LLC Absolute capacitive micro pressure sensor
TWI435667B (zh) * 2012-04-13 2014-04-21 Quanta Comp Inc 印刷電路板組件
KR101387208B1 (ko) * 2012-06-04 2014-04-29 삼성전기주식회사 임베디드 기판 제조방법 및 임베디드 기판
EP2811427A1 (de) * 2013-06-07 2014-12-10 Gemalto SA Herstellungsverfahren einer reißfesten elektronischen Vorrichtung
KR20150025129A (ko) * 2013-08-28 2015-03-10 삼성전기주식회사 전자 소자 모듈 및 그 제조 방법
US20150255411A1 (en) * 2014-03-05 2015-09-10 Omkar G. Karhade Die-to-die bonding and associated package configurations
US10141201B2 (en) * 2014-06-13 2018-11-27 Taiwan Semiconductor Manufacturing Company Integrated circuit packages and methods of forming same
US20150380392A1 (en) * 2014-06-27 2015-12-31 Apple Inc. Package with memory die and logic die interconnected in a face-to-face configuration
CN106960799B (zh) * 2016-01-12 2022-11-22 恩智浦美国有限公司 集成电路装置及其三维扇出结构和制造方法
EP3582259B1 (de) * 2018-06-11 2021-11-03 AT & S Austria Technologie & Systemtechnik Aktiengesellschaft Gestufte baugruppe, die in einem gestuften hohlraum in einem baugruppenträger untergebracht ist
US11862983B1 (en) 2019-03-28 2024-01-02 Roger W. Graham Earth energy systems and devices
JP7268544B2 (ja) * 2019-08-30 2023-05-08 富士通株式会社 電気チップ及び光モジュール
CN110759311A (zh) * 2019-10-29 2020-02-07 太极半导体（苏州）有限公司 一种基于窗口式基板的无引线mems芯片封装结构及其工艺
KR20220001311A (ko) * 2020-06-29 2022-01-05 삼성전자주식회사 반도체 패키지, 및 이를 가지는 패키지 온 패키지
US20230243049A1 (en) * 2020-12-02 2023-08-03 Tsuyoshi Funatsu Oxygen-hydrogen mixed gas generation device
KR102488845B1 (ko) * 2021-03-29 2023-01-17 김성록 수소 산소 혼합가스 발생장치
CN115444426B (zh) * 2022-11-09 2023-04-28 之江实验室 片上电极集成的无线肌电SoC系统、芯片及采集装置

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB2098398A (en) * 1981-05-13 1982-11-17 Honeywell Ltd Electronic packaging system
FR2535110B1 (fr) * 1982-10-20 1986-07-25 Radiotechnique Compelec Procede d'encapsulation d'un composant semi-conducteur dans un circuit electronique realise sur substrat et application aux circuits integres rapides
US4903120A (en) * 1985-11-22 1990-02-20 Texas Instruments Incorporated Chip carrier with interconnects on lid
US4843188A (en) * 1986-03-25 1989-06-27 Western Digital Corporation Integrated circuit chip mounting and packaging assembly
US5138436A (en) * 1990-11-16 1992-08-11 Ball Corporation Interconnect package having means for waveguide transmission of rf signals
JPH0513659A (ja) * 1991-07-03 1993-01-22 Hitachi Ltd 半導体集積回路装置の製造方法

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TW376574B (en) 1999-12-11
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