DE69622960T2 - Verfahren und Vorrichtung zur Übertragung und Verarbeitung virtueller Befehle - Google Patents

Verfahren und Vorrichtung zur Übertragung und Verarbeitung virtueller Befehle

Info

Publication number
DE69622960T2
DE69622960T2 DE69622960T DE69622960T DE69622960T2 DE 69622960 T2 DE69622960 T2 DE 69622960T2 DE 69622960 T DE69622960 T DE 69622960T DE 69622960 T DE69622960 T DE 69622960T DE 69622960 T2 DE69622960 T2 DE 69622960T2
Authority
DE
Germany
Prior art keywords
transmitting
processing virtual
virtual commands
commands
processing
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE69622960T
Other languages
English (en)
Other versions
DE69622960D1 (de
Inventor
Denny E Gentry
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sun Microsystems Inc
Original Assignee
Sun Microsystems Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sun Microsystems Inc filed Critical Sun Microsystems Inc
Application granted granted Critical
Publication of DE69622960D1 publication Critical patent/DE69622960D1/de
Publication of DE69622960T2 publication Critical patent/DE69622960T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/10—Program control for peripheral devices
    • G06F13/12—Program control for peripheral devices using hardware independent of the central processor, e.g. channel or peripheral processor
    • G06F13/124—Program control for peripheral devices using hardware independent of the central processor, e.g. channel or peripheral processor where hardware is a sequential transfer control unit, e.g. microprocessor, peripheral processor or state-machine
    • G06F13/126—Program control for peripheral devices using hardware independent of the central processor, e.g. channel or peripheral processor where hardware is a sequential transfer control unit, e.g. microprocessor, peripheral processor or state-machine and has means for transferring I/O instructions and statuses between control unit and main processor
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/10—Program control for peripheral devices
DE69622960T 1995-11-03 1996-10-23 Verfahren und Vorrichtung zur Übertragung und Verarbeitung virtueller Befehle Expired - Fee Related DE69622960T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US08/552,802 US5848293A (en) 1995-11-03 1995-11-03 Method and apparatus for transmission and processing of virtual commands

Publications (2)

Publication Number Publication Date
DE69622960D1 DE69622960D1 (de) 2002-09-19
DE69622960T2 true DE69622960T2 (de) 2002-12-19

Family

ID=24206871

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69622960T Expired - Fee Related DE69622960T2 (de) 1995-11-03 1996-10-23 Verfahren und Vorrichtung zur Übertragung und Verarbeitung virtueller Befehle

Country Status (4)

Country Link
US (1) US5848293A (de)
EP (1) EP0772130B1 (de)
JP (1) JPH09325947A (de)
DE (1) DE69622960T2 (de)

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US6205501B1 (en) * 1998-01-07 2001-03-20 National Semiconductor Corp. Apparatus and method for handling universal serial bus control transfers
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US6070208A (en) * 1998-01-07 2000-05-30 National Semiconductor Corporation Apparatus and method for implementing a versatile USB endpoint pipe
US6353866B1 (en) 1998-01-07 2002-03-05 National Semiconductor Corporation Apparatus and method for initializing a universal serial bus device
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US6400717B1 (en) * 1998-10-16 2002-06-04 Samsung Electronics Co., Ltd. Device for booting a multiprocessor embedded system and method of operation
US6360278B1 (en) * 1999-05-27 2002-03-19 3Com Corporation FIFO queued entry point circuit for a network interface card
US6584511B1 (en) * 2000-03-24 2003-06-24 Unisys Corporation Loop initialization procedure exception handling for fibre channel transmissions
US8019901B2 (en) 2000-09-29 2011-09-13 Alacritech, Inc. Intelligent network storage interface system
US7543087B2 (en) 2002-04-22 2009-06-02 Alacritech, Inc. Freeing transmit memory on a network interface device prior to receiving an acknowledgement that transmit data has been received by a remote device
US7496689B2 (en) 2002-04-22 2009-02-24 Alacritech, Inc. TCP/IP offload device
US7191241B2 (en) 2002-09-27 2007-03-13 Alacritech, Inc. Fast-path apparatus for receiving data corresponding to a TCP connection
US7337241B2 (en) 2002-09-27 2008-02-26 Alacritech, Inc. Fast-path apparatus for receiving data corresponding to a TCP connection
US8248939B1 (en) 2004-10-08 2012-08-21 Alacritech, Inc. Transferring control of TCP connections between hierarchy of processing mechanisms
US7738500B1 (en) 2005-12-14 2010-06-15 Alacritech, Inc. TCP timestamp synchronization for network connections that are offloaded to network interface devices
US8539513B1 (en) 2008-04-01 2013-09-17 Alacritech, Inc. Accelerating data transfer in a virtual computer system with tightly coupled TCP connections
US8341286B1 (en) 2008-07-31 2012-12-25 Alacritech, Inc. TCP offload send optimization
US9306793B1 (en) 2008-10-22 2016-04-05 Alacritech, Inc. TCP offload device that batches session layer headers to reduce interrupts as well as CPU copies
US9213665B2 (en) * 2008-10-28 2015-12-15 Freescale Semiconductor, Inc. Data processor for processing a decorated storage notify
US8627471B2 (en) * 2008-10-28 2014-01-07 Freescale Semiconductor, Inc. Permissions checking for data processing instructions
US8266498B2 (en) * 2009-03-31 2012-09-11 Freescale Semiconductor, Inc. Implementation of multiple error detection schemes for a cache
US8990660B2 (en) 2010-09-13 2015-03-24 Freescale Semiconductor, Inc. Data processing system having end-to-end error correction and method therefor
US8504777B2 (en) 2010-09-21 2013-08-06 Freescale Semiconductor, Inc. Data processor for processing decorated instructions with cache bypass
US8566672B2 (en) 2011-03-22 2013-10-22 Freescale Semiconductor, Inc. Selective checkbit modification for error correction
US8607121B2 (en) 2011-04-29 2013-12-10 Freescale Semiconductor, Inc. Selective error detection and error correction for a memory interface
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Also Published As

Publication number Publication date
JPH09325947A (ja) 1997-12-16
US5848293A (en) 1998-12-08
DE69622960D1 (de) 2002-09-19
EP0772130A1 (de) 1997-05-07
EP0772130B1 (de) 2002-08-14

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Legal Events

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8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee