DE69617147D1 - Verfahren zur Herstellung dünner Halbleiterschichten - Google Patents

Verfahren zur Herstellung dünner Halbleiterschichten

Info

Publication number
DE69617147D1
DE69617147D1 DE69617147T DE69617147T DE69617147D1 DE 69617147 D1 DE69617147 D1 DE 69617147D1 DE 69617147 T DE69617147 T DE 69617147T DE 69617147 T DE69617147 T DE 69617147T DE 69617147 D1 DE69617147 D1 DE 69617147D1
Authority
DE
Germany
Prior art keywords
production
semiconductor layers
thin semiconductor
thin
layers
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE69617147T
Other languages
English (en)
Other versions
DE69617147T2 (de
Inventor
Michel Bruel
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Commissariat a lEnergie Atomique et aux Energies Alternatives CEA
Original Assignee
Commissariat a lEnergie Atomique CEA
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Commissariat a lEnergie Atomique CEA filed Critical Commissariat a lEnergie Atomique CEA
Publication of DE69617147D1 publication Critical patent/DE69617147D1/de
Application granted granted Critical
Publication of DE69617147T2 publication Critical patent/DE69617147T2/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/26Bombardment with radiation
    • H01L21/263Bombardment with radiation with high-energy radiation
    • H01L21/265Bombardment with radiation with high-energy radiation producing ion implantation
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76Making of isolation regions between components
    • H01L21/762Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • H01L21/76251Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques
    • H01L21/76254Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques with separation/delamination along an ion implanted layer, e.g. Smart-cut, Unibond
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02002Preparing wafers
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02002Preparing wafers
    • H01L21/02005Preparing bulk and homogeneous wafers
    • YGENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10STECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S438/00Semiconductor device manufacturing: process
    • Y10S438/977Thinning or removal of substrate
DE69617147T 1995-09-13 1996-09-10 Verfahren zur Herstellung dünner Halbleiterschichten Expired - Lifetime DE69617147T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
FR9510718A FR2738671B1 (fr) 1995-09-13 1995-09-13 Procede de fabrication de films minces a materiau semiconducteur

Publications (2)

Publication Number Publication Date
DE69617147D1 true DE69617147D1 (de) 2002-01-03
DE69617147T2 DE69617147T2 (de) 2002-07-04

Family

ID=9482495

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69617147T Expired - Lifetime DE69617147T2 (de) 1995-09-13 1996-09-10 Verfahren zur Herstellung dünner Halbleiterschichten

Country Status (6)

Country Link
US (1) US5714395A (de)
EP (1) EP0763849B1 (de)
JP (1) JP4049834B2 (de)
KR (1) KR100400684B1 (de)
DE (1) DE69617147T2 (de)
FR (1) FR2738671B1 (de)

Families Citing this family (300)

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DE69617147T2 (de) 2002-07-04
KR970018021A (ko) 1997-04-30
KR100400684B1 (ko) 2004-01-14
US5714395A (en) 1998-02-03
EP0763849A1 (de) 1997-03-19
EP0763849B1 (de) 2001-11-21

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