DE69610714T2 - System, architektur und verfahren mit hoher leistung für einen universellen multiport dynamischen direktzugriffspeicher mit internem cache-speicher - Google Patents

System, architektur und verfahren mit hoher leistung für einen universellen multiport dynamischen direktzugriffspeicher mit internem cache-speicher

Info

Publication number
DE69610714T2
DE69610714T2 DE69610714T DE69610714T DE69610714T2 DE 69610714 T2 DE69610714 T2 DE 69610714T2 DE 69610714 T DE69610714 T DE 69610714T DE 69610714 T DE69610714 T DE 69610714T DE 69610714 T2 DE69610714 T2 DE 69610714T2
Authority
DE
Germany
Prior art keywords
architecture
high performance
memory
access memory
direct access
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE69610714T
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English (en)
Other versions
DE69610714D1 (de
Inventor
Mukesh Chatter
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Individual
Original Assignee
Individual
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Individual filed Critical Individual
Publication of DE69610714D1 publication Critical patent/DE69610714D1/de
Application granted granted Critical
Publication of DE69610714T2 publication Critical patent/DE69610714T2/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1075—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers for multiport memories each having random access ports and serial ports, e.g. video RAM
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0893—Caches characterised by their organisation or structure
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/16—Handling requests for interconnection or transfer for access to memory bus
DE69610714T 1995-12-29 1996-08-12 System, architektur und verfahren mit hoher leistung für einen universellen multiport dynamischen direktzugriffspeicher mit internem cache-speicher Expired - Lifetime DE69610714T2 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US08/581,467 US5799209A (en) 1995-12-29 1995-12-29 Multi-port internally cached DRAM system utilizing independent serial interfaces and buffers arbitratively connected under a dynamic configuration
PCT/IB1996/000794 WO1997024725A1 (en) 1995-12-29 1996-08-12 High performance universal multi-port internally cached dynamic random access memory system, architecture and method

Publications (2)

Publication Number Publication Date
DE69610714D1 DE69610714D1 (de) 2000-11-23
DE69610714T2 true DE69610714T2 (de) 2001-05-10

Family

ID=24325313

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69610714T Expired - Lifetime DE69610714T2 (de) 1995-12-29 1996-08-12 System, architektur und verfahren mit hoher leistung für einen universellen multiport dynamischen direktzugriffspeicher mit internem cache-speicher

Country Status (15)

Country Link
US (2) US5799209A (de)
EP (1) EP0870303B1 (de)
JP (1) JP3699126B2 (de)
KR (1) KR100328603B1 (de)
CN (1) CN1120495C (de)
AT (1) ATE197101T1 (de)
AU (1) AU721764B2 (de)
CA (1) CA2241841C (de)
DE (1) DE69610714T2 (de)
DK (1) DK0870303T3 (de)
GR (1) GR3035261T3 (de)
HK (1) HK1018342A1 (de)
IL (1) IL125135A (de)
TW (1) TW318222B (de)
WO (1) WO1997024725A1 (de)

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Also Published As

Publication number Publication date
EP0870303A1 (de) 1998-10-14
US5799209A (en) 1998-08-25
CN1209213A (zh) 1999-02-24
CN1120495C (zh) 2003-09-03
US6108725A (en) 2000-08-22
DK0870303T3 (da) 2001-02-26
EP0870303B1 (de) 2000-10-18
AU721764B2 (en) 2000-07-13
WO1997024725A1 (en) 1997-07-10
ATE197101T1 (de) 2000-11-15
IL125135A (en) 2002-12-01
DE69610714D1 (de) 2000-11-23
CA2241841A1 (en) 1997-07-10
CA2241841C (en) 1999-10-26
KR19990076893A (ko) 1999-10-25
HK1018342A1 (en) 1999-12-17
GR3035261T3 (en) 2001-04-30
AU6529596A (en) 1997-07-28
KR100328603B1 (ko) 2002-10-19
TW318222B (de) 1997-10-21
JP3699126B2 (ja) 2005-09-28
IL125135A0 (en) 1999-01-26
JP2000501524A (ja) 2000-02-08

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