DE69528409D1 - Verfahren zur Herstellung von Löchern in einer dielektrischen Schicht mit niedriger Dielektrizitätskonstante auf einer Halbleitervorrichtung - Google Patents
Verfahren zur Herstellung von Löchern in einer dielektrischen Schicht mit niedriger Dielektrizitätskonstante auf einer HalbleitervorrichtungInfo
- Publication number
- DE69528409D1 DE69528409D1 DE69528409T DE69528409T DE69528409D1 DE 69528409 D1 DE69528409 D1 DE 69528409D1 DE 69528409 T DE69528409 T DE 69528409T DE 69528409 T DE69528409 T DE 69528409T DE 69528409 D1 DE69528409 D1 DE 69528409D1
- Authority
- DE
- Germany
- Prior art keywords
- semiconductor device
- dielectric layer
- dielectric constant
- producing holes
- low dielectric
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
- H01L21/76834—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers formation of thin insulating films on the sidewalls or on top of conductors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
- H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
- H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
- H01L21/02164—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material being a silicon oxide, e.g. SiO2
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
- H01L21/02205—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates the layer being characterised by the precursor material for deposition
- H01L21/02208—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates the layer being characterised by the precursor material for deposition the precursor containing a compound comprising Si
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/312—Organic layers, e.g. photoresist
- H01L21/3121—Layers comprising organo-silicon compounds
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/314—Inorganic layers
- H01L21/316—Inorganic layers composed of oxides or glassy oxides or oxide based glass
- H01L21/31604—Deposition from a gas or vapour
- H01L21/31608—Deposition of SiO2
- H01L21/31612—Deposition of SiO2 on a silicon body
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10S148/00—Metal treatment
- Y10S148/051—Etching
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US08/234,100 US5565384A (en) | 1994-04-28 | 1994-04-28 | Self-aligned via using low permittivity dielectric |
Publications (2)
Publication Number | Publication Date |
---|---|
DE69528409D1 true DE69528409D1 (de) | 2002-11-07 |
DE69528409T2 DE69528409T2 (de) | 2003-08-21 |
Family
ID=22879931
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
DE69528409T Expired - Fee Related DE69528409T2 (de) | 1994-04-28 | 1995-04-28 | Verfahren zur Herstellung von Löchern in einer dielektrischen Schicht mit niedriger Dielektrizitätskonstante auf einer Halbleitervorrichtung |
Country Status (6)
Country | Link |
---|---|
US (1) | US5565384A (de) |
EP (1) | EP0680084B1 (de) |
JP (1) | JPH0851154A (de) |
KR (1) | KR950034532A (de) |
DE (1) | DE69528409T2 (de) |
TW (1) | TW299484B (de) |
Families Citing this family (69)
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US6278174B1 (en) * | 1994-04-28 | 2001-08-21 | Texas Instruments Incorporated | Integrated circuit insulator and structure using low dielectric insulator material including HSQ and fluorinated oxide |
US5488015A (en) * | 1994-05-20 | 1996-01-30 | Texas Instruments Incorporated | Method of making an interconnect structure with an integrated low density dielectric |
US7294578B1 (en) * | 1995-06-02 | 2007-11-13 | Micron Technology, Inc. | Use of a plasma source to form a layer during the formation of a semiconductor device |
US6716769B1 (en) | 1995-06-02 | 2004-04-06 | Micron Technology, Inc. | Use of a plasma source to form a layer during the formation of a semiconductor device |
JPH0936226A (ja) * | 1995-07-18 | 1997-02-07 | Nec Corp | 半導体装置およびその製造方法 |
TW439003B (en) * | 1995-11-17 | 2001-06-07 | Semiconductor Energy Lab | Display device |
JPH1041382A (ja) * | 1996-04-29 | 1998-02-13 | Texas Instr Inc <Ti> | 集積回路レベル間絶縁構造 |
US5854131A (en) * | 1996-06-05 | 1998-12-29 | Advanced Micro Devices, Inc. | Integrated circuit having horizontally and vertically offset interconnect lines |
KR100192589B1 (ko) * | 1996-08-08 | 1999-06-15 | 윤종용 | 반도체 장치 및 그 제조방법 |
US6136700A (en) * | 1996-12-20 | 2000-10-24 | Texas Instruments Incorporated | Method for enhancing the performance of a contact |
US6303488B1 (en) * | 1997-02-12 | 2001-10-16 | Micron Technology, Inc. | Semiconductor processing methods of forming openings to devices and substrates, exposing material from which photoresist cannot be substantially selectively removed |
US6849557B1 (en) | 1997-04-30 | 2005-02-01 | Micron Technology, Inc. | Undoped silicon dioxide as etch stop for selective etch of doped silicon dioxide |
US6010957A (en) * | 1997-06-25 | 2000-01-04 | Advanced Micro Devices | Semiconductor device having tapered conductive lines and fabrication thereof |
JP3390329B2 (ja) * | 1997-06-27 | 2003-03-24 | 日本電気株式会社 | 半導体装置およびその製造方法 |
GB2350931B (en) * | 1997-06-27 | 2001-03-14 | Nec Corp | Method of manufacturing semiconductor device having multilayer wiring |
US6048803A (en) * | 1997-08-19 | 2000-04-11 | Advanced Microdevices, Inc. | Method of fabricating a semiconductor device having fluorine bearing oxide between conductive lines |
US6875681B1 (en) * | 1997-12-31 | 2005-04-05 | Intel Corporation | Wafer passivation structure and method of fabrication |
US6143649A (en) * | 1998-02-05 | 2000-11-07 | Micron Technology, Inc. | Method for making semiconductor devices having gradual slope contacts |
KR100283028B1 (ko) * | 1998-03-19 | 2001-03-02 | 윤종용 | 디램 셀 캐패시터의 제조 방법 |
KR20010042419A (ko) | 1998-04-02 | 2001-05-25 | 조셉 제이. 스위니 | 낮은 k 유전체를 에칭하는 방법 |
US6287751B2 (en) * | 1998-05-12 | 2001-09-11 | United Microelectronics Corp. | Method of fabricating contact window |
US6175147B1 (en) * | 1998-05-14 | 2001-01-16 | Micron Technology Inc. | Device isolation for semiconductor devices |
JP3208376B2 (ja) * | 1998-05-20 | 2001-09-10 | 株式会社半導体プロセス研究所 | 成膜方法及び半導体装置の製造方法 |
TW389988B (en) * | 1998-05-22 | 2000-05-11 | United Microelectronics Corp | Method for forming metal interconnect in dielectric layer with low dielectric constant |
US6007733A (en) * | 1998-05-29 | 1999-12-28 | Taiwan Semiconductor Manufacturing Company | Hard masking method for forming oxygen containing plasma etchable layer |
US6492276B1 (en) | 1998-05-29 | 2002-12-10 | Taiwan Semiconductor Manufacturing Company | Hard masking method for forming residue free oxygen containing plasma etched layer |
US6019906A (en) * | 1998-05-29 | 2000-02-01 | Taiwan Semiconductor Manufacturing Company | Hard masking method for forming patterned oxygen containing plasma etchable layer |
US6232235B1 (en) * | 1998-06-03 | 2001-05-15 | Motorola, Inc. | Method of forming a semiconductor device |
US6323118B1 (en) | 1998-07-13 | 2001-11-27 | Taiwan Semiconductor For Manufacturing Company | Borderless dual damascene contact |
US6440863B1 (en) * | 1998-09-04 | 2002-08-27 | Taiwan Semiconductor Manufacturing Company | Plasma etch method for forming patterned oxygen containing plasma etchable layer |
US6174800B1 (en) | 1998-09-08 | 2001-01-16 | Taiwan Semiconductor Manufacturing Company | Via formation in a poly(arylene ether) inter metal dielectric layer |
US6187672B1 (en) * | 1998-09-22 | 2001-02-13 | Conexant Systems, Inc. | Interconnect with low dielectric constant insulators for semiconductor integrated circuit manufacturing |
US6245663B1 (en) * | 1998-09-30 | 2001-06-12 | Conexant Systems, Inc. | IC interconnect structures and methods for making same |
US6228758B1 (en) * | 1998-10-14 | 2001-05-08 | Advanced Micro Devices, Inc. | Method of making dual damascene conductive interconnections and integrated circuit device comprising same |
US6004883A (en) * | 1998-10-23 | 1999-12-21 | Taiwan Semiconductor Manufacturing Company, Ltd. | Dual damascene patterned conductor layer formation method without etch stop layer |
US6165898A (en) * | 1998-10-23 | 2000-12-26 | Taiwan Semiconductor Manufacturing Company | Dual damascene patterned conductor layer formation method without etch stop layer |
US6265308B1 (en) | 1998-11-30 | 2001-07-24 | International Business Machines Corporation | Slotted damascene lines for low resistive wiring lines for integrated circuit |
US6495468B2 (en) | 1998-12-22 | 2002-12-17 | Micron Technology, Inc. | Laser ablative removal of photoresist |
US6417090B1 (en) * | 1999-01-04 | 2002-07-09 | Advanced Micro Devices, Inc. | Damascene arrangement for metal interconnection using low k dielectric constant materials for etch stop layer |
US6255232B1 (en) | 1999-02-11 | 2001-07-03 | Taiwan Semiconductor Manufacturing Company | Method for forming low dielectric constant spin-on-polymer (SOP) dielectric layer |
US6114253A (en) * | 1999-03-15 | 2000-09-05 | Taiwan Semiconductor Manufacturing Company | Via patterning for poly(arylene ether) used as an inter-metal dielectric |
US6211063B1 (en) | 1999-05-25 | 2001-04-03 | Taiwan Semiconductor Manufacturing Company | Method to fabricate self-aligned dual damascene structures |
US20030205815A1 (en) * | 1999-06-09 | 2003-11-06 | Henry Chung | Fabrication method of integrated circuits with borderless vias and low dielectric constant inter-metal dielectrics |
JP2001007202A (ja) * | 1999-06-22 | 2001-01-12 | Sony Corp | 半導体装置の製造方法 |
US6498399B2 (en) * | 1999-09-08 | 2002-12-24 | Alliedsignal Inc. | Low dielectric-constant dielectric for etchstop in dual damascene backend of integrated circuits |
JP3430091B2 (ja) * | 1999-12-01 | 2003-07-28 | Necエレクトロニクス株式会社 | エッチングマスク及びエッチングマスクを用いたコンタクトホールの形成方法並びにその方法で形成した半導体装置 |
US6432833B1 (en) | 1999-12-20 | 2002-08-13 | Micron Technology, Inc. | Method of forming a self aligned contact opening |
US6531389B1 (en) | 1999-12-20 | 2003-03-11 | Taiwan Semiconductor Manufacturing Company | Method for forming incompletely landed via with attenuated contact resistance |
AU2761301A (en) | 2000-01-03 | 2001-07-16 | Micron Technology, Inc. | Method of forming a self-aligned contact opening |
US6348706B1 (en) * | 2000-03-20 | 2002-02-19 | Micron Technology, Inc. | Method to form etch and/or CMP stop layers |
JP4149644B2 (ja) * | 2000-08-11 | 2008-09-10 | 株式会社東芝 | 不揮発性半導体記憶装置 |
EP1837902B1 (de) * | 2000-08-21 | 2017-05-24 | Dow Global Technologies LLC | Verwendung von Organosilikat-Harzen als Masken für organische Polymerdielektrika bei der Herstellung mikroelektronischer Geräte |
US6617239B1 (en) * | 2000-08-31 | 2003-09-09 | Micron Technology, Inc. | Subtractive metallization structure and method of making |
US7172960B2 (en) * | 2000-12-27 | 2007-02-06 | Intel Corporation | Multi-layer film stack for extinction of substrate reflections during patterning |
US6803314B2 (en) * | 2001-04-30 | 2004-10-12 | Chartered Semiconductor Manufacturing Ltd. | Double-layered low dielectric constant dielectric dual damascene method |
US6989108B2 (en) | 2001-08-30 | 2006-01-24 | Micron Technology, Inc. | Etchant gas composition |
US20030096090A1 (en) * | 2001-10-22 | 2003-05-22 | Boisvert Ronald Paul | Etch-stop resins |
KR100704469B1 (ko) * | 2001-12-14 | 2007-04-09 | 주식회사 하이닉스반도체 | 반도체 소자 제조 방법 |
JP2004071705A (ja) * | 2002-08-02 | 2004-03-04 | Fujitsu Ltd | 半導体装置及び半導体装置の製造方法 |
JP2004274020A (ja) * | 2002-09-24 | 2004-09-30 | Rohm & Haas Electronic Materials Llc | 電子デバイス製造 |
KR100480636B1 (ko) * | 2002-11-22 | 2005-03-31 | 삼성전자주식회사 | 반도체 장치의 제조방법 |
US9515135B2 (en) * | 2003-01-15 | 2016-12-06 | Cree, Inc. | Edge termination structures for silicon carbide devices |
US7026650B2 (en) | 2003-01-15 | 2006-04-11 | Cree, Inc. | Multiple floating guard ring edge termination for silicon carbide devices |
US7109092B2 (en) | 2003-05-19 | 2006-09-19 | Ziptronix, Inc. | Method of room temperature covalent bonding |
US7183187B2 (en) * | 2004-05-20 | 2007-02-27 | Texas Instruments Incorporated | Integration scheme for using silicided dual work function metal gates |
US7235489B2 (en) * | 2004-05-21 | 2007-06-26 | Agere Systems Inc. | Device and method to eliminate shorting induced by via to metal misalignment |
JP5134193B2 (ja) * | 2005-07-15 | 2013-01-30 | 株式会社東芝 | 半導体装置及びその製造方法 |
KR100685735B1 (ko) * | 2005-08-11 | 2007-02-26 | 삼성전자주식회사 | 폴리실리콘 제거용 조성물, 이를 이용한 폴리실리콘 제거방법 및 반도체 장치의 제조 방법 |
EP3217425B1 (de) | 2016-03-07 | 2021-09-15 | IMEC vzw | Selbstjustierte interconnects und zugehöriges verfahren |
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DE3345C (de) * | HÜSMERT & CO. in Wald bei Solingen | Bügelverschlufs an Handtaschen etc | ||
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JPH0715938B2 (ja) * | 1985-05-23 | 1995-02-22 | 日本電信電話株式会社 | 半導体装置およびその製造方法 |
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JPH0612790B2 (ja) * | 1987-02-24 | 1994-02-16 | 日本電気株式会社 | 半導体装置 |
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JPH04127454A (ja) * | 1990-09-18 | 1992-04-28 | Nec Corp | 半導体装置 |
JPH04311059A (ja) * | 1991-04-09 | 1992-11-02 | Oki Electric Ind Co Ltd | 配線容量の低減方法 |
US5246883A (en) * | 1992-02-06 | 1993-09-21 | Sgs-Thomson Microelectronics, Inc. | Semiconductor contact via structure and method |
US5371047A (en) * | 1992-10-30 | 1994-12-06 | International Business Machines Corporation | Chip interconnection having a breathable etch stop layer |
US5393712A (en) * | 1993-06-28 | 1995-02-28 | Lsi Logic Corporation | Process for forming low dielectric constant insulation layer on integrated circuit structure |
-
1994
- 1994-04-28 US US08/234,100 patent/US5565384A/en not_active Expired - Lifetime
-
1995
- 1995-04-27 KR KR19950010065A patent/KR950034532A/ko active IP Right Grant
- 1995-04-27 JP JP7104296A patent/JPH0851154A/ja active Pending
- 1995-04-28 EP EP95106395A patent/EP0680084B1/de not_active Expired - Lifetime
- 1995-04-28 DE DE69528409T patent/DE69528409T2/de not_active Expired - Fee Related
- 1995-06-08 TW TW084105790A patent/TW299484B/zh not_active IP Right Cessation
Also Published As
Publication number | Publication date |
---|---|
TW299484B (de) | 1997-03-01 |
JPH0851154A (ja) | 1996-02-20 |
EP0680084A1 (de) | 1995-11-02 |
US5565384A (en) | 1996-10-15 |
EP0680084B1 (de) | 2002-10-02 |
DE69528409T2 (de) | 2003-08-21 |
KR950034532A (de) | 1995-12-28 |
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