DE69523189D1 - Bus-Master-Arbitrierungsschaltung mit Wiederholungsmechanismus - Google Patents

Bus-Master-Arbitrierungsschaltung mit Wiederholungsmechanismus

Info

Publication number
DE69523189D1
DE69523189D1 DE69523189T DE69523189T DE69523189D1 DE 69523189 D1 DE69523189 D1 DE 69523189D1 DE 69523189 T DE69523189 T DE 69523189T DE 69523189 T DE69523189 T DE 69523189T DE 69523189 D1 DE69523189 D1 DE 69523189D1
Authority
DE
Germany
Prior art keywords
bus
priority
retried
arbiter
access
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE69523189T
Other languages
English (en)
Other versions
DE69523189T2 (de
Inventor
Maria L Melo
Randy M Bonella
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Compaq Computer Corp
Original Assignee
Compaq Computer Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Compaq Computer Corp filed Critical Compaq Computer Corp
Publication of DE69523189D1 publication Critical patent/DE69523189D1/de
Application granted granted Critical
Publication of DE69523189T2 publication Critical patent/DE69523189T2/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/36—Handling requests for interconnection or transfer for access to common bus or bus system
    • G06F13/362—Handling requests for interconnection or transfer for access to common bus or bus system with centralised access control
    • G06F13/364—Handling requests for interconnection or transfer for access to common bus or bus system with centralised access control using independent requests or grants, e.g. using separated request and grant lines
DE69523189T 1994-01-28 1995-01-20 Bus-Master-Arbitrierungsschaltung mit Wiederholungsmechanismus Expired - Lifetime DE69523189T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US08/188,456 US5471590A (en) 1994-01-28 1994-01-28 Bus master arbitration circuitry having improved prioritization

Publications (2)

Publication Number Publication Date
DE69523189D1 true DE69523189D1 (de) 2001-11-22
DE69523189T2 DE69523189T2 (de) 2002-05-16

Family

ID=22693236

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69523189T Expired - Lifetime DE69523189T2 (de) 1994-01-28 1995-01-20 Bus-Master-Arbitrierungsschaltung mit Wiederholungsmechanismus

Country Status (6)

Country Link
US (1) US5471590A (de)
EP (1) EP0665500B1 (de)
JP (1) JP2596895B2 (de)
AT (1) ATE207218T1 (de)
CA (1) CA2140686C (de)
DE (1) DE69523189T2 (de)

Families Citing this family (72)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO1996008773A2 (en) * 1994-09-16 1996-03-21 Cirrus Logic, Inc. Pcmcia dma data bus mastering
US5611057A (en) * 1994-10-06 1997-03-11 Dell Usa, L.P. Computer system modular add-in daughter card for an adapter card which also functions as an independent add-in card
US5623691A (en) * 1994-11-14 1997-04-22 Compaq Computer Corporation PCI bus hard disk activity LED circuit
CA2160500C (en) * 1994-11-30 1999-11-09 Amy Kulik Pci/isa bridge having an arrangement for responding to pci bridge address parity errors for internal pci slaves in the pci/isa bridge
US5621902A (en) * 1994-11-30 1997-04-15 International Business Machines Corporation Computer system having a bridge between two buses with a direct memory access controller and an alternative memory access controller
US5623697A (en) * 1994-11-30 1997-04-22 International Business Machines Corporation Bridge between two buses of a computer system with a direct memory access controller having a high address extension and a high count extension
US5596729A (en) * 1995-03-03 1997-01-21 Compaq Computer Corporation First arbiter coupled to a first bus receiving requests from devices coupled to a second bus and controlled by a second arbiter on said second bus
US5729762A (en) * 1995-04-21 1998-03-17 Intel Corporation Input output controller having interface logic coupled to DMA controller and plurality of address lines for carrying control information to DMA agent
US5706446A (en) * 1995-05-18 1998-01-06 Unisys Corporation Arbitration system for bus requestors with deadlock prevention
US5644733A (en) * 1995-05-18 1997-07-01 Unisys Corporation Dual coupled partitionable networks providing arbitration logic for managed access to commonly shared busses
US5692219A (en) * 1995-06-07 1997-11-25 Dell Usa, Lp System and method for disabling or re-enabling PCI-compliant devices in a computer system by masking the idsel signal with a disable or re-enable signal
US5978860A (en) * 1995-06-07 1999-11-02 Dell Usa, L.P. System and method for disabling and re-enabling at least one peripheral device in a computer system by masking a device-configuration-space-access-signal with a disable or re-enable signal
JPH08339346A (ja) * 1995-06-09 1996-12-24 Toshiba Corp バスアービタ
US5805842A (en) * 1995-09-26 1998-09-08 Intel Corporation Apparatus, system and method for supporting DMA transfers on a multiplexed bus
US5935232A (en) * 1995-11-20 1999-08-10 Advanced Micro Devices, Inc. Variable latency and bandwidth communication pathways
US5754807A (en) * 1995-11-20 1998-05-19 Advanced Micro Devices, Inc. Computer system including a multimedia bus which utilizes a separate local expansion bus for addressing and control cycles
US5778200A (en) * 1995-11-21 1998-07-07 Advanced Micro Devices, Inc. Bus arbiter including aging factor counters to dynamically vary arbitration priority
JP3056989B2 (ja) * 1995-12-05 2000-06-26 インターナショナル・ビジネス・マシーンズ・コーポレイション 情報処理装置
US5943483A (en) * 1995-12-11 1999-08-24 Lsi Logic Corporation Method and apparatus for controlling access to a bus in a data processing system
US5787486A (en) * 1995-12-15 1998-07-28 International Business Machines Corporation Bus protocol for locked cycle cache hit
US5850530A (en) * 1995-12-18 1998-12-15 International Business Machines Corporation Method and apparatus for improving bus efficiency by enabling arbitration based upon availability of completion data
US5764929A (en) * 1995-12-18 1998-06-09 International Business Machines Corporation Method and apparatus for improving bus bandwidth by reducing redundant access attempts
US5859990A (en) * 1995-12-29 1999-01-12 Intel Corporation System for transferring data segments from a first storage device to a second storage device using an alignment stage including even and odd temporary devices
KR0167726B1 (ko) * 1996-01-30 1999-01-15 김광호 버스의 우선권 선택장치
US5956493A (en) * 1996-03-08 1999-09-21 Advanced Micro Devices, Inc. Bus arbiter including programmable request latency counters for varying arbitration priority
US5761452A (en) * 1996-03-18 1998-06-02 Advanced Micro Devices, Inc. Bus arbiter method and system
US5805840A (en) * 1996-03-26 1998-09-08 Advanced Micro Devices, Inc. Bus arbiter employing a transaction grading mechanism to dynamically vary arbitration priority
US5802330A (en) * 1996-05-01 1998-09-01 Advanced Micro Devices, Inc. Computer system including a plurality of real time peripheral devices having arbitration control feedback mechanisms
US6021480A (en) * 1996-06-05 2000-02-01 Compaq Computer Corporation Aligning a memory read request with a cache line boundary when the request is for data beginning at a location in the middle of the cache line
US5872939A (en) * 1996-06-05 1999-02-16 Compaq Computer Corporation Bus arbitration
US5987539A (en) * 1996-06-05 1999-11-16 Compaq Computer Corporation Method and apparatus for flushing a bridge device read buffer
US6052513A (en) * 1996-06-05 2000-04-18 Compaq Computer Corporation Multi-threaded bus master
US5872941A (en) * 1996-06-05 1999-02-16 Compaq Computer Corp. Providing data from a bridge to a requesting device while the bridge is receiving the data
US5903906A (en) * 1996-06-05 1999-05-11 Compaq Computer Corporation Receiving a write request that allows less than one cache line of data to be written and issuing a subsequent write request that requires at least one cache line of data to be written
US6035362A (en) * 1996-06-05 2000-03-07 Goodrum; Alan L. Storing data associated with one request while continuing to store data associated with a previous request from the same device
US6108741A (en) * 1996-06-05 2000-08-22 Maclaren; John M. Ordering transactions
US6055590A (en) * 1996-06-05 2000-04-25 Compaq Computer Corporation Bridge circuit comprising independent transaction buffers with control logic adapted to store overflow data in second buffer when transaction size exceeds the first buffer size
US6075929A (en) * 1996-06-05 2000-06-13 Compaq Computer Corporation Prefetching data in response to a read transaction for which the requesting device relinquishes control of the data bus while awaiting data requested in the transaction
US5873000A (en) * 1996-07-19 1999-02-16 Compaq Computer Corporation System incorporating hot docking and undocking capabilities without requiring a standby or suspend mode by placing local arbiters of system and base into idle state
US5954809A (en) * 1996-07-19 1999-09-21 Compaq Computer Corporation Circuit for handling distributed arbitration in a computer system having multiple arbiters
US6385678B2 (en) * 1996-09-19 2002-05-07 Trimedia Technologies, Inc. Method and apparatus for bus arbitration with weighted bandwidth allocation
JPH10116247A (ja) * 1996-10-15 1998-05-06 Nec Corp マイクロコンピュータ
US5887144A (en) * 1996-11-20 1999-03-23 International Business Machines Corp. Method and system for increasing the load and expansion capabilities of a bus through the use of in-line switches
US5761461A (en) * 1996-12-13 1998-06-02 International Business Machines Corporation Method and system for preventing peripheral component interconnect (PCI) peer-to-peer access across multiple PCI host bridges within a data processing system
US6138192A (en) * 1996-12-31 2000-10-24 Compaq Computer Corporation Delivering a request to write or read data before delivering an earlier write request
US5862353A (en) * 1997-03-25 1999-01-19 International Business Machines Corporation Systems and methods for dynamically controlling a bus
US6141715A (en) * 1997-04-03 2000-10-31 Micron Technology, Inc. Method and system for avoiding live lock conditions on a computer bus by insuring that the first retired bus master is the first to resubmit its retried transaction
US5905877A (en) * 1997-05-09 1999-05-18 International Business Machines Corporation PCI host bridge multi-priority fairness arbiter
US6076132A (en) * 1997-05-28 2000-06-13 Integrated Memory Logic, Inc. Arbitration method and circuit to increase access without increasing latency
US6327636B1 (en) * 1997-09-16 2001-12-04 International Business Machines Corporation Ordering for pipelined read transfers
US6073199A (en) * 1997-10-06 2000-06-06 Cisco Technology, Inc. History-based bus arbitration with hidden re-arbitration during wait cycles
US6178477B1 (en) * 1997-10-09 2001-01-23 Vlsi Technology, Inc. Method and system for pseudo delayed transactions through a bridge to guarantee access to a shared resource
US6199131B1 (en) * 1997-12-22 2001-03-06 Compaq Computer Corporation Computer system employing optimized delayed transaction arbitration technique
US6044061A (en) * 1998-03-10 2000-03-28 Cabletron Systems, Inc. Method and apparatus for fair and efficient scheduling of variable-size data packets in an input-buffered multipoint switch
JP2000040061A (ja) * 1998-05-20 2000-02-08 Oki Data Corp バス使用権調停システム
US6081861A (en) * 1998-06-15 2000-06-27 International Business Machines Corporation PCI migration support of ISA adapters
US6323755B1 (en) 1998-08-19 2001-11-27 International Business Machines Corporation Dynamic bus locking in a cross bar switch
US6275890B1 (en) 1998-08-19 2001-08-14 International Business Machines Corporation Low latency data path in a cross-bar switch providing dynamically prioritized bus arbitration
US6185221B1 (en) 1998-11-09 2001-02-06 Cabletron Systems, Inc. Method and apparatus for fair and efficient scheduling of variable-size data packets in an input-buffered multipoint switch
US6532507B1 (en) 1999-05-28 2003-03-11 National Semiconductor Corporation Digital signal processor and method for prioritized access by multiple core processors to shared device
US6718422B1 (en) * 1999-07-29 2004-04-06 International Business Machines Corporation Enhanced bus arbiter utilizing variable priority and fairness
US6742074B2 (en) * 1999-08-31 2004-05-25 Micron Technology, Inc. Bus to system memory delayed read processing
US6557087B1 (en) * 2000-02-22 2003-04-29 International Business Machines Corporation Management of PCI read access to a central resource
US7529268B1 (en) * 2001-09-27 2009-05-05 Hamilton Sundstrand Corporation Multi-point electronic control system protocol
JP2003281080A (ja) * 2002-03-20 2003-10-03 Matsushita Electric Ind Co Ltd データ転送制御装置
US6944698B2 (en) * 2002-07-08 2005-09-13 International Business Machines Corporation Method and apparatus for providing bus arbitrations in a data processing system
DE10234992A1 (de) 2002-07-31 2004-02-19 Advanced Micro Devices, Inc., Sunnyvale Retry-Mechanismus für blockierende Schnittstellen
US7099971B1 (en) * 2003-06-26 2006-08-29 Emc Corporation Arbitration system
US20060026329A1 (en) * 2004-07-30 2006-02-02 Yu James K System and method for an arbiter rewind
US7552268B2 (en) * 2006-05-18 2009-06-23 Cisco Technology, Inc. Method for improving bus utilization using predictive arbitration
US20090248919A1 (en) * 2008-03-25 2009-10-01 Jerzy Szwagrzyk Method for external fifo acceleration
US20160062930A1 (en) * 2013-03-25 2016-03-03 Mitsubishi Electric Corporation Bus master, bus system, and bus control method

Family Cites Families (17)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4574350A (en) * 1982-05-19 1986-03-04 At&T Bell Laboratories Shared resource locking apparatus
JPS58222361A (ja) * 1982-06-18 1983-12-24 Fujitsu Ltd デ−タ処理システムにおけるアクセス要求の優先順位決定制御方式
US4602327A (en) * 1983-07-28 1986-07-22 Motorola, Inc. Bus master capable of relinquishing bus on request and retrying bus cycle
US4706190A (en) * 1983-09-22 1987-11-10 Digital Equipment Corporation Retry mechanism for releasing control of a communications path in digital computer system
US5067071A (en) * 1985-02-27 1991-11-19 Encore Computer Corporation Multiprocessor computer system employing a plurality of tightly coupled processors with interrupt vector bus
US4663756A (en) * 1985-08-29 1987-05-05 Sperry Corporation Multiple-use priority network
US4785394A (en) * 1986-09-19 1988-11-15 Datapoint Corporation Fair arbitration technique for a split transaction bus in a multiprocessor computer system
US4858116A (en) * 1987-05-01 1989-08-15 Digital Equipment Corporation Method and apparatus for managing multiple lock indicators in a multiprocessor computer system
US4980854A (en) * 1987-05-01 1990-12-25 Digital Equipment Corporation Lookahead bus arbitration system with override of conditional access grants by bus cycle extensions for multicycle data transfers
US5341510A (en) * 1987-05-01 1994-08-23 Digital Equipment Corporation Commander node method and apparatus for assuring adequate access to system resources in a multiprocessor
US4987529A (en) * 1988-08-11 1991-01-22 Ast Research, Inc. Shared memory bus system for arbitrating access control among contending memory refresh circuits, peripheral controllers, and bus masters
US5167022A (en) * 1988-10-25 1992-11-24 Hewlett-Packard Company Multiprocessor bus locking system with a winning processor broadcasting an ownership signal causing all processors to halt their requests
US5127089A (en) * 1989-07-03 1992-06-30 Motorola, Inc. Synchronous bus lock mechanism permitting bus arbiter to change bus master during a plurality of successive locked operand transfer sequences after completion of current sequence
KR940002905B1 (en) * 1989-12-15 1994-04-07 Ibm Apparatus for conditioning priority arbitration in buffered direct memory addressing
US5265223A (en) * 1991-08-07 1993-11-23 Hewlett-Packard Company Preservation of priority in computer bus arbitration
EP0537899B1 (de) * 1991-09-27 1999-12-15 Sun Microsystems, Inc. Verklemmungserkennung und Maskierung enthaltende Busarbitrierungsarchitektur
DE69230462T2 (de) * 1991-11-19 2000-08-03 Sun Microsystems Inc Arbitrierung des Multiprozessorzugriffs zu gemeinsamen Mitteln

Also Published As

Publication number Publication date
EP0665500B1 (de) 2001-10-17
US5471590A (en) 1995-11-28
CA2140686A1 (en) 1995-07-29
JP2596895B2 (ja) 1997-04-02
EP0665500A1 (de) 1995-08-02
JPH07219892A (ja) 1995-08-18
DE69523189T2 (de) 2002-05-16
CA2140686C (en) 1999-02-02
ATE207218T1 (de) 2001-11-15

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