DE69503046D1 - Mehrfachbefehlssatzabbildung - Google Patents

Mehrfachbefehlssatzabbildung

Info

Publication number
DE69503046D1
DE69503046D1 DE69503046T DE69503046T DE69503046D1 DE 69503046 D1 DE69503046 D1 DE 69503046D1 DE 69503046 T DE69503046 T DE 69503046T DE 69503046 T DE69503046 T DE 69503046T DE 69503046 D1 DE69503046 D1 DE 69503046D1
Authority
DE
Germany
Prior art keywords
command set
multiple command
command
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE69503046T
Other languages
English (en)
Other versions
DE69503046T2 (de
Inventor
David Vivian Jaggar
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
ARM Ltd
Original Assignee
Advanced Risc Machines Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Advanced Risc Machines Ltd filed Critical Advanced Risc Machines Ltd
Publication of DE69503046D1 publication Critical patent/DE69503046D1/de
Application granted granted Critical
Publication of DE69503046T2 publication Critical patent/DE69503046T2/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/3017—Runtime instruction translation, e.g. macros
    • G06F9/30174—Runtime instruction translation, e.g. macros for non-native instruction set, e.g. Javabyte, legacy code
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30181—Instruction operation extension or modification
    • G06F9/30189—Instruction operation extension or modification according to execution mode, e.g. mode flag
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30181—Instruction operation extension or modification
    • G06F9/30196—Instruction operation extension or modification using decoder, e.g. decoder per instruction set, adaptable or programmable decoders
DE69503046T 1994-05-03 1995-02-15 Mehrfachbefehlssatzabbildung Expired - Lifetime DE69503046T2 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
GB9408873A GB2289354B (en) 1994-05-03 1994-05-03 Multiple instruction set mapping
PCT/GB1995/000314 WO1995030187A1 (en) 1994-05-03 1995-02-15 Multiple instruction set mapping

Publications (2)

Publication Number Publication Date
DE69503046D1 true DE69503046D1 (de) 1998-07-23
DE69503046T2 DE69503046T2 (de) 1999-01-28

Family

ID=10754569

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69503046T Expired - Lifetime DE69503046T2 (de) 1994-05-03 1995-02-15 Mehrfachbefehlssatzabbildung

Country Status (13)

Country Link
US (1) US5568646A (de)
EP (1) EP0758463B1 (de)
JP (2) JP3171201B2 (de)
KR (3) KR100327778B1 (de)
CN (1) CN1088214C (de)
DE (1) DE69503046T2 (de)
GB (1) GB2289354B (de)
IL (1) IL113134A (de)
IN (1) IN189950B (de)
MY (1) MY114381A (de)
RU (1) RU2137184C1 (de)
TW (1) TW242678B (de)
WO (1) WO1995030187A1 (de)

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US5896519A (en) * 1996-06-10 1999-04-20 Lsi Logic Corporation Apparatus for detecting instructions from a variable-length compressed instruction set having extended and non-extended instructions
US5794010A (en) * 1996-06-10 1998-08-11 Lsi Logic Corporation Method and apparatus for allowing execution of both compressed instructions and decompressed instructions in a microprocessor
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US6044460A (en) * 1998-01-16 2000-03-28 Lsi Logic Corporation System and method for PC-relative address generation in a microprocessor with a pipeline architecture
EP0942357A3 (de) 1998-03-11 2000-03-22 Matsushita Electric Industrial Co., Ltd. Mit einer Mehrzahl von Befehlsformaten vereinbarer Datenprozessor
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US6189094B1 (en) * 1998-05-27 2001-02-13 Arm Limited Recirculating register file
US7111290B1 (en) 1999-01-28 2006-09-19 Ati International Srl Profiling program execution to identify frequently-executed portions and to assist binary translation
US6826748B1 (en) 1999-01-28 2004-11-30 Ati International Srl Profiling program execution into registers of a computer
US7941647B2 (en) 1999-01-28 2011-05-10 Ati Technologies Ulc Computer for executing two instruction sets and adds a macroinstruction end marker for performing iterations after loop termination
US7275246B1 (en) 1999-01-28 2007-09-25 Ati International Srl Executing programs for a first computer architecture on a computer of a second architecture
US8127121B2 (en) 1999-01-28 2012-02-28 Ati Technologies Ulc Apparatus for executing programs for a first computer architechture on a computer of a second architechture
US8074055B1 (en) * 1999-01-28 2011-12-06 Ati Technologies Ulc Altering data storage conventions of a processor when execution flows from first architecture code to second architecture code
US8121828B2 (en) 1999-01-28 2012-02-21 Ati Technologies Ulc Detecting conditions for transfer of execution from one computer instruction stream to another and executing transfer on satisfaction of the conditions
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US7065633B1 (en) 1999-01-28 2006-06-20 Ati International Srl System for delivering exception raised in first architecture to operating system coded in second architecture in dual architecture CPU
US6978462B1 (en) 1999-01-28 2005-12-20 Ati International Srl Profiling execution of a sequence of events occuring during a profiled execution interval that matches time-independent selection criteria of events to be profiled
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US6820189B1 (en) * 1999-05-12 2004-11-16 Analog Devices, Inc. Computation core executing multiple operation DSP instructions and micro-controller instructions of shorter length without performing switch operation
US6779107B1 (en) 1999-05-28 2004-08-17 Ati International Srl Computer execution by opportunistic adaptation
US6549959B1 (en) 1999-08-30 2003-04-15 Ati International Srl Detecting modification to computer memory by a DMA device
JP2001142692A (ja) * 1999-10-01 2001-05-25 Hitachi Ltd ２つの異なる固定長命令セットを実行するマイクロプロセッサ、マイクロコンピュータおよび命令実行方法
US6934832B1 (en) 2000-01-18 2005-08-23 Ati International Srl Exception mechanism for a computer
US7353368B2 (en) * 2000-02-15 2008-04-01 Intel Corporation Method and apparatus for achieving architectural correctness in a multi-mode processor providing floating-point support
US20020004897A1 (en) * 2000-07-05 2002-01-10 Min-Cheng Kao Data processing apparatus for executing multiple instruction sets
US6633969B1 (en) 2000-08-11 2003-10-14 Lsi Logic Corporation Instruction translation system and method achieving single-cycle translation of variable-length MIPS16 instructions
GB2367651B (en) * 2000-10-05 2004-12-29 Advanced Risc Mach Ltd Hardware instruction translation within a processor pipeline
GB2367653B (en) * 2000-10-05 2004-10-20 Advanced Risc Mach Ltd Restarting translated instructions
US7149878B1 (en) * 2000-10-30 2006-12-12 Mips Technologies, Inc. Changing instruction set architecture mode by comparison of current instruction execution address with boundary address register values
US7711926B2 (en) * 2001-04-18 2010-05-04 Mips Technologies, Inc. Mapping system and method for instruction set processing
GB2376100B (en) * 2001-05-31 2005-03-09 Advanced Risc Mach Ltd Data processing using multiple instruction sets
US7107439B2 (en) * 2001-08-10 2006-09-12 Mips Technologies, Inc. System and method of controlling software decompression through exceptions
US20070005942A1 (en) * 2002-01-14 2007-01-04 Gil Vinitzky Converting a processor into a compatible virtual multithreaded processor (VMP)
US20060149927A1 (en) * 2002-11-26 2006-07-06 Eran Dagan Processor capable of multi-threaded execution of a plurality of instruction-sets
JP4090908B2 (ja) * 2003-02-21 2008-05-28 シャープ株式会社 画像処理装置および画像形成装置
TWI230899B (en) * 2003-03-10 2005-04-11 Sunplus Technology Co Ltd Processor and method using parity check to proceed command mode switch
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US7707389B2 (en) * 2003-10-31 2010-04-27 Mips Technologies, Inc. Multi-ISA instruction fetch unit for a processor, and applications thereof
GB2414308B (en) * 2004-05-17 2007-08-15 Advanced Risc Mach Ltd Program instruction compression
US20060155974A1 (en) * 2005-01-07 2006-07-13 Moyer William C Data processing system having flexible instruction capability and selection mechanism
US20060174089A1 (en) * 2005-02-01 2006-08-03 International Business Machines Corporation Method and apparatus for embedding wide instruction words in a fixed-length instruction set architecture
US7793078B2 (en) * 2005-04-01 2010-09-07 Arm Limited Multiple instruction set data processing system with conditional branch instructions of a first instruction set and a second instruction set sharing a same instruction encoding
US7958335B2 (en) * 2005-08-05 2011-06-07 Arm Limited Multiple instruction set decoding
GB2435116B (en) * 2006-02-10 2010-04-07 Imagination Tech Ltd Selecting between instruction sets in a microprocessors
US7500210B2 (en) * 2006-11-15 2009-03-03 Mplicity Ltd. Chip area optimization for multithreaded designs
US7802252B2 (en) * 2007-01-09 2010-09-21 International Business Machines Corporation Method and apparatus for selecting the architecture level to which a processor appears to conform
US20090044159A1 (en) * 2007-08-08 2009-02-12 Mplicity Ltd. False path handling
JP2011512566A (ja) * 2007-09-19 2011-04-21 ケーピーアイティ クミンズ インフォシステムズ リミテッド 半自動ソフトウェア移行のためにハードウェアコンポーネントのプラグアンドプレイを可能にするメカニズム
US8347067B2 (en) * 2008-01-23 2013-01-01 Arm Limited Instruction pre-decoding of multiple instruction sets
US20100115239A1 (en) * 2008-10-29 2010-05-06 Adapteva Incorporated Variable instruction width digital signal processor
GB2478726B (en) * 2010-03-15 2013-12-25 Advanced Risc Mach Ltd Mapping between registers used by multiple instruction sets
GB2484489A (en) * 2010-10-12 2012-04-18 Advanced Risc Mach Ltd Instruction decoder using an instruction set identifier to determine the decode rules to use.
US8914615B2 (en) 2011-12-02 2014-12-16 Arm Limited Mapping same logical register specifier for different instruction sets with divergent association to architectural register file using common address format
WO2013132767A1 (ja) 2012-03-09 2013-09-12 パナソニック株式会社 プロセッサ、マルチプロセッサシステム、コンパイラ、ソフトウェアシステム、メモリ制御システムおよびコンピュータシステム
US9442730B2 (en) 2013-07-31 2016-09-13 Apple Inc. Instruction source specification
RU2556364C1 (ru) * 2014-03-18 2015-07-10 Федеральное государственное бюджетное учреждение науки Научно-исследовательский институт системных исследований Российской академии наук (НИИСИ РАН) Гибридный микропроцессор
RU2584470C2 (ru) * 2014-03-18 2016-05-20 Федеральное государственное учреждение "Федеральный научный центр Научно-исследовательский институт системных исследований Российской академии наук" (ФГУ ФНЦ НИИСИ РАН) Гибридный потоковый микропроцессор
GB2540971B (en) 2015-07-31 2018-03-14 Advanced Risc Mach Ltd Graphics processing systems
CN116009814A (zh) 2016-10-20 2023-04-25 英特尔公司 用于经融合的乘加的系统、装置和方法
GB2563580B (en) * 2017-06-15 2019-09-25 Advanced Risc Mach Ltd An apparatus and method for controlling a change in instruction set
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Also Published As

Publication number Publication date
IL113134A0 (en) 1995-06-29
EP0758463A1 (de) 1997-02-19
KR100327777B1 (ko) 2002-03-15
GB2289354B (en) 1997-08-27
CN1088214C (zh) 2002-07-24
MY114381A (en) 2002-10-31
WO1995030187A1 (en) 1995-11-09
US5568646A (en) 1996-10-22
KR970703010A (ko) 1997-06-10
CN1147306A (zh) 1997-04-09
JP3592230B2 (ja) 2004-11-24
EP0758463B1 (de) 1998-06-17
JP3171201B2 (ja) 2001-05-28
JPH09512651A (ja) 1997-12-16
IL113134A (en) 1998-03-10
RU2137184C1 (ru) 1999-09-10
GB2289354A (en) 1995-11-15
KR100323191B1 (ko) 2002-06-24
TW242678B (en) 1995-03-11
IN189950B (de) 2003-05-17
GB9408873D0 (en) 1994-06-22
KR100327778B1 (ko) 2002-03-15
JP2001142697A (ja) 2001-05-25
DE69503046T2 (de) 1999-01-28

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Legal Events

Date Code Title Description
8327 Change in the person/name/address of the patent owner

Owner name: ARM LTD., CHERRY HINTON, CAMBRIDGE, GB

8364 No opposition during term of opposition