DE69435045D1 - Halbleiter-Anordnung und Herstellungsverfahren dafür - Google Patents

Halbleiter-Anordnung und Herstellungsverfahren dafür

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Publication number
DE69435045D1
DE69435045D1 DE69435045T DE69435045T DE69435045D1 DE 69435045 D1 DE69435045 D1 DE 69435045D1 DE 69435045 T DE69435045 T DE 69435045T DE 69435045 T DE69435045 T DE 69435045T DE 69435045 D1 DE69435045 D1 DE 69435045D1
Authority
DE
Germany
Prior art keywords
manufacturing
method therefor
semiconductor arrangement
semiconductor
arrangement
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE69435045T
Other languages
English (en)
Other versions
DE69435045T2 (de
Inventor
Toshimitsu Konuma
Akira Sugawara
Yukiko Uehara
Hongyong Zhang
Atsunori Suzuki
Hideto Ohnuma
Naoaki Yamaguchi
Hideomi Suzawa
Hideki Uochi
Yasuhiko Takemura
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Semiconductor Energy Laboratory Co Ltd
Original Assignee
Semiconductor Energy Laboratory Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from JP28428793A external-priority patent/JP2759414B2/ja
Application filed by Semiconductor Energy Laboratory Co Ltd filed Critical Semiconductor Energy Laboratory Co Ltd
Application granted granted Critical
Publication of DE69435045D1 publication Critical patent/DE69435045D1/de
Publication of DE69435045T2 publication Critical patent/DE69435045T2/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

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    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
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    • H01L29/00Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007Multistep manufacturing processes
    • H01L29/66075Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409Unipolar field-effect transistors
    • H01L29/66477Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/665Unipolar field-effect transistors with an insulated gate, i.e. MISFET using self aligned silicidation, i.e. salicide
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    • H01L21/02107Forming insulating materials on a substrate
    • H01L21/02109Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02112Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H01L21/02123Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
    • H01L21/02142Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material containing silicon and at least one metal element, e.g. metal silicate based insulators or metal silicon oxynitrides
    • H01L21/02145Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material containing silicon and at least one metal element, e.g. metal silicate based insulators or metal silicon oxynitrides the material containing aluminium, e.g. AlSiOx
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    • H01L21/02225Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
    • H01L21/02227Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process
    • H01L21/0223Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by oxidation, e.g. oxidation of the substrate
    • H01L21/02244Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by oxidation, e.g. oxidation of the substrate of a metallic layer
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    • H01L21/02227Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process
    • H01L21/02258Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by anodic treatment, e.g. anodic oxidation
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    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
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    • H01L21/31683Inorganic layers composed of oxides or glassy oxides or oxide based glass formed by oxidation of metallic layers, e.g. Al deposited on the body, e.g. formation of multi-layer insulating structures
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    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321After treatment
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    • H01L27/12Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/124Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
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    • H01L27/12Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259Multistep manufacturing methods
    • H01L27/127Multistep manufacturing methods with a particular formation, treatment or patterning of the active layer specially adapted to the circuit arrangement
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    • H01L29/40Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/45Ohmic electrodes
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    • H01L29/458Ohmic electrodes on silicon for thin film silicon, e.g. source or drain electrode
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    • H01L29/66568Lateral single gate silicon transistors
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    • H01L29/6659Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate with both lightly doped source and drain extensions and source and drain self-aligned to the sides of the gate, e.g. lightly doped drain [LDD] MOSFET, double diffused drain [DDD] MOSFET
    • H01L29/66598Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate with both lightly doped source and drain extensions and source and drain self-aligned to the sides of the gate, e.g. lightly doped drain [LDD] MOSFET, double diffused drain [DDD] MOSFET forming drain [D] and lightly doped drain [LDD] simultaneously, e.g. using implantation through the wings a T-shaped layer, or through a specially shaped layer
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    • H01L29/66409Unipolar field-effect transistors
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    • H01L29/66742Thin film unipolar transistors
    • H01L29/6675Amorphous silicon or polysilicon transistors
    • H01L29/66757Lateral single gate single channel transistors with non-inverted structure, i.e. the channel layer is formed before the gate
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    • H01L29/76Unipolar devices, e.g. field effect transistors
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    • H01L29/78618Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device characterised by the drain or the source properties, e.g. the doping structure, the composition, the sectional shape or the contact structure
    • H01L29/78621Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device characterised by the drain or the source properties, e.g. the doping structure, the composition, the sectional shape or the contact structure with LDD structure or an extension or an offset region or characterised by the doping profile
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    • H01L29/78621Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device characterised by the drain or the source properties, e.g. the doping structure, the composition, the sectional shape or the contact structure with LDD structure or an extension or an offset region or characterised by the doping profile
    • H01L29/78627Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device characterised by the drain or the source properties, e.g. the doping structure, the composition, the sectional shape or the contact structure with LDD structure or an extension or an offset region or characterised by the doping profile with a significant overlap between the lightly doped drain and the gate electrode, e.g. GOLDD
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    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
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    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
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    • H01L21/314Inorganic layers
    • H01L21/316Inorganic layers composed of oxides or glassy oxides or oxide based glass
    • H01L21/3165Inorganic layers composed of oxides or glassy oxides or oxide based glass formed by oxidation
    • H01L21/31683Inorganic layers composed of oxides or glassy oxides or oxide based glass formed by oxidation of metallic layers, e.g. Al deposited on the body, e.g. formation of multi-layer insulating structures
DE69435045T 1993-09-20 1994-09-20 Halbleiter-Anordnung und Herstellungsverfahren dafür Expired - Lifetime DE69435045T2 (de)

Applications Claiming Priority (8)

Application Number Priority Date Filing Date Title
JP25656793 1993-09-20
JP25656593 1993-09-20
JP25656393 1993-09-20
JP25656793 1993-09-20
JP25656393 1993-09-20
JP25656593 1993-09-20
JP28428793A JP2759414B2 (ja) 1993-10-19 1993-10-19 半導体装置の作製方法
JP28428793 1993-10-19

Publications (2)

Publication Number Publication Date
DE69435045D1 true DE69435045D1 (de) 2008-01-03
DE69435045T2 DE69435045T2 (de) 2008-10-02

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DE69435045T Expired - Lifetime DE69435045T2 (de) 1993-09-20 1994-09-20 Halbleiter-Anordnung und Herstellungsverfahren dafür

Country Status (6)

Country Link
US (7) US6867431B2 (de)
EP (3) EP1564800A3 (de)
KR (1) KR100306829B1 (de)
CN (5) CN1652351B (de)
DE (1) DE69435045T2 (de)
TW (1) TW297142B (de)

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Publication number Priority date Publication date Assignee Title
JP3437863B2 (ja) 1993-01-18 2003-08-18 株式会社半導体エネルギー研究所 Mis型半導体装置の作製方法
TW297142B (de) 1993-09-20 1997-02-01 Handotai Energy Kenkyusho Kk
US5719065A (en) 1993-10-01 1998-02-17 Semiconductor Energy Laboratory Co., Ltd. Method for manufacturing semiconductor device with removable spacers
US6777763B1 (en) 1993-10-01 2004-08-17 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device and method for fabricating the same
TW299897U (en) 1993-11-05 1997-03-01 Semiconductor Energy Lab A semiconductor integrated circuit
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CN100502046C (zh) 2009-06-17
US20050153489A1 (en) 2005-07-14
CN1173388C (zh) 2004-10-27
US20090289254A1 (en) 2009-11-26
US7381599B2 (en) 2008-06-03
US20050142705A1 (en) 2005-06-30
CN1652352A (zh) 2005-08-10
TW297142B (de) 1997-02-01
EP1564800A3 (de) 2006-03-15
US8198683B2 (en) 2012-06-12
CN1109220A (zh) 1995-09-27
EP1564799A3 (de) 2005-12-28
US20030100152A1 (en) 2003-05-29
DE69435045T2 (de) 2008-10-02
US7569856B2 (en) 2009-08-04
CN100423290C (zh) 2008-10-01
US20110068339A1 (en) 2011-03-24
EP0645802A3 (de) 1998-03-11
EP0645802A2 (de) 1995-03-29
US6867431B2 (en) 2005-03-15
EP1564799A2 (de) 2005-08-17
CN1223465A (zh) 1999-07-21
US7525158B2 (en) 2009-04-28
US7847355B2 (en) 2010-12-07
EP0645802B1 (de) 2007-11-21
CN1652351A (zh) 2005-08-10
CN1652351B (zh) 2010-05-12
CN1571165A (zh) 2005-01-26
US6049092A (en) 2000-04-11
US20040256621A1 (en) 2004-12-23
KR100306829B1 (ko) 2001-12-15
CN1055790C (zh) 2000-08-23

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