DE69428399D1 - Verfahren zur Herstellung von ohmschen Kontakten für eine komplementäre Halbleiteranordnung - Google Patents

Verfahren zur Herstellung von ohmschen Kontakten für eine komplementäre Halbleiteranordnung

Info

Publication number
DE69428399D1
DE69428399D1 DE69428399T DE69428399T DE69428399D1 DE 69428399 D1 DE69428399 D1 DE 69428399D1 DE 69428399 T DE69428399 T DE 69428399T DE 69428399 T DE69428399 T DE 69428399T DE 69428399 D1 DE69428399 D1 DE 69428399D1
Authority
DE
Germany
Prior art keywords
ohmic contacts
semiconductor arrangement
complementary semiconductor
producing ohmic
producing
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE69428399T
Other languages
English (en)
Other versions
DE69428399T2 (de
Inventor
Jonathan K Abrokwah
Jenn-Hwa Huang
Jaeshin Cho
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NXP USA Inc
Original Assignee
Motorola Energy Systems Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Motorola Energy Systems Inc filed Critical Motorola Energy Systems Inc
Application granted granted Critical
Publication of DE69428399D1 publication Critical patent/DE69428399D1/de
Publication of DE69428399T2 publication Critical patent/DE69428399T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007Multistep manufacturing processes
    • H01L29/66075Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409Unipolar field-effect transistors
    • H01L29/66446Unipolar field-effect transistors with an active layer made of a group 13/15 material, e.g. group 13/15 velocity modulation transistor [VMT], group 13/15 negative resistance FET [NERFET]
    • H01L29/66462Unipolar field-effect transistors with an active layer made of a group 13/15 material, e.g. group 13/15 velocity modulation transistor [VMT], group 13/15 negative resistance FET [NERFET] with a heterojunction interface channel or gate, e.g. HFET, HIGFET, SISFET, HJFET, HEMT
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/283Deposition of conductive or insulating materials for electrodes conducting electric current
    • H01L21/285Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation
    • H01L21/28506Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers
    • H01L21/28575Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising AIIIBV compounds
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232Field-effect technology
    • H01L21/8234MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238Complementary field-effect transistors, e.g. CMOS
    • H01L21/823871Complementary field-effect transistors, e.g. CMOS interconnection or wiring or contact manufacturing related aspects
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/45Ohmic electrodes
    • H01L29/452Ohmic electrodes on AIII-BV compounds
    • YGENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10STECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00Metal treatment
    • Y10S148/02Contacts, special
    • YGENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10STECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00Metal treatment
    • Y10S148/065Gp III-V generic compounds-processing
DE69428399T 1993-06-25 1994-06-23 Verfahren zur Herstellung von ohmschen Kontakten für eine komplementäre Halbleiteranordnung Expired - Fee Related DE69428399T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US08/083,751 US5444016A (en) 1993-06-25 1993-06-25 Method of making ohmic contacts to a complementary III-V semiconductor device

Publications (2)

Publication Number Publication Date
DE69428399D1 true DE69428399D1 (de) 2001-10-31
DE69428399T2 DE69428399T2 (de) 2002-07-04

Family

ID=22180464

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69428399T Expired - Fee Related DE69428399T2 (de) 1993-06-25 1994-06-23 Verfahren zur Herstellung von ohmschen Kontakten für eine komplementäre Halbleiteranordnung

Country Status (3)

Country Link
US (1) US5444016A (de)
EP (1) EP0631324B1 (de)
DE (1) DE69428399T2 (de)

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US5606184A (en) * 1995-05-04 1997-02-25 Motorola, Inc. Heterostructure field effect device having refractory ohmic contact directly on channel layer and method for making
US5940695A (en) * 1996-10-11 1999-08-17 Trw Inc. Gallium antimonide complementary HFET
US5827753A (en) * 1997-03-20 1998-10-27 Motorola, Inc. Monolithic integration of driver circuits with LED array and methods of manufacture
JP3109449B2 (ja) * 1997-04-25 2000-11-13 日本電気株式会社 多層配線構造の形成方法
US6329063B2 (en) * 1998-12-11 2001-12-11 Nova Crystals, Inc. Method for producing high quality heteroepitaxial growth using stress engineering and innovative substrates
US6693033B2 (en) 2000-02-10 2004-02-17 Motorola, Inc. Method of removing an amorphous oxide from a monocrystalline surface
US6528405B1 (en) 2000-02-18 2003-03-04 Motorola, Inc. Enhancement mode RF device and fabrication method
US6410941B1 (en) 2000-06-30 2002-06-25 Motorola, Inc. Reconfigurable systems using hybrid integrated circuits with optical ports
US6427066B1 (en) 2000-06-30 2002-07-30 Motorola, Inc. Apparatus and method for effecting communications among a plurality of remote stations
US6477285B1 (en) 2000-06-30 2002-11-05 Motorola, Inc. Integrated circuits with optical signal propagation
US6501973B1 (en) 2000-06-30 2002-12-31 Motorola, Inc. Apparatus and method for measuring selected physical condition of an animate subject
US6555946B1 (en) 2000-07-24 2003-04-29 Motorola, Inc. Acoustic wave device and process for forming the same
US6638838B1 (en) 2000-10-02 2003-10-28 Motorola, Inc. Semiconductor structure including a partially annealed layer and method of forming the same
US6563118B2 (en) 2000-12-08 2003-05-13 Motorola, Inc. Pyroelectric device on a monocrystalline semiconductor substrate and process for fabricating same
US6673646B2 (en) 2001-02-28 2004-01-06 Motorola, Inc. Growth of compound semiconductor structures on patterned oxide films and process for fabricating same
US6709989B2 (en) 2001-06-21 2004-03-23 Motorola, Inc. Method for fabricating a semiconductor structure including a metal oxide interface with silicon
US6646293B2 (en) 2001-07-18 2003-11-11 Motorola, Inc. Structure for fabricating high electron mobility transistors utilizing the formation of complaint substrates
US6693298B2 (en) 2001-07-20 2004-02-17 Motorola, Inc. Structure and method for fabricating epitaxial semiconductor on insulator (SOI) structures and devices utilizing the formation of a compliant substrate for materials used to form same
US6472694B1 (en) 2001-07-23 2002-10-29 Motorola, Inc. Microprocessor structure having a compound semiconductor layer
US6594414B2 (en) 2001-07-25 2003-07-15 Motorola, Inc. Structure and method of fabrication for an optical switch
US6585424B2 (en) 2001-07-25 2003-07-01 Motorola, Inc. Structure and method for fabricating an electro-rheological lens
US6667196B2 (en) 2001-07-25 2003-12-23 Motorola, Inc. Method for real-time monitoring and controlling perovskite oxide film growth and semiconductor structure formed using the method
US6589856B2 (en) 2001-08-06 2003-07-08 Motorola, Inc. Method and apparatus for controlling anti-phase domains in semiconductor structures and devices
US6462360B1 (en) 2001-08-06 2002-10-08 Motorola, Inc. Integrated gallium arsenide communications systems
US6639249B2 (en) 2001-08-06 2003-10-28 Motorola, Inc. Structure and method for fabrication for a solid-state lighting device
US6673667B2 (en) 2001-08-15 2004-01-06 Motorola, Inc. Method for manufacturing a substantially integral monolithic apparatus including a plurality of semiconductor materials
US7504677B2 (en) * 2005-03-28 2009-03-17 Freescale Semiconductor, Inc. Multi-gate enhancement mode RF switch and bias arrangement
US8283653B2 (en) 2009-12-23 2012-10-09 Intel Corporation Non-planar germanium quantum well devices

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US3684930A (en) * 1970-12-28 1972-08-15 Gen Electric Ohmic contact for group iii-v p-types semiconductors
DE2359640C2 (de) * 1973-11-30 1983-09-15 Licentia Patent-Verwaltungs-Gmbh, 6000 Frankfurt Elektrischer Anschlußkontakt an einen Halbleiterkörper und Verwendung
US4188710A (en) * 1978-08-11 1980-02-19 The United States Of America As Represented By The Secretary Of The Navy Ohmic contacts for group III-V n-type semiconductors using epitaxial germanium films
US4313971A (en) * 1979-05-29 1982-02-02 Rca Corporation Method of fabricating a Schottky barrier contact
JPS5984580A (ja) * 1982-11-08 1984-05-16 Nippon Telegr & Teleph Corp <Ntt> 超短ゲ−ト電界効果トランジスタ
US4540446A (en) * 1983-09-19 1985-09-10 Oki Electric Industry Co., Ltd. Method of forming ohmic contact on GaAs by Ge film and implanting impurity ions therethrough
US4712291A (en) * 1985-06-06 1987-12-15 The United States Of America As Represented By The Secretary Of The Air Force Process of fabricating TiW/Si self-aligned gate for GaAs MESFETs
US4729000A (en) * 1985-06-21 1988-03-01 Honeywell Inc. Low power AlGaAs/GaAs complementary FETs incorporating InGaAs n-channel gates
DE3682119D1 (de) * 1985-06-21 1991-11-28 Honeywell Inc Komplementaere ic-struktur mit hoher steilheit.
JPS62149138A (ja) * 1985-12-23 1987-07-03 Nec Corp 半導体装置の製造方法
JPS62149125A (ja) * 1985-12-23 1987-07-03 Nec Corp 半導体装置の製造方法
US5214298A (en) * 1986-09-30 1993-05-25 Texas Instruments Incorporated Complementary heterostructure field effect transistors
JPS6395620A (ja) * 1986-10-09 1988-04-26 Mitsubishi Electric Corp オ−ミツク電極形成法
US4746627A (en) * 1986-10-30 1988-05-24 Mcdonnell Douglas Corporation Method of making complementary GaAs heterojunction transistors
US4998158A (en) * 1987-06-01 1991-03-05 Motorola, Inc. Hypoeutectic ohmic contact to N-type gallium arsenide with diffusion barrier
US5093280A (en) * 1987-10-13 1992-03-03 Northrop Corporation Refractory metal ohmic contacts and method
US4833042A (en) * 1988-01-27 1989-05-23 Rockwell International Corporation Nonalloyed ohmic contacts for n type gallium arsenide
US4830980A (en) * 1988-04-22 1989-05-16 Hughes Aircraft Company Making complementary integrated p-MODFET and n-MODFET
JP2893723B2 (ja) * 1988-06-13 1999-05-24 住友電気工業株式会社 オーミック電極の製造方法
US5144410A (en) * 1989-03-29 1992-09-01 Vitesse Semiconductor Corporation Ohmic contact for III-V semiconductor devices
US5045502A (en) * 1990-05-10 1991-09-03 Bell Communications Research, Inc. PdIn ohmic contact to GaAs
KR950009893B1 (ko) * 1990-06-28 1995-09-01 미쓰비시 뎅끼 가부시끼가이샤 반도체기억장치
US5060031A (en) * 1990-09-18 1991-10-22 Motorola, Inc Complementary heterojunction field effect transistor with an anisotype N+ ga-channel devices
US5100835A (en) * 1991-03-18 1992-03-31 Eastman Kodak Company Shallow ohmic contacts to N-GaAs
US5116774A (en) * 1991-03-22 1992-05-26 Motorola, Inc. Heterojunction method and structure
US5275971A (en) * 1992-04-20 1994-01-04 Motorola, Inc. Method of forming an ohmic contact to III-V semiconductor materials
US5389564A (en) * 1992-06-22 1995-02-14 Motorola, Inc. Method of forming a GaAs FET having etched ohmic contacts

Also Published As

Publication number Publication date
DE69428399T2 (de) 2002-07-04
EP0631324A1 (de) 1994-12-28
EP0631324B1 (de) 2001-09-26
US5444016A (en) 1995-08-22

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Legal Events

Date Code Title Description
8328 Change in the person/name/address of the agent

Free format text: SCHUMACHER & WILLSAU, PATENTANWALTSSOZIETAET, 80335 MUENCHEN

8364 No opposition during term of opposition
8327 Change in the person/name/address of the patent owner

Owner name: FREESCALE SEMICONDUCTOR, INC., AUSTIN, TEX., US

8339 Ceased/non-payment of the annual fee