DE69427265T2 - Superskalarbefehlsdekoder - Google Patents

Superskalarbefehlsdekoder

Info

Publication number
DE69427265T2
DE69427265T2 DE69427265T DE69427265T DE69427265T2 DE 69427265 T2 DE69427265 T2 DE 69427265T2 DE 69427265 T DE69427265 T DE 69427265T DE 69427265 T DE69427265 T DE 69427265T DE 69427265 T2 DE69427265 T2 DE 69427265T2
Authority
DE
Germany
Prior art keywords
superskalarbefehlsdekoder
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE69427265T
Other languages
English (en)
Other versions
DE69427265D1 (de
Inventor
David B Witt
Michael D Goddard
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Advanced Micro Devices Inc
Original Assignee
Advanced Micro Devices Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Advanced Micro Devices Inc filed Critical Advanced Micro Devices Inc
Publication of DE69427265D1 publication Critical patent/DE69427265D1/de
Application granted granted Critical
Publication of DE69427265T2 publication Critical patent/DE69427265T2/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline, look ahead
    • G06F9/3818—Decoding for concurrent execution
    • G06F9/382—Pipelined decoding, e.g. using predecoding
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30145—Instruction analysis, e.g. decoding, instruction word fields
    • G06F9/30149—Instruction analysis, e.g. decoding, instruction word fields of variable length instructions
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30145—Instruction analysis, e.g. decoding, instruction word fields
    • G06F9/30149—Instruction analysis, e.g. decoding, instruction word fields of variable length instructions
    • G06F9/30152—Determining start or end of instruction; determining instruction length
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/3017—Runtime instruction translation, e.g. macros
    • G06F9/30174—Runtime instruction translation, e.g. macros for non-native instruction set, e.g. Javabyte, legacy code
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline, look ahead
    • G06F9/3802—Instruction prefetching
    • G06F9/3816—Instruction alignment, e.g. cache line crossing
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline, look ahead
    • G06F9/3836—Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline, look ahead
    • G06F9/3836—Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution
    • G06F9/3838—Dependency mechanisms, e.g. register scoreboarding
    • G06F9/384—Register renaming
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline, look ahead
    • G06F9/3854—Instruction completion, e.g. retiring, committing or graduating
    • G06F9/3856—Reordering of instructions, e.g. using queues or age tags
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline, look ahead
    • G06F9/3854—Instruction completion, e.g. retiring, committing or graduating
    • G06F9/3858—Result writeback, i.e. updating the architectural state or memory
DE69427265T 1993-10-29 1994-09-20 Superskalarbefehlsdekoder Expired - Lifetime DE69427265T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US14638393A 1993-10-29 1993-10-29

Publications (2)

Publication Number Publication Date
DE69427265D1 DE69427265D1 (de) 2001-06-28
DE69427265T2 true DE69427265T2 (de) 2002-05-02

Family

ID=22517123

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69427265T Expired - Lifetime DE69427265T2 (de) 1993-10-29 1994-09-20 Superskalarbefehlsdekoder

Country Status (4)

Country Link
US (2) US6189087B1 (de)
EP (1) EP0651320B1 (de)
JP (1) JPH07182163A (de)
DE (1) DE69427265T2 (de)

Families Citing this family (77)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5630082A (en) * 1993-10-29 1997-05-13 Advanced Micro Devices, Inc. Apparatus and method for instruction queue scanning
GB2290395B (en) 1994-06-10 1997-05-28 Advanced Risc Mach Ltd Interoperability with multiple instruction sets
US5781789A (en) * 1995-08-31 1998-07-14 Advanced Micro Devices, Inc. Superscaler microprocessor employing a parallel mask decoder
EP0853782B1 (de) * 1995-10-06 2001-06-27 Advanced Micro Devices, Inc. Befehlsdekoder mit emulation durch indirektspezifizierer
US5794063A (en) * 1996-01-26 1998-08-11 Advanced Micro Devices, Inc. Instruction decoder including emulation using indirect specifiers
US5835747A (en) * 1996-01-26 1998-11-10 Advanced Micro Devices, Inc. Hierarchical scan logic for out-of-order load/store execution control
US6093213A (en) * 1995-10-06 2000-07-25 Advanced Micro Devices, Inc. Flexible implementation of a system management mode (SMM) in a processor
US5926642A (en) 1995-10-06 1999-07-20 Advanced Micro Devices, Inc. RISC86 instruction set
US5920713A (en) * 1995-10-06 1999-07-06 Advanced Micro Devices, Inc. Instruction decoder including two-way emulation code branching
US5796974A (en) * 1995-11-07 1998-08-18 Advanced Micro Devices, Inc. Microcode patching apparatus and method
US5787266A (en) * 1996-02-20 1998-07-28 Advanced Micro Devices, Inc. Apparatus and method for accessing special registers without serialization
DE69718278T2 (de) * 1996-10-31 2003-08-21 Texas Instruments Inc Methode und System zur Einzel-Zyklus-Ausführung aufeinanderfolgender Iterationen einer Befehlsschleife
US6088793A (en) * 1996-12-30 2000-07-11 Intel Corporation Method and apparatus for branch execution on a multiple-instruction-set-architecture microprocessor
US5845102A (en) * 1997-03-03 1998-12-01 Advanced Micro Devices, Inc. Determining microcode entry points and prefix bytes using a parallel logic technique
US6016544A (en) * 1997-06-09 2000-01-18 Ip First Llc Apparatus and method for tracking changes in address size and for different size retranslate second instruction with an indicator from address size
US5933629A (en) * 1997-06-12 1999-08-03 Advanced Micro Devices, Inc. Apparatus and method for detecting microbranches early
US5930491A (en) * 1997-06-18 1999-07-27 International Business Machines Corporation Identification of related instructions resulting from external to internal translation by use of common ID field for each group
US6098165A (en) * 1997-06-25 2000-08-01 Sun Microsystems, Inc. Fetching and handling a bundle of instructions comprising instructions and non-complex instructions
US5875316A (en) * 1997-06-25 1999-02-23 Sun Microsystems, Inc. Method for handling complex instructions in an out-of-order processor
US6192398B1 (en) * 1997-10-17 2001-02-20 International Business Machines Corporation Remote/shared browser cache
US6253311B1 (en) * 1997-11-29 2001-06-26 Jp First Llc Instruction set for bi-directional conversion and transfer of integer and floating point data
US6546479B1 (en) * 1998-02-10 2003-04-08 Koninklijke Philips Electronics N.V. Reduced instruction fetch latency in a system including a pipelined processor
US6249855B1 (en) * 1998-06-02 2001-06-19 Compaq Computer Corporation Arbiter system for central processing unit having dual dominoed encoders for four instruction issue per machine cycle
US6418527B1 (en) * 1998-10-13 2002-07-09 Motorola, Inc. Data processor instruction system for grouping instructions with or without a common prefix and data processing system that uses two or more instruction grouping methods
US6438664B1 (en) 1999-10-27 2002-08-20 Advanced Micro Devices, Inc. Microcode patch device and method for patching microcode using match registers and patch routines
US6442707B1 (en) 1999-10-29 2002-08-27 Advanced Micro Devices, Inc. Alternate fault handler
US6539470B1 (en) 1999-11-16 2003-03-25 Advanced Micro Devices, Inc. Instruction decode unit producing instruction operand information in the order in which the operands are identified, and systems including same
US6502185B1 (en) * 2000-01-03 2002-12-31 Advanced Micro Devices, Inc. Pipeline elements which verify predecode information
US7003407B1 (en) * 2000-10-23 2006-02-21 Stmicroelectronics S.A. Circuit for detecting and formatting data frames
US7149878B1 (en) 2000-10-30 2006-12-12 Mips Technologies, Inc. Changing instruction set architecture mode by comparison of current instruction execution address with boundary address register values
US7181484B2 (en) 2001-02-21 2007-02-20 Mips Technologies, Inc. Extended-precision accumulation of multiplier output
US7711763B2 (en) 2001-02-21 2010-05-04 Mips Technologies, Inc. Microprocessor instructions for performing polynomial arithmetic operations
US7599981B2 (en) 2001-02-21 2009-10-06 Mips Technologies, Inc. Binary polynomial multiplier
US7162621B2 (en) * 2001-02-21 2007-01-09 Mips Technologies, Inc. Virtual instruction expansion based on template and parameter selector information specifying sign-extension or concentration
US6738792B1 (en) 2001-03-09 2004-05-18 Advanced Micro Devices, Inc. Parallel mask generator
US7711926B2 (en) * 2001-04-18 2010-05-04 Mips Technologies, Inc. Mapping system and method for instruction set processing
US7074489B2 (en) * 2001-05-23 2006-07-11 Air Products And Chemicals, Inc. Low dielectric constant material and method of processing by CVD
US7107439B2 (en) * 2001-08-10 2006-09-12 Mips Technologies, Inc. System and method of controlling software decompression through exceptions
US7529912B2 (en) * 2002-02-12 2009-05-05 Via Technologies, Inc. Apparatus and method for instruction-level specification of floating point format
US7181596B2 (en) * 2002-02-12 2007-02-20 Ip-First, Llc Apparatus and method for extending a microprocessor instruction set
US7328328B2 (en) * 2002-02-19 2008-02-05 Ip-First, Llc Non-temporal memory reference control mechanism
US7315921B2 (en) 2002-02-19 2008-01-01 Ip-First, Llc Apparatus and method for selective memory attribute control
US7395412B2 (en) * 2002-03-08 2008-07-01 Ip-First, Llc Apparatus and method for extending data modes in a microprocessor
US7546446B2 (en) * 2002-03-08 2009-06-09 Ip-First, Llc Selective interrupt suppression
US7155598B2 (en) * 2002-04-02 2006-12-26 Ip-First, Llc Apparatus and method for conditional instruction execution
US7185180B2 (en) * 2002-04-02 2007-02-27 Ip-First, Llc Apparatus and method for selective control of condition code write back
US7373483B2 (en) * 2002-04-02 2008-05-13 Ip-First, Llc Mechanism for extending the number of registers in a microprocessor
US7380103B2 (en) * 2002-04-02 2008-05-27 Ip-First, Llc Apparatus and method for selective control of results write back
US7302551B2 (en) * 2002-04-02 2007-11-27 Ip-First, Llc Suppression of store checking
US7380109B2 (en) * 2002-04-15 2008-05-27 Ip-First, Llc Apparatus and method for providing extended address modes in an existing instruction set for a microprocessor
US6957322B1 (en) 2002-07-25 2005-10-18 Advanced Micro Devices, Inc. Efficient microcode entry access from sequentially addressed portion via non-sequentially addressed portion
US7822955B2 (en) * 2003-01-21 2010-10-26 Arm Limited Data processing apparatus and method for utilizing endianess independent data values
US6957319B1 (en) 2003-02-19 2005-10-18 Advanced Micro Devices, Inc. Integrated circuit with multiple microcode ROMs
US20040193844A1 (en) * 2003-03-24 2004-09-30 Sun Microsystems, Inc. Load and/or store queue emptying technique to facilitate atomicity in processor execution of helper set
US20040193845A1 (en) * 2003-03-24 2004-09-30 Sun Microsystems, Inc. Stall technique to facilitate atomicity in processor execution of helper set
US7219218B2 (en) * 2003-03-31 2007-05-15 Sun Microsystems, Inc. Vector technique for addressing helper instruction groups associated with complex instructions
JP3752493B2 (ja) * 2003-03-31 2006-03-08 東芝マイクロエレクトロニクス株式会社 レジスタ・リネーミング機能を有するプロセッサ
US7707389B2 (en) * 2003-10-31 2010-04-27 Mips Technologies, Inc. Multi-ISA instruction fetch unit for a processor, and applications thereof
EP1622009A1 (de) * 2004-07-27 2006-02-01 Texas Instruments Incorporated JSM-Architektur und Systeme
US7707387B2 (en) 2005-06-01 2010-04-27 Microsoft Corporation Conditional execution via content addressable memory and parallel computing execution model
US7451297B2 (en) 2005-06-01 2008-11-11 Microsoft Corporation Computing system and method that determines current configuration dependent on operand input from another configuration
US7793040B2 (en) 2005-06-01 2010-09-07 Microsoft Corporation Content addressable memory architecture
US7350056B2 (en) * 2005-09-27 2008-03-25 International Business Machines Corporation Method and apparatus for issuing instructions from an issue queue in an information handling system
US7802073B1 (en) 2006-03-29 2010-09-21 Oracle America, Inc. Virtual core management
US7624253B2 (en) * 2006-10-25 2009-11-24 Arm Limited Determining register availability for register renaming
US8281308B1 (en) 2007-07-23 2012-10-02 Oracle America, Inc. Virtual core remapping based on temperature
CN100530164C (zh) * 2007-12-29 2009-08-19 中国科学院计算技术研究所 一种risc处理器及其寄存器标志位处理方法
CN101216755B (zh) * 2008-01-02 2011-10-12 中国科学院计算技术研究所 Risc处理器及其浮点寄存器的非对齐访存方法
CN101216778B (zh) * 2008-01-21 2011-04-13 中国科学院计算技术研究所 一种risc处理器装置及其指令地址转换查找方法
CN100555225C (zh) * 2008-03-17 2009-10-28 中国科学院计算技术研究所 一种支持x86虚拟机的risc处理器装置及方法
JP5357475B2 (ja) * 2008-09-09 2013-12-04 ルネサスエレクトロニクス株式会社 データプロセッサ
US8639886B2 (en) * 2009-02-03 2014-01-28 International Business Machines Corporation Store-to-load forwarding mechanism for processor runahead mode operation
US8589661B2 (en) * 2010-12-07 2013-11-19 Advanced Micro Devices, Inc. Odd and even start bit vectors
US9280352B2 (en) * 2011-11-30 2016-03-08 Apple Inc. Lookahead scanning and cracking of microcode instructions in a dispatch queue
US9710278B2 (en) * 2014-09-30 2017-07-18 International Business Machines Corporation Optimizing grouping of instructions
US10095637B2 (en) * 2016-09-15 2018-10-09 Advanced Micro Devices, Inc. Speculative retirement of post-lock instructions
US20230229447A1 (en) * 2021-12-30 2023-07-20 Advanced Micro Devices, Inc. Stateful microcode branching

Family Cites Families (48)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3781808A (en) 1972-10-17 1973-12-25 Ibm Virtual memory system
AT354159B (de) 1975-02-10 1979-12-27 Siemens Ag Assoziativspeicher mit getrennt assoziierbaren bereichen
US4161784A (en) 1978-01-05 1979-07-17 Honeywell Information Systems, Inc. Microprogrammable floating point arithmetic unit capable of performing arithmetic operations on long and short operands
US4502111A (en) 1981-05-29 1985-02-26 Harris Corporation Token generator
US4928223A (en) 1982-10-06 1990-05-22 Fairchild Semiconductor Corporation Floating point microprocessor with directable two level microinstructions
US4807115A (en) 1983-10-07 1989-02-21 Cornell Research Foundation, Inc. Instruction issuing mechanism for processors with multiple functional units
JPH0658631B2 (ja) 1983-12-19 1994-08-03 株式会社日立製作所 デ−タ処理装置
DE3751503T2 (de) 1986-03-26 1996-05-09 Hitachi Ltd Datenprozessor in Pipelinestruktur mit der Fähigkeit mehrere Befehle parallel zu dekodieren und auszuführen.
EP0259095A3 (de) 1986-08-27 1990-02-28 Amdahl Corporation Warteschlange für einen Cachespeicher
US4992934A (en) 1986-12-15 1991-02-12 United Technologies Corporation Reduced instruction set computing apparatus and methods
US4926322A (en) 1987-08-03 1990-05-15 Compag Computer Corporation Software emulation of bank-switched memory using a virtual DOS monitor and paged memory management
US5222230A (en) 1988-01-29 1993-06-22 Texas Instruments Incorporated Circuitry for transferring data from a data bus and temporary register into a plurality of input registers on clock edges
US5155817A (en) 1988-04-01 1992-10-13 Kabushiki Kaisha Toshiba Microprocessor
US5131086A (en) 1988-08-25 1992-07-14 Edgcore Technology, Inc. Method and system for executing pipelined three operand construct
US5101341A (en) 1988-08-25 1992-03-31 Edgcore Technology, Inc. Pipelined system for reducing instruction access time by accumulating predecoded instruction bits a FIFO
US5056006A (en) 1988-09-12 1991-10-08 General Electric Company Parallel processor with single program storage and sequencer and simultaneous instruction processing
JP2810068B2 (ja) 1988-11-11 1998-10-15 株式会社日立製作所 プロセッサシステム、コンピュータシステム及び命令処理方法
US5067069A (en) 1989-02-03 1991-11-19 Digital Equipment Corporation Control of multiple functional units with parallel operation in a microcoded execution unit
US5113515A (en) 1989-02-03 1992-05-12 Digital Equipment Corporation Virtual instruction cache system using length responsive decoded instruction shifting and merging with prefetch buffer outputs to fill instruction buffer
US5155816A (en) 1989-02-10 1992-10-13 Intel Corporation Pipelined apparatus and method for controlled loading of floating point data in a microprocessor
US5155820A (en) 1989-02-21 1992-10-13 Gibson Glenn A Instruction format with designations for operand lengths of byte, half word, word, or double word encoded in address bits
US5226126A (en) 1989-02-24 1993-07-06 Nexgen Microsystems Processor having plurality of functional units for orderly retiring outstanding operations based upon its associated tags
CA2016068C (en) 1989-05-24 2000-04-04 Robert W. Horst Multiple instruction issue computer architecture
US5136697A (en) 1989-06-06 1992-08-04 Advanced Micro Devices, Inc. System for reducing delay for execution subsequent to correctly predicted branch instruction using fetch information stored with each block of instructions in cache
US5129067A (en) 1989-06-06 1992-07-07 Advanced Micro Devices, Inc. Multiple instruction decoder for minimizing register port requirements
DE69030905T2 (de) 1989-08-28 1998-01-29 Nec Corp Mikroprozessor mit Pipeline-Predecodereinheit und -Hauptdecodereinheit
US5251306A (en) 1990-01-16 1993-10-05 Advanced Micro Devices, Inc. Apparatus for controlling execution of a program in a computing device
US5185868A (en) 1990-01-16 1993-02-09 Advanced Micro Devices, Inc. Apparatus having hierarchically arranged decoders concurrently decoding instructions and shifting instructions not ready for execution to vacant decoders higher in the hierarchy
US5226130A (en) 1990-02-26 1993-07-06 Nexgen Microsystems Method and apparatus for store-into-instruction-stream detection and maintaining branch prediction cache consistency
US5128888A (en) 1990-04-02 1992-07-07 Advanced Micro Devices, Inc. Arithmetic unit having multiple accumulators
CA2037708C (en) 1990-05-04 1998-01-20 Richard J. Eickemeyer General purpose compound apparatus for instruction-level parallel processors
DE69123629T2 (de) * 1990-05-04 1997-06-12 Ibm Maschinenarchitektur für skalaren Verbundbefehlssatz
EP0459232B1 (de) * 1990-05-29 1998-12-09 National Semiconductor Corporation Cache-Speicher von partiell decodierten Befehlen und Verfahren hierfür
WO1992006426A1 (en) 1990-10-09 1992-04-16 Nexgen Microsystems Method and apparatus for parallel decoding of instructions with branch prediction look-up
JPH04156613A (ja) * 1990-10-20 1992-05-29 Fujitsu Ltd 命令バッファ装置
EP0498654B1 (de) 1991-02-08 2000-05-10 Fujitsu Limited Cachespeicher zur Verarbeitung von Befehlsdaten und Datenprozessor mit demselben
JPH052484A (ja) 1991-06-24 1993-01-08 Mitsubishi Electric Corp スーパースカラプロセツサ
ATE200357T1 (de) 1991-07-08 2001-04-15 Seiko Epson Corp Risc-prozessor mit dehnbarer architektur
US5345569A (en) 1991-09-20 1994-09-06 Advanced Micro Devices, Inc. Apparatus and method for resolving dependencies among a plurality of instructions within a storage device
GB2263987B (en) 1992-02-06 1996-03-06 Intel Corp End bit markers for instruction decode
GB2263985B (en) * 1992-02-06 1995-06-14 Intel Corp Two stage window multiplexors for deriving variable length instructions from a stream of instructions
GB2263895B (en) 1992-02-07 1995-06-28 Aeb Jacked Structures Ltd Improvements in and relating to moving a structure relative to the ground
US5438668A (en) 1992-03-31 1995-08-01 Seiko Epson Corporation System and method for extraction, alignment and decoding of CISC instructions into a nano-instruction bucket for execution by a RISC computer
US5337415A (en) 1992-12-04 1994-08-09 Hewlett-Packard Company Predecoding instructions for supercalar dependency indicating simultaneous execution for increased operating frequency
US5465373A (en) 1993-01-08 1995-11-07 International Business Machines Corporation Method and system for single cycle dispatch of multiple instructions in a superscalar processor system
IE80854B1 (en) 1993-08-26 1999-04-07 Intel Corp Processor ordering consistency for a processor performing out-of-order instruction execution
DE69429061T2 (de) 1993-10-29 2002-07-18 Advanced Micro Devices Inc Superskalarmikroprozessoren
US5632023A (en) 1994-06-01 1997-05-20 Advanced Micro Devices, Inc. Superscalar microprocessor including flag operand renaming and forwarding apparatus

Also Published As

Publication number Publication date
US5796973A (en) 1998-08-18
DE69427265D1 (de) 2001-06-28
US6189087B1 (en) 2001-02-13
EP0651320A1 (de) 1995-05-03
EP0651320B1 (de) 2001-05-23
JPH07182163A (ja) 1995-07-21

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