DE69426507D1 - System und Verfahren zur gleichzeitigen Prozess- und Device-Simulation - Google Patents

System und Verfahren zur gleichzeitigen Prozess- und Device-Simulation

Info

Publication number
DE69426507D1
DE69426507D1 DE69426507T DE69426507T DE69426507D1 DE 69426507 D1 DE69426507 D1 DE 69426507D1 DE 69426507 T DE69426507 T DE 69426507T DE 69426507 T DE69426507 T DE 69426507T DE 69426507 D1 DE69426507 D1 DE 69426507D1
Authority
DE
Germany
Prior art keywords
procedure
device simulation
simultaneous process
simultaneous
simulation
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE69426507T
Other languages
English (en)
Other versions
DE69426507T2 (de
Inventor
Yukio Tamegaya
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Electronics Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Publication of DE69426507D1 publication Critical patent/DE69426507D1/de
Application granted granted Critical
Publication of DE69426507T2 publication Critical patent/DE69426507T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/44—Arrangements for executing specific programs
    • G06F9/455—Emulation; Interpretation; Software simulation, e.g. virtualisation or emulation of application or operating system execution engines
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/20—Design optimisation, verification or simulation
    • G06F30/23—Design optimisation, verification or simulation using finite element methods [FEM] or finite difference methods [FDM]
DE69426507T 1993-06-24 1994-06-24 System und Verfahren zur gleichzeitigen Prozess- und Device-Simulation Expired - Fee Related DE69426507T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP5152553A JP3001351B2 (ja) 1993-06-24 1993-06-24 シミュレーション方法

Publications (2)

Publication Number Publication Date
DE69426507D1 true DE69426507D1 (de) 2001-02-08
DE69426507T2 DE69426507T2 (de) 2001-06-13

Family

ID=15542987

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69426507T Expired - Fee Related DE69426507T2 (de) 1993-06-24 1994-06-24 System und Verfahren zur gleichzeitigen Prozess- und Device-Simulation

Country Status (5)

Country Link
US (1) US5629877A (de)
EP (1) EP0631248B1 (de)
JP (1) JP3001351B2 (de)
KR (1) KR0136020B1 (de)
DE (1) DE69426507T2 (de)

Families Citing this family (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6304836B1 (en) 1996-10-28 2001-10-16 Advanced Micro Devices Worst case design parameter extraction for logic technologies
US5966527A (en) * 1996-10-28 1999-10-12 Advanced Micro Devices, Inc. Apparatus, article of manufacture, method and system for simulating a mass-produced semiconductor device behavior
US6055460A (en) * 1997-08-06 2000-04-25 Advanced Micro Devices, Inc. Semiconductor process compensation utilizing non-uniform ion implantation methodology
US6370675B1 (en) * 1998-08-18 2002-04-09 Advantest Corp. Semiconductor integrated circuit design and evaluation system using cycle base timing
US6978229B1 (en) 1999-11-18 2005-12-20 Pdf Solutions, Inc. Efficient method for modeling and simulation of the impact of local and global variation on integrated circuits
US6449749B1 (en) 1999-11-18 2002-09-10 Pdf Solutions, Inc. System and method for product yield prediction
AU1616101A (en) 1999-11-18 2001-05-30 Pdf Solutions, Inc. The passive multiplexor test structure for intergrated circuit manufacturing
US8073667B2 (en) * 2003-09-30 2011-12-06 Tokyo Electron Limited System and method for using first-principles simulation to control a semiconductor manufacturing process
US8050900B2 (en) * 2003-09-30 2011-11-01 Tokyo Electron Limited System and method for using first-principles simulation to provide virtual sensors that facilitate a semiconductor manufacturing process
US8032348B2 (en) * 2003-09-30 2011-10-04 Tokyo Electron Limited System and method for using first-principles simulation to facilitate a semiconductor manufacturing process
US8036869B2 (en) * 2003-09-30 2011-10-11 Tokyo Electron Limited System and method for using first-principles simulation to control a semiconductor manufacturing process via a simulation result or a derived empirical model
JP2017037441A (ja) * 2015-08-07 2017-02-16 株式会社東芝 プロセスシミュレータ、レイアウトエディタ及びシミュレーションシステム

Family Cites Families (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB8416039D0 (en) * 1984-06-22 1984-07-25 Micro Consultants Ltd Graphic simulation system
US5050091A (en) * 1985-02-28 1991-09-17 Electric Editor, Inc. Integrated electric design system with automatic constraint satisfaction
FR2578668B1 (fr) * 1985-03-08 1989-06-02 Hennion Bernard Systeme de simulation d'un circuit electronique
US4858146A (en) * 1986-08-13 1989-08-15 The Babcock & Wilcox Company Automated design of structures using a finite element database
JP2695160B2 (ja) * 1987-04-30 1997-12-24 株式会社日立製作所 任意形状抵抗体の端子間抵抗計算方法
JP2635617B2 (ja) * 1987-09-29 1997-07-30 株式会社東芝 半導体素子特性評価用の直交格子点の発生方法
US4815024A (en) * 1987-11-12 1989-03-21 University Of Toronto, Innovations Foundation Simulation apparatus
JPH0244712A (ja) * 1988-08-05 1990-02-14 Toshiba Mach Co Ltd 線対称パターンを含むパターンの描画方法
US5070469A (en) * 1988-11-29 1991-12-03 Mitsubishi Denki Kabushiki Kaisha Topography simulation method
US5103415A (en) * 1989-01-13 1992-04-07 Kabushiki Kaisha Toshiba Computer-simulation technique for numerical analysis of semiconductor devices
US5237513A (en) * 1989-11-20 1993-08-17 Massachusetts Institute Of Technology Optimal integrated circuit generation
JP2800437B2 (ja) * 1991-02-06 1998-09-21 日本電気株式会社 デバイスシミュレーション方法
JP2763985B2 (ja) * 1992-04-27 1998-06-11 三菱電機株式会社 論理シミュレーション装置
US5313398A (en) * 1992-07-23 1994-05-17 Carnegie Mellon University Method and apparatus for simulating a microelectronic circuit

Also Published As

Publication number Publication date
EP0631248A3 (de) 1996-01-17
US5629877A (en) 1997-05-13
KR950001537A (ko) 1995-01-03
JP3001351B2 (ja) 2000-01-24
KR0136020B1 (ko) 1998-06-15
JPH0722604A (ja) 1995-01-24
EP0631248B1 (de) 2001-01-03
EP0631248A2 (de) 1994-12-28
DE69426507T2 (de) 2001-06-13

Similar Documents

Publication Publication Date Title
DE69430688D1 (de) Verfahren und Gerät zur Systemsteuerung
DE69430426T2 (de) Vorrichtung und verfahren zur feuerbekämpfung
DE69429867D1 (de) Verfahren und einrichtung zur authentifizierung
DE69422739T2 (de) Verfahren und Vorrichtung zur Belichtung
DE69332739T2 (de) Verfahren und vorrichtung zur präparativen elektroforese
DE69603577D1 (de) Verfahren und vorrichtung zur verabreichung von analgetika
DE69426003T2 (de) Verfahren und Vorrichtung zur Kathodenzerstäubung
DE69226511D1 (de) Verfahren und Vorrichtung zur Belichtung von Substraten
DE69428089D1 (de) Gerät und Verfahren zur Bildanalyse
DE69626977D1 (de) Gerät und verfahren zur kalibration von vielfachbehältern
DE69434398D1 (de) Verfahren und Einrichtung zur Signalformung
DE68925399T2 (de) Verfahren und Gerät zur Bildtransformation
DE59207521D1 (de) Verfahren und vorrichtung zur schaumerzeugung
DE69323863D1 (de) Verfahren und Vorrichtung zur Adressübersetzung
DE69414784D1 (de) Vorrichtung und Verfahren zur Formmodellierung
DE69422845D1 (de) Vorrichtung und Verfahren zur Koordinateneingabe
DE69628494D1 (de) Vorrichtung und Verfahren zur Koordinateneingabe
DE59408389D1 (de) Verfahren und vorrichtung zur schlupfregelung
DE69313735D1 (de) Verfahren und Vorrichtung zur Anzeigesteuerung
DE69426507D1 (de) System und Verfahren zur gleichzeitigen Prozess- und Device-Simulation
DE69333806D1 (de) Verfahren und Gerät zur Prüfsequenzgenerierung
DE69419970D1 (de) Verfahren und Vorrichtung zur Elektroplattierung
DE59700343D1 (de) Verfahren und Vorrichtung zur Weitergabe von Gegenständen
DE69229433T2 (de) Einrichtung und Verfahren zur kinematischen Simulierung
DE69425166T2 (de) Verfahren und Gerät zur Mustererkennung

Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8327 Change in the person/name/address of the patent owner

Owner name: NEC ELECTRONICS CORP., KAWASAKI, KANAGAWA, JP

8339 Ceased/non-payment of the annual fee