DE69426406T2 - Schaltung zur Verteilung des Hochfrequenz-Taktsignals mit reduzierter Taktverschiebung - Google Patents

Schaltung zur Verteilung des Hochfrequenz-Taktsignals mit reduzierter Taktverschiebung

Info

Publication number
DE69426406T2
DE69426406T2 DE69426406T DE69426406T DE69426406T2 DE 69426406 T2 DE69426406 T2 DE 69426406T2 DE 69426406 T DE69426406 T DE 69426406T DE 69426406 T DE69426406 T DE 69426406T DE 69426406 T2 DE69426406 T2 DE 69426406T2
Authority
DE
Germany
Prior art keywords
distribution
circuit
clock signal
reduced
shift
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE69426406T
Other languages
English (en)
Other versions
DE69426406D1 (de
Inventor
Masahiro Nomura
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Publication of DE69426406D1 publication Critical patent/DE69426406D1/de
Application granted granted Critical
Publication of DE69426406T2 publication Critical patent/DE69426406T2/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/04—Generating or distributing clock signals or signals derived directly therefrom
    • G06F1/10—Distribution of clock signals, e.g. skew
DE69426406T 1993-09-24 1994-09-23 Schaltung zur Verteilung des Hochfrequenz-Taktsignals mit reduzierter Taktverschiebung Expired - Lifetime DE69426406T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP05237079A JP3112784B2 (ja) 1993-09-24 1993-09-24 クロック信号分配回路

Publications (2)

Publication Number Publication Date
DE69426406D1 DE69426406D1 (de) 2001-01-18
DE69426406T2 true DE69426406T2 (de) 2001-06-28

Family

ID=17010108

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69426406T Expired - Lifetime DE69426406T2 (de) 1993-09-24 1994-09-23 Schaltung zur Verteilung des Hochfrequenz-Taktsignals mit reduzierter Taktverschiebung

Country Status (4)

Country Link
US (1) US5668484A (de)
EP (1) EP0646854B1 (de)
JP (1) JP3112784B2 (de)
DE (1) DE69426406T2 (de)

Families Citing this family (32)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2735034B2 (ja) * 1995-06-14 1998-04-02 日本電気株式会社 クロック信号分配回路
US5519350A (en) * 1995-06-30 1996-05-21 At&T Corp. Circuitry for delivering a signal to different load elements located in an electronic system
JPH0944267A (ja) * 1995-07-26 1997-02-14 Mitsubishi Electric Corp クロック分配回路
US5790841A (en) 1996-04-15 1998-08-04 Advanced Micro Devices, Inc. Method for placement of clock buffers in a clock distribution system
US6144224A (en) * 1997-06-16 2000-11-07 International Business Machines Corporation Clock distribution network with dual wire routing
JPH11175183A (ja) * 1997-12-12 1999-07-02 Fujitsu Ltd 半導体集積回路におけるクロック分配回路
JP3441948B2 (ja) * 1997-12-12 2003-09-02 富士通株式会社 半導体集積回路におけるクロック分配回路
US6133750A (en) * 1998-04-27 2000-10-17 Lattice Semiconductor Corp. Combination of global clock and localized clocks
US6311313B1 (en) * 1998-12-29 2001-10-30 International Business Machines Corporation X-Y grid tree clock distribution network with tunable tree and grid networks
JP2001117967A (ja) 1999-10-22 2001-04-27 Nec Corp クロック分配設計方法、及び、木構造のバッファ回路
US6532544B1 (en) * 1999-11-08 2003-03-11 International Business Machines Corporation High gain local clock buffer for a mesh clock distribution utilizing a gain enhanced split driver clock buffer
JP3699875B2 (ja) * 2000-01-04 2005-09-28 株式会社東芝 半導体集積回路装置
US6356132B1 (en) 2000-01-31 2002-03-12 Agere Systems Guardian Corp. Programmable delay cell
US6433605B1 (en) * 2000-02-03 2002-08-13 Hewlett-Packard Company Low wiring skew clock network with current mode buffer
US7085237B1 (en) 2000-03-31 2006-08-01 Alcatel Method and apparatus for routing alarms in a signaling server
US6643791B1 (en) * 2000-03-31 2003-11-04 Alcatel Clock distribution scheme in a signaling server
WO2001095075A1 (fr) * 2000-06-02 2001-12-13 Hitachi,Ltd Circuit integre a semi-conducteur et circuit de distribution du signal d'horloge
US6909127B2 (en) * 2001-06-27 2005-06-21 Intel Corporation Low loss interconnect structure for use in microelectronic circuits
US6522186B2 (en) * 2001-06-27 2003-02-18 Intel Corporation Hierarchical clock grid for on-die salphasic clocking
JP2003060060A (ja) * 2001-08-21 2003-02-28 Fujitsu Ltd 半導体集積回路装置
JP3672889B2 (ja) * 2001-08-29 2005-07-20 Ｎｅｃエレクトロニクス株式会社 半導体集積回路とそのレイアウト方法
US7209492B2 (en) * 2002-04-15 2007-04-24 Alcatel DSO timing source transient compensation
TW560128B (en) * 2002-08-09 2003-11-01 Via Tech Inc Method and related circuitry for buffering output signals of a chip with even number driving circuits
JP4878727B2 (ja) * 2003-10-15 2012-02-15 ルネサスエレクトロニクス株式会社 半導体集積回路
EP1751865A4 (de) * 2004-05-24 2009-10-21 Univ California Übertragungsleitungsnetz mit hochgeschwindigkeitstaktverteilung
TWI287187B (en) * 2005-08-17 2007-09-21 Ind Tech Res Inst Opposite-phase scheme for peak current reduction
WO2009019659A2 (en) * 2007-08-08 2009-02-12 Koninklijke Philips Electronics N.V. Silicon photomultiplier readout circuitry
CN101861527B (zh) 2007-08-08 2013-08-14 皇家飞利浦电子股份有限公司 硅光电倍增器触发网络
US8448114B1 (en) 2012-01-23 2013-05-21 Freescale Semiconductor, Inc. Method for dual edge clock and buffer tree synthesis
US9256245B2 (en) * 2014-04-02 2016-02-09 Mediatek Inc. Clock tree circuit and memory controller
GB2532284A (en) * 2014-11-17 2016-05-18 Ibm Method to reduce dynamic clock skew and/or slew in an electronic circuit
US10234891B2 (en) 2016-03-16 2019-03-19 Ricoh Company, Ltd. Semiconductor integrated circuit, and method for supplying clock signals in semiconductor integrated circuit

Family Cites Families (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6182525A (ja) * 1984-09-29 1986-04-26 Toshiba Corp 半導体集積回路装置
JPS6313517A (ja) * 1986-07-04 1988-01-20 Nec Corp ゲ−トアレ−回路
US4769558A (en) * 1986-07-09 1988-09-06 Eta Systems, Inc. Integrated circuit clock bus layout delay system
JPH083773B2 (ja) * 1987-02-23 1996-01-17 株式会社日立製作所 大規模半導体論理回路
US4833677A (en) * 1987-06-12 1989-05-23 The United States Of America As Represented By The Secretary Of The Air Force Easily testable high speed architecture for large RAMS
JPH077809B2 (ja) * 1988-03-29 1995-01-30 株式会社東芝 集積回路
JP2684806B2 (ja) * 1989-02-03 1997-12-03 日本電気株式会社 集積回路
US5077676A (en) * 1990-03-30 1991-12-31 International Business Machines Corporation Reducing clock skew in large-scale integrated circuits
JPH04241011A (ja) * 1991-01-24 1992-08-28 Oki Electric Ind Co Ltd クロック駆動回路
US5109168A (en) * 1991-02-27 1992-04-28 Sun Microsystems, Inc. Method and apparatus for the design and optimization of a balanced tree for clock distribution in computer integrated circuits
JP2695078B2 (ja) * 1991-06-10 1997-12-24 株式会社東芝 データ処理装置クロック信号の分配方法
JPH04373160A (ja) * 1991-06-24 1992-12-25 Mitsubishi Electric Corp 半導体集積回路
JP3026387B2 (ja) * 1991-08-23 2000-03-27 沖電気工業株式会社 半導体集積回路
JPH05233092A (ja) * 1992-02-18 1993-09-10 Nec Ic Microcomput Syst Ltd クロック信号分配方法および分配回路
US5396129A (en) * 1992-05-25 1995-03-07 Matsushita Electronics Corporation Semiconductor integrated circuit apparatus comprising clock signal line formed in a ring shape

Also Published As

Publication number Publication date
EP0646854A3 (de) 1995-07-05
JP3112784B2 (ja) 2000-11-27
US5668484A (en) 1997-09-16
JPH0798616A (ja) 1995-04-11
DE69426406D1 (de) 2001-01-18
EP0646854A2 (de) 1995-04-05
EP0646854B1 (de) 2000-12-13

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