Classifications

• • G—PHYSICS
  • G02—OPTICS
  • G02B—OPTICAL ELEMENTS, SYSTEMS OR APPARATUS
  • G02B5/00—Optical elements other than lenses
  • G02B5/18—Diffraction gratings
  • G02B5/1876—Diffractive Fresnel lenses; Zone plates; Kinoforms
  • G02B5/189—Structurally combined with optical elements not having diffractive power
  • G02B5/1895—Structurally combined with optical elements not having diffractive power such optical elements having dioptric power
• • G—PHYSICS
  • G02—OPTICS
  • G02B—OPTICAL ELEMENTS, SYSTEMS OR APPARATUS
  • G02B5/00—Optical elements other than lenses
  • G02B5/18—Diffraction gratings
  • G02B5/1847—Manufacturing methods
  • G02B5/1857—Manufacturing methods using exposure or etching means, e.g. holography, photolithography, exposure to electron or ion beams
• • G—PHYSICS
  • G02—OPTICS
  • G02B—OPTICAL ELEMENTS, SYSTEMS OR APPARATUS
  • G02B5/00—Optical elements other than lenses
  • G02B5/18—Diffraction gratings
  • G02B5/1876—Diffractive Fresnel lenses; Zone plates; Kinoforms
• • G—PHYSICS
  • G02—OPTICS
  • G02B—OPTICAL ELEMENTS, SYSTEMS OR APPARATUS
  • G02B6/00—Light guides; Structural details of arrangements comprising light guides and other optical elements, e.g. couplings
  • G02B6/10—Light guides; Structural details of arrangements comprising light guides and other optical elements, e.g. couplings of the optical waveguide type
  • G02B6/12—Light guides; Structural details of arrangements comprising light guides and other optical elements, e.g. couplings of the optical waveguide type of the integrated circuit kind
  • G02B6/13—Integrated optical circuits characterised by the manufacturing method
  • G02B6/134—Integrated optical circuits characterised by the manufacturing method by substitution by dopant atoms
  • G02B6/1347—Integrated optical circuits characterised by the manufacturing method by substitution by dopant atoms using ion implantation
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
  • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
  • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
  • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
  • H01L21/185—Joining of semiconductor bodies for junction formation
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
  • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
  • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
  • H01L21/76—Making of isolation regions between components
  • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
  • H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
  • H01L21/76251—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques
  • H01L21/76254—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques with separation/delamination along an ion implanted layer, e.g. Smart-cut, Unibond
• • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
  • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
  • Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
  • Y10T156/00—Adhesive bonding and miscellaneous chemical manufacture
  • Y10T156/10—Methods of surface bonding and/or assembly therefor
  • Y10T156/1052—Methods of surface bonding and/or assembly therefor with cutting, punching, tearing or severing

Applications Claiming Priority (1)

Publications (2)

Family

ID=9454325

Family Applications (1)

Country Status (5)

Families Citing this family (87)

Family Cites Families (4)

• 1993
  • 1993-12-23 FR FR9315563A patent/FR2714524B1/fr not_active Expired - Fee Related
• 1994
  • 1994-11-23 US US08/344,560 patent/US5494835A/en not_active Expired - Lifetime
  • 1994-12-16 JP JP33364694A patent/JP3735880B2/ja not_active Expired - Fee Related
  • 1994-12-21 DE DE69423309T patent/DE69423309T2/de not_active Expired - Lifetime
  • 1994-12-21 EP EP94402969A patent/EP0660140B1/de not_active Expired - Lifetime

Also Published As

Similar Documents

Legal Events