DE69423309D1 - Herstellungsverfahren für eine Reliefstruktur auf einem Substrat aus Halbleitermaterial - Google Patents
Herstellungsverfahren für eine Reliefstruktur auf einem Substrat aus HalbleitermaterialInfo
- Publication number
- DE69423309D1 DE69423309D1 DE69423309T DE69423309T DE69423309D1 DE 69423309 D1 DE69423309 D1 DE 69423309D1 DE 69423309 T DE69423309 T DE 69423309T DE 69423309 T DE69423309 T DE 69423309T DE 69423309 D1 DE69423309 D1 DE 69423309D1
- Authority
- DE
- Germany
- Prior art keywords
- manufacturing
- semiconductor material
- substrate made
- relief structure
- relief
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
Classifications
-
- G—PHYSICS
- G02—OPTICS
- G02B—OPTICAL ELEMENTS, SYSTEMS OR APPARATUS
- G02B5/00—Optical elements other than lenses
- G02B5/18—Diffraction gratings
- G02B5/1876—Diffractive Fresnel lenses; Zone plates; Kinoforms
- G02B5/189—Structurally combined with optical elements not having diffractive power
- G02B5/1895—Structurally combined with optical elements not having diffractive power such optical elements having dioptric power
-
- G—PHYSICS
- G02—OPTICS
- G02B—OPTICAL ELEMENTS, SYSTEMS OR APPARATUS
- G02B5/00—Optical elements other than lenses
- G02B5/18—Diffraction gratings
- G02B5/1847—Manufacturing methods
- G02B5/1857—Manufacturing methods using exposure or etching means, e.g. holography, photolithography, exposure to electron or ion beams
-
- G—PHYSICS
- G02—OPTICS
- G02B—OPTICAL ELEMENTS, SYSTEMS OR APPARATUS
- G02B5/00—Optical elements other than lenses
- G02B5/18—Diffraction gratings
- G02B5/1876—Diffractive Fresnel lenses; Zone plates; Kinoforms
-
- G—PHYSICS
- G02—OPTICS
- G02B—OPTICAL ELEMENTS, SYSTEMS OR APPARATUS
- G02B6/00—Light guides; Structural details of arrangements comprising light guides and other optical elements, e.g. couplings
- G02B6/10—Light guides; Structural details of arrangements comprising light guides and other optical elements, e.g. couplings of the optical waveguide type
- G02B6/12—Light guides; Structural details of arrangements comprising light guides and other optical elements, e.g. couplings of the optical waveguide type of the integrated circuit kind
- G02B6/13—Integrated optical circuits characterised by the manufacturing method
- G02B6/134—Integrated optical circuits characterised by the manufacturing method by substitution by dopant atoms
- G02B6/1347—Integrated optical circuits characterised by the manufacturing method by substitution by dopant atoms using ion implantation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/185—Joining of semiconductor bodies for junction formation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
- H01L21/76251—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques
- H01L21/76254—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques with separation/delamination along an ion implanted layer, e.g. Smart-cut, Unibond
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
- Y10T156/00—Adhesive bonding and miscellaneous chemical manufacture
- Y10T156/10—Methods of surface bonding and/or assembly therefor
- Y10T156/1052—Methods of surface bonding and/or assembly therefor with cutting, punching, tearing or severing
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
FR9315563A FR2714524B1 (fr) | 1993-12-23 | 1993-12-23 | Procede de realisation d'une structure en relief sur un support en materiau semiconducteur |
Publications (2)
Publication Number | Publication Date |
---|---|
DE69423309D1 true DE69423309D1 (de) | 2000-04-13 |
DE69423309T2 DE69423309T2 (de) | 2000-09-14 |
Family
ID=9454325
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
DE69423309T Expired - Lifetime DE69423309T2 (de) | 1993-12-23 | 1994-12-21 | Herstellungsverfahren für eine Reliefstruktur auf einem Substrat aus Halbleitermaterial |
Country Status (5)
Country | Link |
---|---|
US (1) | US5494835A (de) |
EP (1) | EP0660140B1 (de) |
JP (1) | JP3735880B2 (de) |
DE (1) | DE69423309T2 (de) |
FR (1) | FR2714524B1 (de) |
Families Citing this family (87)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
FR2715501B1 (fr) * | 1994-01-26 | 1996-04-05 | Commissariat Energie Atomique | Procédé de dépôt de lames semiconductrices sur un support. |
FR2738671B1 (fr) * | 1995-09-13 | 1997-10-10 | Commissariat Energie Atomique | Procede de fabrication de films minces a materiau semiconducteur |
FR2747506B1 (fr) * | 1996-04-11 | 1998-05-15 | Commissariat Energie Atomique | Procede d'obtention d'un film mince de materiau semiconducteur comprenant notamment des composants electroniques |
FR2748850B1 (fr) | 1996-05-15 | 1998-07-24 | Commissariat Energie Atomique | Procede de realisation d'un film mince de materiau solide et applications de ce procede |
FR2748851B1 (fr) * | 1996-05-15 | 1998-08-07 | Commissariat Energie Atomique | Procede de realisation d'une couche mince de materiau semiconducteur |
KR100481994B1 (ko) * | 1996-08-27 | 2005-12-01 | 세이코 엡슨 가부시키가이샤 | 박리방법,박막디바이스의전사방법,및그것을이용하여제조되는박막디바이스,박막집적회로장치및액정표시장치 |
FR2755537B1 (fr) * | 1996-11-05 | 1999-03-05 | Commissariat Energie Atomique | Procede de fabrication d'un film mince sur un support et structure ainsi obtenue |
KR100232886B1 (ko) * | 1996-11-23 | 1999-12-01 | 김영환 | Soi 웨이퍼 제조방법 |
FR2756847B1 (fr) * | 1996-12-09 | 1999-01-08 | Commissariat Energie Atomique | Procede de separation d'au moins deux elements d'une structure en contact entre eux par implantation ionique |
FR2758907B1 (fr) * | 1997-01-27 | 1999-05-07 | Commissariat Energie Atomique | Procede d'obtention d'un film mince, notamment semiconducteur, comportant une zone protegee des ions, et impliquant une etape d'implantation ionique |
US6191007B1 (en) | 1997-04-28 | 2001-02-20 | Denso Corporation | Method for manufacturing a semiconductor substrate |
US6251754B1 (en) | 1997-05-09 | 2001-06-26 | Denso Corporation | Semiconductor substrate manufacturing method |
US6291313B1 (en) | 1997-05-12 | 2001-09-18 | Silicon Genesis Corporation | Method and device for controlled cleaving process |
US20070122997A1 (en) | 1998-02-19 | 2007-05-31 | Silicon Genesis Corporation | Controlled process and resulting device |
US6162705A (en) | 1997-05-12 | 2000-12-19 | Silicon Genesis Corporation | Controlled cleavage process and resulting device using beta annealing |
US6033974A (en) | 1997-05-12 | 2000-03-07 | Silicon Genesis Corporation | Method for controlled cleaving process |
US6582999B2 (en) * | 1997-05-12 | 2003-06-24 | Silicon Genesis Corporation | Controlled cleavage process using pressurized fluid |
US6027988A (en) * | 1997-05-28 | 2000-02-22 | The Regents Of The University Of California | Method of separating films from bulk substrates by plasma immersion ion implantation |
US5877070A (en) * | 1997-05-31 | 1999-03-02 | Max-Planck Society | Method for the transfer of thin layers of monocrystalline material to a desirable substrate |
US5949108A (en) * | 1997-06-30 | 1999-09-07 | Intel Corporation | Semiconductor device with reduced capacitance |
DE69733471D1 (de) * | 1997-07-03 | 2005-07-14 | St Microelectronics Srl | Verfahren zur Herstellung von Geräten in einem halbleitenden Substrat |
US6534380B1 (en) * | 1997-07-18 | 2003-03-18 | Denso Corporation | Semiconductor substrate and method of manufacturing the same |
US6548382B1 (en) | 1997-07-18 | 2003-04-15 | Silicon Genesis Corporation | Gettering technique for wafers made using a controlled cleaving process |
FR2766620B1 (fr) | 1997-07-22 | 2000-12-01 | Commissariat Energie Atomique | Realisation de microstructures ou de nanostructures sur un support |
FR2767416B1 (fr) | 1997-08-12 | 1999-10-01 | Commissariat Energie Atomique | Procede de fabrication d'un film mince de materiau solide |
FR2773261B1 (fr) | 1997-12-30 | 2000-01-28 | Commissariat Energie Atomique | Procede pour le transfert d'un film mince comportant une etape de creation d'inclusions |
US5933750A (en) * | 1998-04-03 | 1999-08-03 | Motorola, Inc. | Method of fabricating a semiconductor device with a thinned substrate |
US5909627A (en) * | 1998-05-18 | 1999-06-01 | Philips Electronics North America Corporation | Process for production of thin layers of semiconductor material |
US6291326B1 (en) | 1998-06-23 | 2001-09-18 | Silicon Genesis Corporation | Pre-semiconductor process implant and post-process film separation |
US6054370A (en) * | 1998-06-30 | 2000-04-25 | Intel Corporation | Method of delaminating a pre-fabricated transistor layer from a substrate for placement on another wafer |
FR2784795B1 (fr) * | 1998-10-16 | 2000-12-01 | Commissariat Energie Atomique | Structure comportant une couche mince de materiau composee de zones conductrices et de zones isolantes et procede de fabrication d'une telle structure |
US20040229443A1 (en) * | 1998-12-31 | 2004-11-18 | Bower Robert W. | Structures, materials and methods for fabrication of nanostructures by transposed split of ion cut materials |
US20050124142A1 (en) * | 1998-12-31 | 2005-06-09 | Bower Robert W. | Transposed split of ion cut materials |
US6346458B1 (en) * | 1998-12-31 | 2002-02-12 | Robert W. Bower | Transposed split of ion cut materials |
US6287941B1 (en) | 1999-04-21 | 2001-09-11 | Silicon Genesis Corporation | Surface finishing of SOI substrates using an EPI process |
US6204151B1 (en) * | 1999-04-21 | 2001-03-20 | Silicon Genesis Corporation | Smoothing method for cleaved films made using thermal treatment |
US6881644B2 (en) * | 1999-04-21 | 2005-04-19 | Silicon Genesis Corporation | Smoothing method for cleaved films made using a release layer |
US6171965B1 (en) * | 1999-04-21 | 2001-01-09 | Silicon Genesis Corporation | Treatment method of cleaved film for the manufacture of substrates |
EP1939932A1 (de) * | 1999-08-10 | 2008-07-02 | Silicon Genesis Corporation | Ein Substrat mit einer verspannten Silizium-Germanium Trennschicht |
US6500732B1 (en) | 1999-08-10 | 2002-12-31 | Silicon Genesis Corporation | Cleaving process to fabricate multilayered substrates using low implantation doses |
US6263941B1 (en) | 1999-08-10 | 2001-07-24 | Silicon Genesis Corporation | Nozzle for cleaving substrates |
US6221740B1 (en) | 1999-08-10 | 2001-04-24 | Silicon Genesis Corporation | Substrate cleaving tool and method |
FR2809867B1 (fr) * | 2000-05-30 | 2003-10-24 | Commissariat Energie Atomique | Substrat fragilise et procede de fabrication d'un tel substrat |
US6303469B1 (en) | 2000-06-07 | 2001-10-16 | Micron Technology, Inc. | Thin microelectronic substrates and methods of manufacture |
JP2002124652A (ja) * | 2000-10-16 | 2002-04-26 | Seiko Epson Corp | 半導体基板の製造方法、半導体基板、電気光学装置並びに電子機器 |
US7407869B2 (en) * | 2000-11-27 | 2008-08-05 | S.O.I.Tec Silicon On Insulator Technologies | Method for manufacturing a free-standing substrate made of monocrystalline semiconductor material |
FR2835096B1 (fr) * | 2002-01-22 | 2005-02-18 | Procede de fabrication d'un substrat auto-porte en materiau semi-conducteur monocristallin | |
US7094667B1 (en) | 2000-12-28 | 2006-08-22 | Bower Robert W | Smooth thin film layers produced by low temperature hydrogen ion cut |
FR2823599B1 (fr) | 2001-04-13 | 2004-12-17 | Commissariat Energie Atomique | Substrat demomtable a tenue mecanique controlee et procede de realisation |
JP2004063730A (ja) * | 2002-07-29 | 2004-02-26 | Shin Etsu Handotai Co Ltd | Soiウェーハの製造方法 |
US7508034B2 (en) * | 2002-09-25 | 2009-03-24 | Sharp Kabushiki Kaisha | Single-crystal silicon substrate, SOI substrate, semiconductor device, display device, and manufacturing method of semiconductor device |
JP2004119943A (ja) * | 2002-09-30 | 2004-04-15 | Renesas Technology Corp | 半導体ウェハおよびその製造方法 |
US8187377B2 (en) | 2002-10-04 | 2012-05-29 | Silicon Genesis Corporation | Non-contact etch annealing of strained layers |
FR2848336B1 (fr) * | 2002-12-09 | 2005-10-28 | Commissariat Energie Atomique | Procede de realisation d'une structure contrainte destinee a etre dissociee |
FR2856844B1 (fr) * | 2003-06-24 | 2006-02-17 | Commissariat Energie Atomique | Circuit integre sur puce de hautes performances |
FR2857953B1 (fr) | 2003-07-21 | 2006-01-13 | Commissariat Energie Atomique | Structure empilee, et procede pour la fabriquer |
FR2861497B1 (fr) * | 2003-10-28 | 2006-02-10 | Soitec Silicon On Insulator | Procede de transfert catastrophique d'une couche fine apres co-implantation |
US7542197B2 (en) * | 2003-11-01 | 2009-06-02 | Silicon Quest Kabushiki-Kaisha | Spatial light modulator featured with an anti-reflective structure |
US7354815B2 (en) * | 2003-11-18 | 2008-04-08 | Silicon Genesis Corporation | Method for fabricating semiconductor devices using strained silicon bearing material |
US20060043534A1 (en) * | 2004-08-26 | 2006-03-02 | Kirby Kyle K | Microfeature dies with porous regions, and associated methods and systems |
FR2878535B1 (fr) * | 2004-11-29 | 2007-01-05 | Commissariat Energie Atomique | Procede de realisation d'un substrat demontable |
US7635637B2 (en) * | 2005-07-25 | 2009-12-22 | Fairchild Semiconductor Corporation | Semiconductor structures formed on substrates and methods of manufacturing the same |
US7674687B2 (en) * | 2005-07-27 | 2010-03-09 | Silicon Genesis Corporation | Method and structure for fabricating multiple tiled regions onto a plate using a controlled cleaving process |
FR2889887B1 (fr) * | 2005-08-16 | 2007-11-09 | Commissariat Energie Atomique | Procede de report d'une couche mince sur un support |
FR2891281B1 (fr) | 2005-09-28 | 2007-12-28 | Commissariat Energie Atomique | Procede de fabrication d'un element en couches minces. |
DE102006007293B4 (de) * | 2006-01-31 | 2023-04-06 | OSRAM Opto Semiconductors Gesellschaft mit beschränkter Haftung | Verfahren zum Herstellen eines Quasi-Substratwafers und ein unter Verwendung eines solchen Quasi-Substratwafers hergestellter Halbleiterkörper |
US8993410B2 (en) | 2006-09-08 | 2015-03-31 | Silicon Genesis Corporation | Substrate cleaving under controlled stress conditions |
US7811900B2 (en) | 2006-09-08 | 2010-10-12 | Silicon Genesis Corporation | Method and structure for fabricating solar cells using a thick layer transfer process |
US8293619B2 (en) | 2008-08-28 | 2012-10-23 | Silicon Genesis Corporation | Layer transfer of films utilizing controlled propagation |
US9362439B2 (en) | 2008-05-07 | 2016-06-07 | Silicon Genesis Corporation | Layer transfer of films utilizing controlled shear region |
FR2910179B1 (fr) * | 2006-12-19 | 2009-03-13 | Commissariat Energie Atomique | PROCEDE DE FABRICATION DE COUCHES MINCES DE GaN PAR IMPLANTATION ET RECYCLAGE D'UN SUBSTRAT DE DEPART |
US8101500B2 (en) * | 2007-09-27 | 2012-01-24 | Fairchild Semiconductor Corporation | Semiconductor device with (110)-oriented silicon |
FR2922359B1 (fr) * | 2007-10-12 | 2009-12-18 | Commissariat Energie Atomique | Procede de fabrication d'une structure micro-electronique impliquant un collage moleculaire |
FR2925221B1 (fr) * | 2007-12-17 | 2010-02-19 | Commissariat Energie Atomique | Procede de transfert d'une couche mince |
US7749884B2 (en) * | 2008-05-06 | 2010-07-06 | Astrowatt, Inc. | Method of forming an electronic device using a separation-enhancing species |
WO2009143026A2 (en) * | 2008-05-17 | 2009-11-26 | Astrowatt, Inc. | Method of forming an electronic device using a separation technique |
US8330126B2 (en) | 2008-08-25 | 2012-12-11 | Silicon Genesis Corporation | Race track configuration and method for wafering silicon solar substrates |
US8039877B2 (en) * | 2008-09-09 | 2011-10-18 | Fairchild Semiconductor Corporation | (110)-oriented p-channel trench MOSFET having high-K gate dielectric |
US7816225B2 (en) | 2008-10-30 | 2010-10-19 | Corning Incorporated | Methods and apparatus for producing semiconductor on insulator structures using directed exfoliation |
TWI451534B (zh) * | 2008-10-30 | 2014-09-01 | Corning Inc | 使用定向剝離作用製造絕緣體上半導體結構之方法及裝置 |
JP5310004B2 (ja) * | 2009-01-07 | 2013-10-09 | 信越半導体株式会社 | 貼り合わせウェーハの製造方法 |
US8329557B2 (en) | 2009-05-13 | 2012-12-11 | Silicon Genesis Corporation | Techniques for forming thin films by implantation with reduced channeling |
FR2947098A1 (fr) * | 2009-06-18 | 2010-12-24 | Commissariat Energie Atomique | Procede de transfert d'une couche mince sur un substrat cible ayant un coefficient de dilatation thermique different de celui de la couche mince |
FR2978600B1 (fr) | 2011-07-25 | 2014-02-07 | Soitec Silicon On Insulator | Procede et dispositif de fabrication de couche de materiau semi-conducteur |
US20180033609A1 (en) * | 2016-07-28 | 2018-02-01 | QMAT, Inc. | Removal of non-cleaved/non-transferred material from donor substrate |
FR3073082B1 (fr) | 2017-10-31 | 2019-10-11 | Soitec | Procede de fabrication d'un film sur un support presentant une surface non plane |
CN116387241A (zh) * | 2023-04-21 | 2023-07-04 | 中芯先锋集成电路制造(绍兴)有限公司 | 绝缘体上半导体衬底的制造方法及半导体器件的制造方法 |
Family Cites Families (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4717683A (en) * | 1986-09-23 | 1988-01-05 | Motorola Inc. | CMOS process |
GB8725497D0 (en) * | 1987-10-30 | 1987-12-02 | Atomic Energy Authority Uk | Isolation of silicon |
US5196355A (en) * | 1989-04-24 | 1993-03-23 | Ibis Technology Corporation | Simox materials through energy variation |
FR2681472B1 (fr) * | 1991-09-18 | 1993-10-29 | Commissariat Energie Atomique | Procede de fabrication de films minces de materiau semiconducteur. |
-
1993
- 1993-12-23 FR FR9315563A patent/FR2714524B1/fr not_active Expired - Fee Related
-
1994
- 1994-11-23 US US08/344,560 patent/US5494835A/en not_active Expired - Lifetime
- 1994-12-16 JP JP33364694A patent/JP3735880B2/ja not_active Expired - Fee Related
- 1994-12-21 DE DE69423309T patent/DE69423309T2/de not_active Expired - Lifetime
- 1994-12-21 EP EP94402969A patent/EP0660140B1/de not_active Expired - Lifetime
Also Published As
Publication number | Publication date |
---|---|
US5494835A (en) | 1996-02-27 |
DE69423309T2 (de) | 2000-09-14 |
JP3735880B2 (ja) | 2006-01-18 |
FR2714524A1 (fr) | 1995-06-30 |
FR2714524B1 (fr) | 1996-01-26 |
EP0660140A1 (de) | 1995-06-28 |
EP0660140B1 (de) | 2000-03-08 |
JPH07215800A (ja) | 1995-08-15 |
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Legal Events
Date | Code | Title | Description |
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8364 | No opposition during term of opposition | ||
8327 | Change in the person/name/address of the patent owner |
Owner name: S.O.I.TEC SILICON ON INSULATOR TECHNOLOGIES S., FR |
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Ref document number: 660140 Country of ref document: EP Representative=s name: GRUENECKER, KINKELDEY, STOCKMAIR & SCHWANHAEUS, DE |
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Ref document number: 660140 Country of ref document: EP Owner name: SOITEC, FR Free format text: FORMER OWNER: S.O.I.TEC SILICON ON INSULATOR TECHNOLOGIES S.A., BERNIN, FR Effective date: 20120905 |
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