DE69418012T2 - Frequenzmultiplizierer mit einer Baumstruktur von CMOS logischen Gattern des Typs "Exclusiv-ODER" - Google Patents

Frequenzmultiplizierer mit einer Baumstruktur von CMOS logischen Gattern des Typs "Exclusiv-ODER"

Info

Publication number
DE69418012T2
DE69418012T2 DE69418012T DE69418012T DE69418012T2 DE 69418012 T2 DE69418012 T2 DE 69418012T2 DE 69418012 T DE69418012 T DE 69418012T DE 69418012 T DE69418012 T DE 69418012T DE 69418012 T2 DE69418012 T2 DE 69418012T2
Authority
DE
Germany
Prior art keywords
exclusive
type
tree structure
logic gates
frequency multiplier
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE69418012T
Other languages
English (en)
Other versions
DE69418012D1 (de
Inventor
Roland Marbot
Bihan Jean-Claude Le
Andrew Cofler
Reza Nezamzadeh-Moosavi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
BULL S.A., LES CLAYES SOUS BOIS, FR
Original Assignee
Bull SA
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Bull SA filed Critical Bull SA
Publication of DE69418012D1 publication Critical patent/DE69418012D1/de
Application granted granted Critical
Publication of DE69418012T2 publication Critical patent/DE69418012T2/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/20—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits characterised by logic function, e.g. AND, OR, NOR, NOT circuits
    • H03K19/21—EXCLUSIVE-OR circuits, i.e. giving output if input signal exists at only one input; COINCIDENCE circuits, i.e. giving output only if all input signals are identical
    • H03K19/215—EXCLUSIVE-OR circuits, i.e. giving output if input signal exists at only one input; COINCIDENCE circuits, i.e. giving output only if all input signals are identical using field-effect transistors
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K5/00006—Changing the frequency
DE69418012T 1993-12-24 1994-12-22 Frequenzmultiplizierer mit einer Baumstruktur von CMOS logischen Gattern des Typs "Exclusiv-ODER" Expired - Lifetime DE69418012T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
FR9315631A FR2714550B1 (fr) 1993-12-24 1993-12-24 Arbre de portes logiques OU-Exclusif et multiplieur de fréquence l'incorporant.

Publications (2)

Publication Number Publication Date
DE69418012D1 DE69418012D1 (de) 1999-05-27
DE69418012T2 true DE69418012T2 (de) 1999-08-26

Family

ID=9454383

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69418012T Expired - Lifetime DE69418012T2 (de) 1993-12-24 1994-12-22 Frequenzmultiplizierer mit einer Baumstruktur von CMOS logischen Gattern des Typs "Exclusiv-ODER"

Country Status (7)

Country Link
US (1) US5614841A (de)
EP (1) EP0660525B1 (de)
JP (1) JP2877709B2 (de)
CA (1) CA2137340C (de)
DE (1) DE69418012T2 (de)
ES (1) ES2134917T3 (de)
FR (1) FR2714550B1 (de)

Cited By (1)

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Publication number Priority date Publication date Assignee Title
DE10301239A1 (de) * 2003-01-15 2004-08-05 Infineon Technologies Ag Verfahren und Vorrichtung zur Erzeugung von verzögerten Signalen

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US5721501A (en) * 1995-07-26 1998-02-24 Kabushiki Kaisha Toshiba Frequency multiplier and semiconductor integrated circuit employing the same
GB2308249A (en) * 1995-12-13 1997-06-18 Altera Corp A clock frequency multiplier whose output waveform is insensitive to input duty cycle
GB2308250A (en) * 1995-12-13 1997-06-18 Altera Corp Clock frequency multiplier using a delay line loop
US5821785A (en) * 1996-08-02 1998-10-13 Rockwell Int'l Corp. Clock signal frequency multiplier
US5864246A (en) * 1997-03-31 1999-01-26 Lsi Logic Corporation Method and apparatus for doubling a clock signal using phase interpolation
FR2768872B1 (fr) * 1997-09-25 2000-09-08 Sgs Thomson Microelectronics Porte logique ou-exclusif a quatre entrees complementaires deux a deux et a deux sorties complementaires, et multiplieur de frequence l'incorporant
US6023182A (en) 1997-12-31 2000-02-08 Intel Corporation High gain pulse generator circuit with clock gating
US5963071A (en) * 1998-01-22 1999-10-05 Nanoamp Solutions, Inc. Frequency doubler with adjustable duty cycle
US6037812A (en) * 1998-05-18 2000-03-14 National Semiconductor Corporation Delay locked loop (DLL) based clock synthesis
US6194917B1 (en) * 1999-01-21 2001-02-27 National Semiconductor Corporation XOR differential phase detector with transconductance circuit as output charge pump
CA2270516C (en) * 1999-04-30 2009-11-17 Mosaid Technologies Incorporated Frequency-doubling delay locked loop
US6424194B1 (en) 1999-06-28 2002-07-23 Broadcom Corporation Current-controlled CMOS logic family
US6304104B1 (en) * 1999-09-13 2001-10-16 Rambus, Inc. Method and apparatus for reducing worst case power
US6794907B2 (en) * 2000-09-15 2004-09-21 Broadcom Corporation Low jitter high speed CMOS to CML clock converter
US6480045B2 (en) 2001-01-05 2002-11-12 Thomson Licensing S.A. Digital frequency multiplier
US6753709B2 (en) * 2002-06-28 2004-06-22 Agere Systems Inc. Digital clock rate multiplier method and apparatus
US7103832B2 (en) * 2003-12-04 2006-09-05 International Business Machines Corporation Scalable cyclic redundancy check circuit
US7598811B2 (en) * 2005-07-29 2009-10-06 Broadcom Corporation Current-controlled CMOS (C3MOS) fully differential integrated wideband amplifier/equalizer with adjustable gain and frequency response without additional power or loading
US7362174B2 (en) * 2005-07-29 2008-04-22 Broadcom Corporation Current-controlled CMOS (C3MOS) wideband input data amplifier for reduced differential and common-mode reflection
US7598788B2 (en) * 2005-09-06 2009-10-06 Broadcom Corporation Current-controlled CMOS (C3MOS) fully differential integrated delay cell with variable delay and high bandwidth
KR101428027B1 (ko) * 2013-02-28 2014-08-11 동국대학교 산학협력단 비적층적 및 대칭적 전류모드 논리회로
KR102276890B1 (ko) 2014-08-14 2021-07-12 삼성전자주식회사 주파수 더블러
US10797722B2 (en) * 2016-06-10 2020-10-06 The Boeing Company System and method for providing hardware based fast and secure expansion and compression functions
JP7343709B2 (ja) 2021-01-14 2023-09-12 チャンシン メモリー テクノロジーズ インコーポレイテッド 誤り訂正システム
CN114765056A (zh) 2021-01-14 2022-07-19 长鑫存储技术有限公司 存储系统
KR20220107007A (ko) 2021-01-14 2022-08-01 창신 메모리 테크놀로지즈 아이엔씨 비교 시스템

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US3252011A (en) * 1964-03-16 1966-05-17 Rca Corp Logic circuit employing transistor means whereby steady state power dissipation is minimized
US3993957A (en) * 1976-03-08 1976-11-23 International Business Machines Corporation Clock converter circuit
US4367420A (en) * 1980-06-02 1983-01-04 Thompson Foss Incorporated Dynamic logic circuits operating in a differential mode for array processing
JPS58101525A (ja) * 1981-12-14 1983-06-16 Fujitsu Ltd 論理回路
EP0101896B1 (de) * 1982-07-30 1988-05-18 Kabushiki Kaisha Toshiba MOS logische Schaltung
JPS5992624A (ja) * 1982-11-19 1984-05-28 Toshiba Corp Ｃｍｏｓ論理回路
US4710650A (en) * 1986-08-26 1987-12-01 American Telephone And Telegraph Company, At&T Bell Laboratories Dual domino CMOS logic circuit, including complementary vectorization and integration
JPH02203621A (ja) * 1989-02-02 1990-08-13 Matsushita Electric Ind Co Ltd エクスクルーシブノア回路
FR2658015B1 (fr) * 1990-02-06 1994-07-29 Bull Sa Circuit verrouille en phase et multiplieur de frequence en resultant.
US5120989A (en) * 1991-02-04 1992-06-09 The United States Of America As Represented By The Secretary Of The Army Simplified clock distribution in electronic systems
US5180994A (en) * 1991-02-14 1993-01-19 The Regents Of The University Of California Differential-logic ring oscillator with quadrature outputs
JPH04290010A (ja) * 1991-03-19 1992-10-14 Fujitsu Ltd 論理回路
JPH04329022A (ja) * 1991-04-30 1992-11-17 Fujitsu Ltd 発振回路
WO1993017500A1 (en) * 1992-02-20 1993-09-02 Northern Telecom Limited Differential ecl circuit
US5448181A (en) * 1992-11-06 1995-09-05 Xilinx, Inc. Output buffer circuit having reduced switching noise

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE10301239A1 (de) * 2003-01-15 2004-08-05 Infineon Technologies Ag Verfahren und Vorrichtung zur Erzeugung von verzögerten Signalen
DE10301239B4 (de) * 2003-01-15 2005-04-28 Infineon Technologies Ag Verfahren und Vorrichtung zur Erzeugung von verzögerten Signalen
US7123071B2 (en) 2003-01-15 2006-10-17 Infineon Technologies Ag Method and device for producing delayed signals

Also Published As

Publication number Publication date
JP2877709B2 (ja) 1999-03-31
FR2714550A1 (fr) 1995-06-30
FR2714550B1 (fr) 1996-02-02
CA2137340A1 (fr) 1995-06-25
ES2134917T3 (es) 1999-10-16
EP0660525B1 (de) 1999-04-21
CA2137340C (fr) 1999-06-01
JPH07212222A (ja) 1995-08-11
EP0660525A1 (de) 1995-06-28
US5614841A (en) 1997-03-25
DE69418012D1 (de) 1999-05-27

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8327 Change in the person/name/address of the patent owner

Owner name: BULL S.A., LES CLAYES SOUS BOIS, FR