DE69408657T2 - TAB-Lötflächengeometrie für Halbleiterbauelemente - Google Patents

TAB-Lötflächengeometrie für Halbleiterbauelemente

Info

Publication number
DE69408657T2
DE69408657T2 DE69408657T DE69408657T DE69408657T2 DE 69408657 T2 DE69408657 T2 DE 69408657T2 DE 69408657 T DE69408657 T DE 69408657T DE 69408657 T DE69408657 T DE 69408657T DE 69408657 T2 DE69408657 T2 DE 69408657T2
Authority
DE
Germany
Prior art keywords
semiconductor components
surface geometry
soldering surface
tab soldering
tab
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE69408657T
Other languages
English (en)
Other versions
DE69408657D1 (de
Inventor
Kimihiro Ikebe
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp filed Critical Toshiba Corp
Publication of DE69408657D1 publication Critical patent/DE69408657D1/de
Application granted granted Critical
Publication of DE69408657T2 publication Critical patent/DE69408657T2/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10Bump connectors ; Manufacturing methods related thereto
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/50Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/60Attaching or detaching leads or other conductive members, to be used for carrying current to or from the device in operation
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/48Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495Lead-frames or other flat leads
    • H01L23/49572Lead-frames or other flat leads consisting of thin flexible metallic tape with or without a film carrier
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10Bump connectors ; Manufacturing methods related thereto
    • H01L24/12Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L24/13Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/12Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/12Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001Core members of the bump connector
    • H01L2224/13099Material
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01005Boron [B]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01006Carbon [C]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01013Aluminum [Al]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01029Copper [Cu]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01033Arsenic [As]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01079Gold [Au]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01082Lead [Pb]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10Details of semiconductor or other solid state devices to be connected
    • H01L2924/11Device type
    • H01L2924/14Integrated circuits
DE69408657T 1993-12-27 1994-12-19 TAB-Lötflächengeometrie für Halbleiterbauelemente Expired - Lifetime DE69408657T2 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP33275593 1993-12-27
JP6295226A JPH07235564A (ja) 1993-12-27 1994-11-29 半導体装置

Publications (2)

Publication Number Publication Date
DE69408657D1 DE69408657D1 (de) 1998-04-02
DE69408657T2 true DE69408657T2 (de) 1998-07-09

Family

ID=26560171

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69408657T Expired - Lifetime DE69408657T2 (de) 1993-12-27 1994-12-19 TAB-Lötflächengeometrie für Halbleiterbauelemente

Country Status (7)

Country Link
US (1) US5569964A (de)
EP (1) EP0664563B1 (de)
JP (1) JPH07235564A (de)
KR (1) KR0150497B1 (de)
CN (1) CN1099135C (de)
DE (1) DE69408657T2 (de)
TW (1) TW268149B (de)

Families Citing this family (33)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH09260575A (ja) * 1996-03-22 1997-10-03 Mitsubishi Electric Corp 半導体装置及びリードフレーム
US5814892A (en) * 1996-06-07 1998-09-29 Lsi Logic Corporation Semiconductor die with staggered bond pads
US5817540A (en) * 1996-09-20 1998-10-06 Micron Technology, Inc. Method of fabricating flip-chip on leads devices and resulting assemblies
KR100210711B1 (ko) * 1996-10-01 1999-07-15 윤종용 반도체 칩 구조
JP3493118B2 (ja) * 1997-07-25 2004-02-03 沖電気工業株式会社 半導体素子及び半導体装置
US6104619A (en) * 1997-12-16 2000-08-15 Kabushiki Kaisha Toshiba Tape carrier package and its fabrication method therefor
JP3480291B2 (ja) * 1998-01-08 2003-12-15 日立電線株式会社 半導体装置及び電子装置
US6251768B1 (en) * 1999-03-08 2001-06-26 Silicon Integrated Systems Corp. Method of arranging the staggered shape bond pads layers for effectively reducing the size of a die
JP3781967B2 (ja) 2000-12-25 2006-06-07 株式会社日立製作所 表示装置
JP2002359461A (ja) * 2001-06-01 2002-12-13 Nec Corp 電子部品の実装方法および実装構造体、メタルマスク
US6577002B1 (en) * 2001-11-29 2003-06-10 Sun Microsystems, Inc. 180 degree bump placement layout for an integrated circuit power grid
JP3573150B2 (ja) 2002-01-25 2004-10-06 セイコーエプソン株式会社 半導体装置及びこれを含む電気光学装置
JP2004342993A (ja) * 2003-05-19 2004-12-02 Seiko Epson Corp 半導体装置、電子デバイス、電子機器および半導体装置の製造方法
JP2005062582A (ja) * 2003-08-18 2005-03-10 Hitachi Displays Ltd 表示装置
US6936970B2 (en) * 2003-09-30 2005-08-30 General Electric Company Method and apparatus for a unidirectional switching, current limited cutoff circuit for an electronic ballast
JP2005159235A (ja) 2003-11-28 2005-06-16 Seiko Epson Corp 半導体装置及びその製造方法、配線基板、電子モジュール並びに電子機器
JP3807502B2 (ja) 2003-11-28 2006-08-09 セイコーエプソン株式会社 半導体装置の製造方法
JP3687674B2 (ja) * 2003-12-12 2005-08-24 セイコーエプソン株式会社 半導体装置、半導体チップ、電子モジュール並びに電子機器
KR100632472B1 (ko) 2004-04-14 2006-10-09 삼성전자주식회사 측벽이 비도전성인 미세 피치 범프 구조를 가지는미세전자소자칩, 이의 패키지, 이를 포함하는액정디스플레이장치 및 이의 제조방법
US20060131726A1 (en) * 2004-12-22 2006-06-22 Bruch Thomas P Arrangement of input/output pads on an integrated circuit
US20060255473A1 (en) * 2005-05-16 2006-11-16 Stats Chippac Ltd. Flip chip interconnect solder mask
US9258904B2 (en) * 2005-05-16 2016-02-09 Stats Chippac, Ltd. Semiconductor device and method of forming narrow interconnect sites on substrate with elongated mask openings
US7863737B2 (en) * 2006-04-01 2011-01-04 Stats Chippac Ltd. Integrated circuit package system with wire bond pattern
JP2007150370A (ja) * 2007-03-15 2007-06-14 Seiko Epson Corp 半導体モジュール、電子デバイス、電子機器および半導体モジュールの製造方法
CN101308830A (zh) * 2007-05-18 2008-11-19 飞思卡尔半导体(中国)有限公司 用于半导体封装的引线框
JP5395407B2 (ja) * 2008-11-12 2014-01-22 ルネサスエレクトロニクス株式会社 表示装置駆動用半導体集積回路装置および表示装置駆動用半導体集積回路装置の製造方法
US8288871B1 (en) * 2011-04-27 2012-10-16 Taiwan Semiconductor Manufacturing Company, Ltd. Reduced-stress bump-on-trace (BOT) structures
US10833033B2 (en) 2011-07-27 2020-11-10 Taiwan Semiconductor Manufacturing Co., Ltd. Bump structure having a side recess and semiconductor structure including the same
US8853853B2 (en) 2011-07-27 2014-10-07 Taiwan Semiconductor Manufacturing Company, Ltd. Bump structures
US9105533B2 (en) 2011-07-27 2015-08-11 Taiwan Semiconductor Manufacturing Company, Ltd. Bump structure having a single side recess
JP6028908B2 (ja) * 2012-07-27 2016-11-24 セイコーエプソン株式会社 半導体装置
US10510722B2 (en) * 2017-06-20 2019-12-17 Taiwan Semiconductor Manufacturing Company Ltd. Semiconductor device and method for manufacturing the same
KR102634290B1 (ko) 2018-11-09 2024-02-06 동우 화인켐 주식회사 패드 전극부 및 이를 갖는 터치센서

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4866504A (en) * 1986-05-05 1989-09-12 Itt Corporation Direct interconnection for use between a semiconductor and a pin connector or the like
JPS63124434A (ja) * 1986-11-12 1988-05-27 Mitsubishi Electric Corp 半導体装置の製造方法
JPH03196634A (ja) * 1989-12-26 1991-08-28 Nec Corp 半導体装置の製造方法
US5173763A (en) * 1991-02-11 1992-12-22 International Business Machines Corporation Electronic packaging with varying height connectors
JP3044872B2 (ja) * 1991-09-25 2000-05-22 ソニー株式会社 半導体装置

Also Published As

Publication number Publication date
KR0150497B1 (ko) 1998-12-01
KR950021300A (ko) 1995-07-26
DE69408657D1 (de) 1998-04-02
JPH07235564A (ja) 1995-09-05
TW268149B (de) 1996-01-11
US5569964A (en) 1996-10-29
EP0664563B1 (de) 1998-02-25
EP0664563A1 (de) 1995-07-26
CN1099135C (zh) 2003-01-15
CN1111402A (zh) 1995-11-08

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