DE69331817D1 - Herstellungsverfahren eines Halbleitersubstrat - Google Patents

Herstellungsverfahren eines Halbleitersubstrat

Info

Publication number
DE69331817D1
DE69331817D1 DE69331817T DE69331817T DE69331817D1 DE 69331817 D1 DE69331817 D1 DE 69331817D1 DE 69331817 T DE69331817 T DE 69331817T DE 69331817 T DE69331817 T DE 69331817T DE 69331817 D1 DE69331817 D1 DE 69331817D1
Authority
DE
Germany
Prior art keywords
manufacturing
semiconductor substrate
semiconductor
substrate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE69331817T
Other languages
English (en)
Other versions
DE69331817T2 (de
Inventor
Kenji Yamagata
Takao Yonehara
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Canon Inc
Original Assignee
Canon Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Canon Inc filed Critical Canon Inc
Application granted granted Critical
Publication of DE69331817D1 publication Critical patent/DE69331817D1/de
Publication of DE69331817T2 publication Critical patent/DE69331817T2/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/30604—Chemical etching
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • H01L21/76251—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • H01L21/76251—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques
    • H01L21/76256—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques using silicon etch back techniques, e.g. BESOI, ELTRAN
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
    • H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
    • H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H01L2221/68363—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support used in a transfer process involving transfer directly from an origin substrate to a target substrate without use of an intermediate handle substrate
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S438/00—Semiconductor device manufacturing: process
    • Y10S438/96—Porous semiconductor
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S438/00—Semiconductor device manufacturing: process
    • Y10S438/977—Thinning or removal of substrate
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T428/00—Stock material or miscellaneous articles
    • Y10T428/249921—Web or sheet containing structurally defined element or component
    • Y10T428/249953—Composite having voids in a component [e.g., porous, cellular, etc.]
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T428/00—Stock material or miscellaneous articles
    • Y10T428/249921—Web or sheet containing structurally defined element or component
    • Y10T428/249953—Composite having voids in a component [e.g., porous, cellular, etc.]
    • Y10T428/249967—Inorganic matrix in void-containing component
DE69331817T 1992-01-31 1993-01-29 Herstellungsverfahren eines Halbleitersubstrat Expired - Lifetime DE69331817T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP01651192A JP3416163B2 (ja) 1992-01-31 1992-01-31 半導体基板及びその作製方法

Publications (2)

Publication Number Publication Date
DE69331817D1 true DE69331817D1 (de) 2002-05-23
DE69331817T2 DE69331817T2 (de) 2002-08-29

Family

ID=11918297

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69331817T Expired - Lifetime DE69331817T2 (de) 1992-01-31 1993-01-29 Herstellungsverfahren eines Halbleitersubstrat

Country Status (4)

Country Link
US (2) US5405802A (de)
EP (1) EP0553857B1 (de)
JP (1) JP3416163B2 (de)
DE (1) DE69331817T2 (de)

Families Citing this family (125)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP1251556B1 (de) * 1992-01-30 2010-03-24 Canon Kabushiki Kaisha Herstellungsverfahren für Halbleitersubstrat
JP3416163B2 (ja) * 1992-01-31 2003-06-16 キヤノン株式会社 半導体基板及びその作製方法
US6110833A (en) * 1998-03-03 2000-08-29 Advanced Micro Devices, Inc. Elimination of oxynitride (ONO) etch residue and polysilicon stringers through isolation of floating gates on adjacent bitlines by polysilicon oxidation
JPH07211916A (ja) * 1994-01-19 1995-08-11 Sony Corp トランジスタ素子及びその作製方法
GB9401770D0 (en) * 1994-01-31 1994-03-23 Philips Electronics Uk Ltd Manufacture of electronic devices comprising thin-film circuits
US6004406A (en) * 1994-06-16 1999-12-21 Nec Corporation Silicon on insulating substrate
JPH08264400A (ja) * 1995-03-28 1996-10-11 Mitsubishi Electric Corp シリコン単結晶ウェハおよびその表面の熱酸化方法
DE69628505T2 (de) * 1995-07-21 2004-05-06 Canon K.K. Halbleitendes Substrat und dessen Herstellungsverfahren
WO1997015946A1 (en) * 1995-10-26 1997-05-01 Philips Electronics N.V. Method of manufacturing a semiconductor device
JPH09331049A (ja) * 1996-04-08 1997-12-22 Canon Inc 貼り合わせｓｏｉ基板の作製方法及びｓｏｉ基板
FR2748851B1 (fr) 1996-05-15 1998-08-07 Commissariat Energie Atomique Procede de realisation d'une couche mince de materiau semiconducteur
US6013583A (en) * 1996-06-25 2000-01-11 International Business Machines Corporation Low temperature BPSG deposition process
KR100230984B1 (ko) * 1996-07-24 1999-11-15 김광호 반도체장치의 비피에스지에 포함된 불순물 측정시 이용되는 계측설비 설정값 보정용 기준 샘플 제조 방법
US7470142B2 (en) * 2004-06-21 2008-12-30 Sang-Yun Lee Wafer bonding method
SG55413A1 (en) * 1996-11-15 1998-12-21 Method Of Manufacturing Semico Method of manufacturing semiconductor article
US6054363A (en) * 1996-11-15 2000-04-25 Canon Kabushiki Kaisha Method of manufacturing semiconductor article
FR2758003B1 (fr) * 1996-12-27 1999-06-18 France Telecom Traitement anti-reflet de surfaces reflectives
CA2231625C (en) * 1997-03-17 2002-04-02 Canon Kabushiki Kaisha Semiconductor substrate having compound semiconductor layer, process for its production, and electronic device fabricated on semiconductor substrate
JP3985065B2 (ja) 1997-05-14 2007-10-03 忠弘 大見 多孔質シリコン基板の形成方法及び多孔質シリコン基板の形成装置
JP4473349B2 (ja) * 1997-06-30 2010-06-02 マクス−プランク−ゲゼルシャフト ツル フォルデルング デル ヴァイセンシャフト エー ファウ 層状構造体製造方法、及び半導体基板
EP0895282A3 (de) 1997-07-30 2000-01-26 Canon Kabushiki Kaisha Verfahren zur Herstellung eines SOI-Substrates mittels eines Bond-Verfahrens und dadurch hergestelltes SOI-Substrat
US6686623B2 (en) 1997-11-18 2004-02-03 Semiconductor Energy Laboratory Co., Ltd. Nonvolatile memory and electronic apparatus
FR2773261B1 (fr) 1997-12-30 2000-01-28 Commissariat Energie Atomique Procede pour le transfert d'un film mince comportant une etape de creation d'inclusions
JPH11195775A (ja) 1997-12-26 1999-07-21 Sony Corp 半導体基板および薄膜半導体素子およびそれらの製造方法ならびに陽極化成装置
JP3501642B2 (ja) 1997-12-26 2004-03-02 キヤノン株式会社 基板処理方法
US5939750A (en) * 1998-01-21 1999-08-17 Advanced Micro Devices Use of implanted ions to reduce oxide-nitride-oxide (ONO) etch residue and polystringers
SG71903A1 (en) * 1998-01-30 2000-04-18 Canon Kk Process of reclamation of soi substrate and reproduced substrate
JP4236722B2 (ja) * 1998-02-05 2009-03-11 株式会社半導体エネルギー研究所 半導体装置の作製方法
US6043120A (en) * 1998-03-03 2000-03-28 Advanced Micro Devices, Inc. Elimination of oxynitride (ONO) etch residue and polysilicon stringers through isolation of floating gates on adjacent bitlines by polysilicon oxidation
US6030868A (en) * 1998-03-03 2000-02-29 Advanced Micro Devices, Inc. Elimination of oxynitride (ONO) etch residue and polysilicon stringers through isolation of floating gates on adjacent bitlines by polysilicon oxidation
JPH11251207A (ja) * 1998-03-03 1999-09-17 Canon Inc Ｓｏｉ基板及びその製造方法並びにその製造設備
US6232232B1 (en) 1998-04-07 2001-05-15 Micron Technology, Inc. High selectivity BPSG to TEOS etchant
US6051451A (en) * 1998-04-21 2000-04-18 Advanced Micro Devices, Inc. Heavy ion implant process to eliminate polystringers in high density type flash memory devices
AU4593499A (en) * 1998-07-03 2000-01-24 Interuniversitair Micro-Elektronica Centrum A thin-film opto-electronic device and a method of making it
CN1495915A (zh) * 1998-07-03 2004-05-12 ������������ʽ���� 光电转换元件
TW444266B (en) * 1998-07-23 2001-07-01 Canon Kk Semiconductor substrate and method of producing same
JP2000277478A (ja) * 1999-03-25 2000-10-06 Canon Inc 陽極化成装置、陽極化成システム、基板の処理装置及び処理方法、並びに基板の製造方法
JP2000307112A (ja) * 1999-04-26 2000-11-02 Mitsubishi Electric Corp 半導体装置及びその製造方法
JP3900741B2 (ja) * 1999-05-21 2007-04-04 信越半導体株式会社 Ｓｏｉウェーハの製造方法
JP2000353797A (ja) * 1999-06-11 2000-12-19 Mitsubishi Electric Corp 半導体ウエハおよびその製造方法
JP3245136B2 (ja) * 1999-09-01 2002-01-07 キヤノン販売株式会社 絶縁膜の膜質改善方法
US6693033B2 (en) 2000-02-10 2004-02-17 Motorola, Inc. Method of removing an amorphous oxide from a monocrystalline surface
US6501973B1 (en) 2000-06-30 2002-12-31 Motorola, Inc. Apparatus and method for measuring selected physical condition of an animate subject
FR2811807B1 (fr) * 2000-07-12 2003-07-04 Commissariat Energie Atomique Procede de decoupage d'un bloc de materiau et de formation d'un film mince
US6555946B1 (en) 2000-07-24 2003-04-29 Motorola, Inc. Acoustic wave device and process for forming the same
US6590236B1 (en) 2000-07-24 2003-07-08 Motorola, Inc. Semiconductor structure for use with high-frequency signals
US6573126B2 (en) * 2000-08-16 2003-06-03 Massachusetts Institute Of Technology Process for producing semiconductor article using graded epitaxial growth
US6493497B1 (en) 2000-09-26 2002-12-10 Motorola, Inc. Electro-optic structure and process for fabricating same
US6638838B1 (en) 2000-10-02 2003-10-28 Motorola, Inc. Semiconductor structure including a partially annealed layer and method of forming the same
US6383924B1 (en) * 2000-12-13 2002-05-07 Micron Technology, Inc. Method of forming buried conductor patterns by surface transformation of empty spaces in solid state materials
US6673646B2 (en) 2001-02-28 2004-01-06 Motorola, Inc. Growth of compound semiconductor structures on patterned oxide films and process for fabricating same
WO2002082514A1 (en) * 2001-04-04 2002-10-17 Massachusetts Institute Of Technology A method for semiconductor device fabrication
FR2823599B1 (fr) 2001-04-13 2004-12-17 Commissariat Energie Atomique Substrat demomtable a tenue mecanique controlee et procede de realisation
FR2823596B1 (fr) * 2001-04-13 2004-08-20 Commissariat Energie Atomique Substrat ou structure demontable et procede de realisation
US6709989B2 (en) 2001-06-21 2004-03-23 Motorola, Inc. Method for fabricating a semiconductor structure including a metal oxide interface with silicon
US6646293B2 (en) 2001-07-18 2003-11-11 Motorola, Inc. Structure for fabricating high electron mobility transistors utilizing the formation of complaint substrates
US6693298B2 (en) 2001-07-20 2004-02-17 Motorola, Inc. Structure and method for fabricating epitaxial semiconductor on insulator (SOI) structures and devices utilizing the formation of a compliant substrate for materials used to form same
US6594414B2 (en) 2001-07-25 2003-07-15 Motorola, Inc. Structure and method of fabrication for an optical switch
US6585424B2 (en) 2001-07-25 2003-07-01 Motorola, Inc. Structure and method for fabricating an electro-rheological lens
US6667196B2 (en) 2001-07-25 2003-12-23 Motorola, Inc. Method for real-time monitoring and controlling perovskite oxide film growth and semiconductor structure formed using the method
US6589856B2 (en) 2001-08-06 2003-07-08 Motorola, Inc. Method and apparatus for controlling anti-phase domains in semiconductor structures and devices
US6639249B2 (en) 2001-08-06 2003-10-28 Motorola, Inc. Structure and method for fabrication for a solid-state lighting device
US6673667B2 (en) 2001-08-15 2004-01-06 Motorola, Inc. Method for manufacturing a substantially integral monolithic apparatus including a plurality of semiconductor materials
US6593213B2 (en) * 2001-09-20 2003-07-15 Heliovolt Corporation Synthesis of layers, coatings or films using electrostatic fields
US6787012B2 (en) * 2001-09-20 2004-09-07 Helio Volt Corp Apparatus for the synthesis of layers, coatings or films
US6881647B2 (en) * 2001-09-20 2005-04-19 Heliovolt Corporation Synthesis of layers, coatings or films using templates
US6559372B2 (en) * 2001-09-20 2003-05-06 Heliovolt Corporation Photovoltaic devices and compositions for use therein
US6500733B1 (en) 2001-09-20 2002-12-31 Heliovolt Corporation Synthesis of layers, coatings or films using precursor layer exerted pressure containment
US6736986B2 (en) 2001-09-20 2004-05-18 Heliovolt Corporation Chemical synthesis of layers, coatings or films using surfactants
KR20030032133A (ko) * 2001-10-10 2003-04-26 유종훈 비정질실리콘 박막층이 증착된 다공질실리콘 반도체의제조방법
FR2830983B1 (fr) * 2001-10-11 2004-05-14 Commissariat Energie Atomique Procede de fabrication de couches minces contenant des microcomposants
US20030134486A1 (en) * 2002-01-16 2003-07-17 Zhongze Wang Semiconductor-on-insulator comprising integrated circuitry
KR100476901B1 (ko) * 2002-05-22 2005-03-17 삼성전자주식회사 소이 반도체기판의 형성방법
US20030227057A1 (en) 2002-06-07 2003-12-11 Lochtefeld Anthony J. Strained-semiconductor-on-insulator device structures
US6995430B2 (en) * 2002-06-07 2006-02-07 Amberwave Systems Corporation Strained-semiconductor-on-insulator device structures
US7074623B2 (en) * 2002-06-07 2006-07-11 Amberwave Systems Corporation Methods of forming strained-semiconductor-on-insulator finFET device structures
TWI272641B (en) * 2002-07-16 2007-02-01 Semiconductor Energy Lab Method of manufacturing a semiconductor device
US7176108B2 (en) * 2002-11-07 2007-02-13 Soitec Silicon On Insulator Method of detaching a thin film at moderate temperature after co-implantation
FR2847075B1 (fr) * 2002-11-07 2005-02-18 Commissariat Energie Atomique Procede de formation d'une zone fragile dans un substrat par co-implantation
FR2848336B1 (fr) * 2002-12-09 2005-10-28 Commissariat Energie Atomique Procede de realisation d'une structure contrainte destinee a etre dissociee
US7501329B2 (en) 2003-05-21 2009-03-10 Micron Technology, Inc. Wafer gettering using relaxed silicon germanium epitaxial proximity layers
US7273788B2 (en) 2003-05-21 2007-09-25 Micron Technology, Inc. Ultra-thin semiconductors bonded on glass substrates
US7008854B2 (en) 2003-05-21 2006-03-07 Micron Technology, Inc. Silicon oxycarbide substrates for bonded silicon on insulator
US7662701B2 (en) * 2003-05-21 2010-02-16 Micron Technology, Inc. Gettering of silicon on insulator using relaxed silicon germanium epitaxial proximity layers
US6875656B2 (en) * 2003-05-22 2005-04-05 Texas Instruments Incorporated Method for improving silicon-on-insulator (SOI) film uniformity on a semiconductor wafer
FR2856844B1 (fr) * 2003-06-24 2006-02-17 Commissariat Energie Atomique Circuit integre sur puce de hautes performances
US7439158B2 (en) 2003-07-21 2008-10-21 Micron Technology, Inc. Strained semiconductor by full wafer bonding
FR2857953B1 (fr) 2003-07-21 2006-01-13 Commissariat Energie Atomique Structure empilee, et procede pour la fabriquer
US7153753B2 (en) 2003-08-05 2006-12-26 Micron Technology, Inc. Strained Si/SiGe/SOI islands and processes of making same
US7091108B2 (en) * 2003-09-11 2006-08-15 Intel Corporation Methods and apparatuses for manufacturing ultra thin device layers for integrated circuit devices
US20050082526A1 (en) * 2003-10-15 2005-04-21 International Business Machines Corporation Techniques for layer transfer processing
FR2861497B1 (fr) * 2003-10-28 2006-02-10 Soitec Silicon On Insulator Procede de transfert catastrophique d'une couche fine apres co-implantation
US7772087B2 (en) * 2003-12-19 2010-08-10 Commissariat A L'energie Atomique Method of catastrophic transfer of a thin film after co-implantation
KR100609367B1 (ko) * 2004-12-14 2006-08-08 한국전자통신연구원 Ｓｏｉ 기판의 제조방법
WO2006082469A1 (en) * 2005-02-03 2006-08-10 S.O.I.Tec Silicon On Insulator Technologies Method for applying a high temperature treatment to a semimiconductor wafer
US7244659B2 (en) * 2005-03-10 2007-07-17 Micron Technology, Inc. Integrated circuits and methods of forming a field effect transistor
FR2886051B1 (fr) 2005-05-20 2007-08-10 Commissariat Energie Atomique Procede de detachement d'un film mince
FR2889887B1 (fr) * 2005-08-16 2007-11-09 Commissariat Energie Atomique Procede de report d'une couche mince sur un support
DE102005042317B3 (de) * 2005-09-06 2007-04-12 Infineon Technologies Ag Verfahren zum Herstellen einer Schichtanordnung und Schichtanordnung
FR2891281B1 (fr) 2005-09-28 2007-12-28 Commissariat Energie Atomique Procede de fabrication d'un element en couches minces.
US7767904B2 (en) * 2006-01-12 2010-08-03 Heliovolt Corporation Compositions including controlled segregated phase domain structures
US20070160763A1 (en) * 2006-01-12 2007-07-12 Stanbery Billy J Methods of making controlled segregated phase domain structures
US8084685B2 (en) * 2006-01-12 2011-12-27 Heliovolt Corporation Apparatus for making controlled segregated phase domain structures
FR2899378B1 (fr) * 2006-03-29 2008-06-27 Commissariat Energie Atomique Procede de detachement d'un film mince par fusion de precipites
US7557002B2 (en) * 2006-08-18 2009-07-07 Micron Technology, Inc. Methods of forming transistor devices
FR2910179B1 (fr) * 2006-12-19 2009-03-13 Commissariat Energie Atomique PROCEDE DE FABRICATION DE COUCHES MINCES DE GaN PAR IMPLANTATION ET RECYCLAGE D'UN SUBSTRAT DE DEPART
US7989322B2 (en) * 2007-02-07 2011-08-02 Micron Technology, Inc. Methods of forming transistors
US20080277778A1 (en) * 2007-05-10 2008-11-13 Furman Bruce K Layer Transfer Process and Functionally Enhanced Integrated Circuits Products Thereby
US8034317B2 (en) * 2007-06-18 2011-10-11 Heliovolt Corporation Assemblies of anisotropic nanoparticles
FR2922359B1 (fr) * 2007-10-12 2009-12-18 Commissariat Energie Atomique Procede de fabrication d'une structure micro-electronique impliquant un collage moleculaire
FR2925221B1 (fr) * 2007-12-17 2010-02-19 Commissariat Energie Atomique Procede de transfert d'une couche mince
KR100980738B1 (ko) * 2008-10-10 2010-09-08 한국전자통신연구원 반도체 나노와이어 센서 소자의 제조 방법 및 이에 따라 제조된 반도체 나노와이어 센서 소자
AU2010211053A1 (en) * 2009-02-04 2010-08-12 Heliovolt Corporation Method of forming an indium-containing transparent conductive oxide film, metal targets used in the method and photovoltaic devices utilizing said films
KR20130122693A (ko) * 2009-06-05 2013-11-07 헬리오볼트 코오퍼레이션 비-접촉 압력 용기를 통해 박막 혹은 복합층을 합성하는 프로세스
FR2947098A1 (fr) * 2009-06-18 2010-12-24 Commissariat Energie Atomique Procede de transfert d'une couche mince sur un substrat cible ayant un coefficient de dilatation thermique different de celui de la couche mince
US8256621B2 (en) * 2009-09-11 2012-09-04 Pro-Pak Industries, Inc. Load tray and method for unitizing a palletized load
US20110180896A1 (en) * 2010-01-25 2011-07-28 International Business Machines Corporation Method of producing bonded wafer structure with buried oxide/nitride layers
US8021641B2 (en) * 2010-02-04 2011-09-20 Alliance For Sustainable Energy, Llc Methods of making copper selenium precursor compositions with a targeted copper selenide content and precursor compositions and thin films resulting therefrom
WO2011146115A1 (en) 2010-05-21 2011-11-24 Heliovolt Corporation Liquid precursor for deposition of copper selenide and method of preparing the same
US9142408B2 (en) 2010-08-16 2015-09-22 Alliance For Sustainable Energy, Llc Liquid precursor for deposition of indium selenide and method of preparing the same
US9105797B2 (en) 2012-05-31 2015-08-11 Alliance For Sustainable Energy, Llc Liquid precursor inks for deposition of In—Se, Ga—Se and In—Ga—Se
US10833175B2 (en) * 2015-06-04 2020-11-10 International Business Machines Corporation Formation of dislocation-free SiGe finFET using porous silicon
US11114333B2 (en) * 2018-02-22 2021-09-07 Micromaterials, LLC Method for depositing and reflow of a high quality etch resistant gapfill dielectric film
CN113571410B (zh) * 2021-07-19 2024-02-02 太原理工大学 一种低界面热阻金刚石基氮化镓晶片材料的制备方法
CN116525415B (zh) * 2023-06-09 2024-01-30 中电科先进材料技术创新有限公司 硅外延片的制备方法及硅外延片

Family Cites Families (22)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
NL7710164A (nl) * 1977-09-16 1979-03-20 Philips Nv Werkwijze ter behandeling van een eenkristal- lijn lichaam.
US4501060A (en) * 1983-01-24 1985-02-26 At&T Bell Laboratories Dielectrically isolated semiconductor devices
US4590130A (en) * 1984-03-26 1986-05-20 General Electric Company Solid state zone recrystallization of semiconductor material on an insulator
JPS61256713A (ja) * 1985-05-10 1986-11-14 Hitachi Ltd 結晶体構造およびその製造方法
JPS6384014A (ja) * 1986-09-27 1988-04-14 Agency Of Ind Science & Technol 半導体単結晶層の製造方法
US4915772A (en) * 1986-10-01 1990-04-10 Corning Incorporated Capping layer for recrystallization process
JPS63102244A (ja) * 1986-10-17 1988-05-07 Fujitsu Ltd 半導体基板の製造方法
NL8800953A (nl) * 1988-04-13 1989-11-01 Philips Nv Werkwijze voor het vervaardigen van een halfgeleiderlichaam.
US4891329A (en) * 1988-11-29 1990-01-02 University Of North Carolina Method of forming a nonsilicon semiconductor on insulator structure
US4990464A (en) * 1988-12-30 1991-02-05 North American Philips Corp. Method of forming improved encapsulation layer
US5013681A (en) * 1989-09-29 1991-05-07 The United States Of America As Represented By The Secretary Of The Navy Method of producing a thin silicon-on-insulator layer
JPH0719839B2 (ja) * 1989-10-18 1995-03-06 株式会社東芝 半導体基板の製造方法
JP3253099B2 (ja) * 1990-03-27 2002-02-04 キヤノン株式会社 半導体基板の作製方法
DE69133359T2 (de) * 1990-08-03 2004-12-16 Canon K.K. Verfahren zur Herstellung eines SOI-Substrats
JP3176072B2 (ja) * 1991-01-16 2001-06-11 キヤノン株式会社 半導体基板の形成方法
EP1347505A3 (de) * 1991-02-15 2004-10-20 Canon Kabushiki Kaisha Verfahren zur Vorbereitung einer Halbleitervorrichtung unter Verwendung der Ätzlösung
JPH04346418A (ja) * 1991-05-24 1992-12-02 Canon Inc 半導体基材の作製方法
JP3042728B2 (ja) * 1991-05-24 2000-05-22 日本電信電話株式会社 Ｘ線マスク及びｘ線露光方法
TW211621B (de) * 1991-07-31 1993-08-21 Canon Kk
JP3112106B2 (ja) * 1991-10-11 2000-11-27 キヤノン株式会社 半導体基材の作製方法
JP3416163B2 (ja) * 1992-01-31 2003-06-16 キヤノン株式会社 半導体基板及びその作製方法
JP3261685B2 (ja) * 1992-01-31 2002-03-04 キヤノン株式会社 半導体素子基体及びその作製方法

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EP0553857A3 (en) 1997-09-10
EP0553857A2 (de) 1993-08-04
EP0553857B1 (de) 2002-04-17
JP3416163B2 (ja) 2003-06-16
US5405802A (en) 1995-04-11
US5679475A (en) 1997-10-21
JPH05217992A (ja) 1993-08-27

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