DE69323628D1 - Chip-verbindung mit gasdurchlässiger ätzsperrschicht - Google Patents

Chip-verbindung mit gasdurchlässiger ätzsperrschicht

Info

Publication number
DE69323628D1
DE69323628D1 DE69323628T DE69323628T DE69323628D1 DE 69323628 D1 DE69323628 D1 DE 69323628D1 DE 69323628 T DE69323628 T DE 69323628T DE 69323628 T DE69323628 T DE 69323628T DE 69323628 D1 DE69323628 D1 DE 69323628D1
Authority
DE
Germany
Prior art keywords
gas
chip connection
etch layer
permeable
permeable etch
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE69323628T
Other languages
English (en)
Other versions
DE69323628T2 (de
Inventor
Stephen E Greco
Kris Srikrishnan
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
International Business Machines Corp
Original Assignee
International Business Machines Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by International Business Machines Corp filed Critical International Business Machines Corp
Publication of DE69323628D1 publication Critical patent/DE69323628D1/de
Application granted granted Critical
Publication of DE69323628T2 publication Critical patent/DE69323628T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/29—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the material, e.g. carbon
    • H01L23/293—Organic, e.g. plastic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76822—Modification of the material of dielectric layers, e.g. grading, after-treatment to improve the stability of the layers, to increase their density etc.
    • H01L21/76826—Modification of the material of dielectric layers, e.g. grading, after-treatment to improve the stability of the layers, to increase their density etc. by contacting the layer with gases, liquids or plasmas
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
    • H01L23/5329—Insulating materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00—Metal treatment
    • Y10S148/043—Dual dielectric
DE69323628T 1992-10-30 1993-04-29 Chip-verbindung mit gasdurchlässiger ätzsperrschicht Expired - Fee Related DE69323628T2 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US07/968,789 US5371047A (en) 1992-10-30 1992-10-30 Chip interconnection having a breathable etch stop layer
PCT/US1993/004043 WO1994010703A1 (en) 1992-10-30 1993-04-29 Chip interconnection having a breathable etch stop layer

Publications (2)

Publication Number Publication Date
DE69323628D1 true DE69323628D1 (de) 1999-04-01
DE69323628T2 DE69323628T2 (de) 1999-09-30

Family

ID=25514780

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69323628T Expired - Fee Related DE69323628T2 (de) 1992-10-30 1993-04-29 Chip-verbindung mit gasdurchlässiger ätzsperrschicht

Country Status (5)

Country Link
US (1) US5371047A (de)
EP (1) EP0667036B1 (de)
JP (1) JP2661652B2 (de)
DE (1) DE69323628T2 (de)
WO (1) WO1994010703A1 (de)

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US5451543A (en) * 1994-04-25 1995-09-19 Motorola, Inc. Straight sidewall profile contact opening to underlying interconnect and method for making the same
US5565384A (en) * 1994-04-28 1996-10-15 Texas Instruments Inc Self-aligned via using low permittivity dielectric
US5482894A (en) * 1994-08-23 1996-01-09 Texas Instruments Incorporated Method of fabricating a self-aligned contact using organic dielectric materials
US5710460A (en) * 1995-04-21 1998-01-20 International Business Machines Corporation Structure for reducing microelectronic short circuits using spin-on glass as part of the interlayer dielectric
JPH08306780A (ja) * 1995-05-11 1996-11-22 Toshiba Corp 半導体装置の製造方法
US5614765A (en) * 1995-06-07 1997-03-25 Advanced Micro Devices, Inc. Self aligned via dual damascene
US5705430A (en) * 1995-06-07 1998-01-06 Advanced Micro Devices, Inc. Dual damascene with a sacrificial via fill
US5691238A (en) * 1995-06-07 1997-11-25 Advanced Micro Devices, Inc. Subtractive dual damascene
US5686354A (en) * 1995-06-07 1997-11-11 Advanced Micro Devices, Inc. Dual damascene with a protective mask for via etching
US5834845A (en) * 1995-09-21 1998-11-10 Advanced Micro Devices, Inc. Interconnect scheme for integrated circuits
US5854131A (en) * 1996-06-05 1998-12-29 Advanced Micro Devices, Inc. Integrated circuit having horizontally and vertically offset interconnect lines
US6143647A (en) * 1997-07-24 2000-11-07 Intel Corporation Silicon-rich block copolymers to achieve unbalanced vias
US6309971B1 (en) 1996-08-01 2001-10-30 Cypress Semiconductor Corporation Hot metallization process
JP3305211B2 (ja) * 1996-09-10 2002-07-22 松下電器産業株式会社 半導体装置及びその製造方法
US5773360A (en) * 1996-10-18 1998-06-30 Taiwan Semiconductor Manufacturing Company, Ltd. Reduction of surface contamination in post-CMP cleaning
US5962113A (en) * 1996-10-28 1999-10-05 International Business Machines Corporation Integrated circuit device and process for its manufacture
US5977638A (en) * 1996-11-21 1999-11-02 Cypress Semiconductor Corp. Edge metal for interconnect layers
US5818110A (en) * 1996-11-22 1998-10-06 International Business Machines Corporation Integrated circuit chip wiring structure with crossover capability and method of manufacturing the same
US5861676A (en) * 1996-11-27 1999-01-19 Cypress Semiconductor Corp. Method of forming robust interconnect and contact structures in a semiconductor and/or integrated circuit
US5897371A (en) * 1996-12-19 1999-04-27 Cypress Semiconductor Corp. Alignment process compatible with chemical mechanical polishing
US5981374A (en) * 1997-04-29 1999-11-09 International Business Machines Corporation Sub-half-micron multi-level interconnection structure and process thereof
US6420273B1 (en) 1997-06-30 2002-07-16 Koninklijke Philips Electronics N.V. Self-aligned etch-stop layer formation for semiconductor devices
US6080655A (en) 1997-08-21 2000-06-27 Micron Technology, Inc. Method for fabricating conductive components in microelectronic devices and substrate structures thereof
US6150072A (en) * 1997-08-22 2000-11-21 Siemens Microelectronics, Inc. Method of manufacturing a shallow trench isolation structure for a semiconductor device
US6218078B1 (en) * 1997-09-24 2001-04-17 Advanced Micro Devices, Inc. Creation of an etch hardmask by spin-on technique
US6127721A (en) * 1997-09-30 2000-10-03 Siemens Aktiengesellschaft Soft passivation layer in semiconductor fabrication
FR2779274B1 (fr) * 1998-05-27 2000-08-18 St Microelectronics Sa Circuit integre avec couche d'arret et procede de fabrication associe
US6025259A (en) * 1998-07-02 2000-02-15 Advanced Micro Devices, Inc. Dual damascene process using high selectivity boundary layers
US6174803B1 (en) 1998-09-16 2001-01-16 Vsli Technology Integrated circuit device interconnection techniques
US6150272A (en) * 1998-11-16 2000-11-21 Taiwan Semiconductor Manufacturing Company Method for making metal plug contacts and metal lines in an insulating layer by chemical/mechanical polishing that reduces polishing-induced damage
US6965165B2 (en) 1998-12-21 2005-11-15 Mou-Shiung Lin Top layers of metal for high performance IC's
JP2000260768A (ja) * 1999-03-05 2000-09-22 Nec Corp 半導体装置の製造方法
US6171949B1 (en) * 1999-06-09 2001-01-09 Advanced Micro Devices, Inc. Low energy passivation of conductive material in damascene process for semiconductors
US6265319B1 (en) * 1999-09-01 2001-07-24 Taiwan Semiconductor Manufacturing Company Dual damascene method employing spin-on polymer (SOP) etch stop layer
US6114243A (en) * 1999-11-15 2000-09-05 Chartered Semiconductor Manufacturing Ltd Method to avoid copper contamination on the sidewall of a via or a dual damascene structure
JP5042427B2 (ja) * 2000-05-08 2012-10-03 電気化学工業株式会社 低比誘電率ＳｉＯｘ膜の製造方法
US6399512B1 (en) 2000-06-15 2002-06-04 Cypress Semiconductor Corporation Method of making metallization and contact structures in an integrated circuit comprising an etch stop layer
US6635566B1 (en) * 2000-06-15 2003-10-21 Cypress Semiconductor Corporation Method of making metallization and contact structures in an integrated circuit
US6379870B1 (en) 2000-07-12 2002-04-30 Honeywell International Inc. Method for determining side wall oxidation of low-k materials
US6603204B2 (en) * 2001-02-28 2003-08-05 International Business Machines Corporation Low-k interconnect structure comprised of a multilayer of spin-on porous dielectrics
US6667217B1 (en) * 2001-03-01 2003-12-23 Taiwan Semiconductor Manufacturing Company Method of fabricating a damascene copper inductor structure using a sub-0.18 um CMOS process
US6798073B2 (en) * 2001-12-13 2004-09-28 Megic Corporation Chip structure and process for forming the same
US9419075B1 (en) * 2015-01-28 2016-08-16 Texas Instruments Incorporated Wafer substrate removal
US10199461B2 (en) * 2015-10-27 2019-02-05 Texas Instruments Incorporated Isolation of circuit elements using front side deep trench etch

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JPS5615052A (en) * 1979-07-18 1981-02-13 Hitachi Ltd Semiconductor device with multilayer wiring
JPS5834945A (ja) * 1981-08-26 1983-03-01 Nippon Telegr & Teleph Corp <Ntt> 多層配線構造体
FR2526225B1 (fr) * 1982-04-30 1985-11-08 Radiotechnique Compelec Procede de realisation d'un condensateur integre, et dispositif ainsi obtenu
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JPS62194644A (ja) * 1986-02-20 1987-08-27 Mitsubishi Electric Corp 半導体装置およびその製造方法
JPH0654774B2 (ja) * 1987-11-30 1994-07-20 株式会社東芝 半導体装置及びその製造方法
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Also Published As

Publication number Publication date
JP2661652B2 (ja) 1997-10-08
US5371047A (en) 1994-12-06
EP0667036B1 (de) 1999-02-24
JPH08501904A (ja) 1996-02-27
WO1994010703A1 (en) 1994-05-11
DE69323628T2 (de) 1999-09-30
EP0667036A1 (de) 1995-08-16

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee