DE69315929D1 - Leitfähige Diffusionsbarriere - Google Patents

Leitfähige Diffusionsbarriere

Info

Publication number
DE69315929D1
DE69315929D1 DE69315929T DE69315929T DE69315929D1 DE 69315929 D1 DE69315929 D1 DE 69315929D1 DE 69315929 T DE69315929 T DE 69315929T DE 69315929 T DE69315929 T DE 69315929T DE 69315929 D1 DE69315929 D1 DE 69315929D1
Authority
DE
Germany
Prior art keywords
diffusion barrier
conductive diffusion
conductive
barrier
diffusion
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE69315929T
Other languages
English (en)
Other versions
DE69315929T2 (de
Inventor
Israel A Lesk
Francine Y Robb
Lewis E Terry
D Aragona Frank Secco
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Motorola Solutions Inc
Original Assignee
Motorola Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Motorola Inc filed Critical Motorola Inc
Publication of DE69315929D1 publication Critical patent/DE69315929D1/de
Application granted granted Critical
Publication of DE69315929T2 publication Critical patent/DE69315929T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/45—Ohmic electrodes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/45—Ohmic electrodes
    • H01L29/452—Ohmic electrodes on AIII-BV compounds
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00—Metal treatment
    • Y10S148/012—Bonding, e.g. electrostatic for strain gauges
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S257/00—Active solid-state devices, e.g. transistors, solid-state diodes
    • Y10S257/915—Active solid-state devices, e.g. transistors, solid-state diodes with titanium nitride portion or region
DE69315929T 1992-08-14 1993-06-01 Leitfähige Diffusionsbarriere Expired - Fee Related DE69315929T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US07/929,232 US5369304A (en) 1992-08-14 1992-08-14 Conductive diffusion barrier of titanium nitride in ohmic contact with a plurality of doped layers therefor

Publications (2)

Publication Number Publication Date
DE69315929D1 true DE69315929D1 (de) 1998-02-05
DE69315929T2 DE69315929T2 (de) 1998-06-18

Family

ID=25457524

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69315929T Expired - Fee Related DE69315929T2 (de) 1992-08-14 1993-06-01 Leitfähige Diffusionsbarriere

Country Status (4)

Country Link
US (2) US5369304A (de)
EP (1) EP0587996B1 (de)
JP (1) JPH06112148A (de)
DE (1) DE69315929T2 (de)

Families Citing this family (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5413952A (en) * 1994-02-02 1995-05-09 Motorola, Inc. Direct wafer bonded structure method of making
US5643821A (en) * 1994-11-09 1997-07-01 Harris Corporation Method for making ohmic contact to lightly doped islands from a silicide buried layer and applications
US5550079A (en) * 1995-06-15 1996-08-27 Top Team/Microelectronics Corp. Method for fabricating silicide shunt of dual-gate CMOS device
FR2798224B1 (fr) * 1999-09-08 2003-08-29 Commissariat Energie Atomique Realisation d'un collage electriquement conducteur entre deux elements semi-conducteurs.
US8314002B2 (en) * 2000-05-05 2012-11-20 International Rectifier Corporation Semiconductor device having increased switching speed
FR2845522A1 (fr) * 2002-10-03 2004-04-09 St Microelectronics Sa Circuit integre a couche enterree fortement conductrice
KR100755410B1 (ko) * 2006-09-22 2007-09-04 삼성전자주식회사 게이트 구조물 및 이를 형성하는 방법, 비휘발성 메모리장치 및 이의 제조 방법
US9406690B2 (en) 2014-12-16 2016-08-02 Sandisk Technologies Llc Contact for vertical memory with dopant diffusion stopper and associated fabrication method

Family Cites Families (19)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS59175763A (ja) * 1983-03-25 1984-10-04 Fujitsu Ltd 半導体装置
US4829363A (en) * 1984-04-13 1989-05-09 Fairchild Camera And Instrument Corp. Structure for inhibiting dopant out-diffusion
US4640004A (en) * 1984-04-13 1987-02-03 Fairchild Camera & Instrument Corp. Method and structure for inhibiting dopant out-diffusion
US4599792A (en) * 1984-06-15 1986-07-15 International Business Machines Corporation Buried field shield for an integrated circuit
US4920071A (en) * 1985-03-15 1990-04-24 Fairchild Camera And Instrument Corporation High temperature interconnect system for an integrated circuit
JPH07122981B2 (ja) * 1985-09-03 1995-12-25 ソニー株式会社 カセツトテ−プレコ−ダ
US4727045A (en) * 1986-07-30 1988-02-23 Advanced Micro Devices, Inc. Plugged poly silicon resistor load for static random access memory cells
US4884123A (en) * 1987-02-19 1989-11-28 Advanced Micro Devices, Inc. Contact plug and interconnect employing a barrier lining and a backfilled conductor material
US4902640A (en) * 1987-04-17 1990-02-20 Tektronix, Inc. High speed double polycide bipolar/CMOS integrated circuit process
US4771016A (en) * 1987-04-24 1988-09-13 Harris Corporation Using a rapid thermal process for manufacturing a wafer bonded soi semiconductor
JP2685819B2 (ja) * 1988-03-31 1997-12-03 株式会社東芝 誘電体分離半導体基板とその製造方法
US5004705A (en) * 1989-01-06 1991-04-02 Unitrode Corporation Inverted epitaxial process
JPH02186626A (ja) * 1989-01-13 1990-07-20 Nec Corp 半導体集積回路の製造方法
US5102821A (en) * 1990-12-20 1992-04-07 Texas Instruments Incorporated SOI/semiconductor heterostructure fabrication by wafer bonding of polysilicon to titanium
US5098861A (en) * 1991-01-08 1992-03-24 Unitrode Corporation Method of processing a semiconductor substrate including silicide bonding
US5231052A (en) * 1991-02-14 1993-07-27 Industrial Technology Research Institute Process for forming a multilayer polysilicon semiconductor electrode
US5183769A (en) * 1991-05-06 1993-02-02 Motorola, Inc. Vertical current flow semiconductor device utilizing wafer bonding
US5260233A (en) * 1992-11-06 1993-11-09 International Business Machines Corporation Semiconductor device and wafer structure having a planar buried interconnect by wafer bonding
US5413952A (en) * 1994-02-02 1995-05-09 Motorola, Inc. Direct wafer bonded structure method of making

Also Published As

Publication number Publication date
US5369304A (en) 1994-11-29
EP0587996A3 (de) 1994-11-09
EP0587996A2 (de) 1994-03-23
EP0587996B1 (de) 1997-12-29
US5567649A (en) 1996-10-22
DE69315929T2 (de) 1998-06-18
JPH06112148A (ja) 1994-04-22

Similar Documents

Publication Publication Date Title
DE69314458T2 (de) Barriereüberzug
DE69311442D1 (de) Kontaktanordnung
NO180184C (no) Varmeisolasjonselement
DE69320500T2 (de) Steckverbinder
DE69302777T2 (de) Feuerabschlussvorrichtung
DE69317374D1 (de) Steckverbinderaufbau
DE59302805D1 (de) Mehrpolige Anschlussklemme
DE69333218D1 (de) Referenzelektrode
DE69315929D1 (de) Leitfähige Diffusionsbarriere
DE69303217T2 (de) Steckverbinder
DE59306773D1 (de) Erdungskontakt
DE59403725D1 (de) Stützisolator
DE69314915T2 (de) Steckverbinderaufbau
DE9316832U1 (de) Leiterverbindung
AT399962B (de) Drilleiter
DE9205659U1 (de) Steckverbinder
DE9205545U1 (de) Steckverbinder
DE59302341D1 (de) Leiterbahnen-Verbindung
IT228366Y1 (it) Barriera mobile
DE59307891D1 (de) Steckverbinder
DE9400198U1 (de) Absperrschranke
NO930476L (no) Avstandselementer
SE9303225D0 (sv) Barriärelement
LT2061B (lt) Elektrostatinis levitatorius
DE9317900U1 (de) Absperrschranke

Legal Events

Date Code Title Description
8320 Willingness to grant licences declared (paragraph 23)
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee