DE69231957T2 - Hochgeschwindigkeitsprozessor zum fähiger Abhandeln mehrerer Unterbrechungen - Google Patents

Hochgeschwindigkeitsprozessor zum fähiger Abhandeln mehrerer Unterbrechungen

Info

Publication number
DE69231957T2
DE69231957T2 DE69231957T DE69231957T DE69231957T2 DE 69231957 T2 DE69231957 T2 DE 69231957T2 DE 69231957 T DE69231957 T DE 69231957T DE 69231957 T DE69231957 T DE 69231957T DE 69231957 T2 DE69231957 T2 DE 69231957T2
Authority
DE
Germany
Prior art keywords
high speed
processor capable
speed processor
handling multiple
multiple interruptions
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE69231957T
Other languages
English (en)
Other versions
DE69231957D1 (de
Inventor
Nobuhiro Takiguchi
Soichi Kawasaki
Yasuo Yamada
Akira Kanuma
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp filed Critical Toshiba Corp
Publication of DE69231957D1 publication Critical patent/DE69231957D1/de
Application granted granted Critical
Publication of DE69231957T2 publication Critical patent/DE69231957T2/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/46—Multiprogramming arrangements
    • G06F9/461—Saving or restoring of program or task context
    • G06F9/462—Saving or restoring of program or task context with multiple register sets
DE69231957T 1991-10-21 1992-10-21 Hochgeschwindigkeitsprozessor zum fähiger Abhandeln mehrerer Unterbrechungen Expired - Lifetime DE69231957T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP27275091 1991-10-21

Publications (2)

Publication Number Publication Date
DE69231957D1 DE69231957D1 (de) 2001-08-30
DE69231957T2 true DE69231957T2 (de) 2002-04-04

Family

ID=17518238

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69231957T Expired - Lifetime DE69231957T2 (de) 1991-10-21 1992-10-21 Hochgeschwindigkeitsprozessor zum fähiger Abhandeln mehrerer Unterbrechungen

Country Status (4)

Country Link
US (1) US5557766A (de)
EP (1) EP0538817B1 (de)
KR (1) KR970008523B1 (de)
DE (1) DE69231957T2 (de)

Families Citing this family (59)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH07114498A (ja) * 1993-10-15 1995-05-02 Toshiba Corp マイクロプロセッサ
JP2677202B2 (ja) * 1994-08-12 1997-11-17 日本電気株式会社 マイクロプロセッサ
JPH08305585A (ja) * 1995-05-11 1996-11-22 Matsushita Electric Ind Co Ltd 割込制御装置
US5944816A (en) * 1996-05-17 1999-08-31 Advanced Micro Devices, Inc. Microprocessor configured to execute multiple threads including interrupt service routines
US5987601A (en) * 1997-02-14 1999-11-16 Xyron Corporation Zero overhead computer interrupts with task switching
KR100263908B1 (ko) * 1997-07-23 2000-08-16 윤종용 디지탈 다기능 디스크 롬 시스템의 데이타 처리장치 및 방법
US5913049A (en) * 1997-07-31 1999-06-15 Texas Instruments Incorporated Multi-stream complex instruction set microprocessor
US6154832A (en) * 1998-12-04 2000-11-28 Advanced Micro Devices, Inc. Processor employing multiple register sets to eliminate interrupts
US6668317B1 (en) 1999-08-31 2003-12-23 Intel Corporation Microengine for parallel processor architecture
US6427196B1 (en) 1999-08-31 2002-07-30 Intel Corporation SRAM controller for parallel processor architecture including address and command queue and arbiter
US6983350B1 (en) 1999-08-31 2006-01-03 Intel Corporation SDRAM controller for parallel processor architecture
AU7099000A (en) 1999-09-01 2001-03-26 Intel Corporation Branch instruction for processor
US7191309B1 (en) 1999-09-01 2007-03-13 Intel Corporation Double shift instruction for micro engine used in multithreaded parallel processor architecture
WO2001016702A1 (en) 1999-09-01 2001-03-08 Intel Corporation Register set used in multithreaded parallel processor architecture
US6532509B1 (en) 1999-12-22 2003-03-11 Intel Corporation Arbitrating command requests in a parallel multi-threaded processing system
US6694380B1 (en) 1999-12-27 2004-02-17 Intel Corporation Mapping requests from a processing unit that uses memory-mapped input-output space
US6631430B1 (en) 1999-12-28 2003-10-07 Intel Corporation Optimizations to receive packet status from fifo bus
US6625654B1 (en) 1999-12-28 2003-09-23 Intel Corporation Thread signaling in multi-threaded network processor
US6307789B1 (en) 1999-12-28 2001-10-23 Intel Corporation Scratchpad memory
US7620702B1 (en) 1999-12-28 2009-11-17 Intel Corporation Providing real-time control data for a network processor
US6661794B1 (en) 1999-12-29 2003-12-09 Intel Corporation Method and apparatus for gigabit packet assignment for multithreaded packet processing
US6952824B1 (en) 1999-12-30 2005-10-04 Intel Corporation Multi-threaded sequenced receive for fast network port stream of packets
US7480706B1 (en) 1999-12-30 2009-01-20 Intel Corporation Multi-threaded round-robin receive for fast network port
US6584522B1 (en) 1999-12-30 2003-06-24 Intel Corporation Communication between processors
US6976095B1 (en) 1999-12-30 2005-12-13 Intel Corporation Port blocking technique for maintaining receive packet ordering for a multiple ethernet port switch
EP1122643A1 (de) * 2000-02-07 2001-08-08 Siemens Aktiengesellschaft Schaltungsanordnung und Verfahren zur Hardware-Interruptbehandlung
US7681018B2 (en) * 2000-08-31 2010-03-16 Intel Corporation Method and apparatus for providing large register address space while maximizing cycletime performance for a multi-threaded register file set
US20020053017A1 (en) * 2000-09-01 2002-05-02 Adiletta Matthew J. Register instructions for a multithreaded processor
JP2002189603A (ja) * 2000-12-19 2002-07-05 Fujitsu Ltd 計算機とその制御方法
US7020871B2 (en) * 2000-12-21 2006-03-28 Intel Corporation Breakpoint method for parallel hardware threads in multithreaded processor
JP3699003B2 (ja) * 2001-04-18 2005-09-28 Ｎｅｃマイクロシステム株式会社 データ処理装置および方法
US6603683B2 (en) * 2001-06-25 2003-08-05 International Business Machines Corporation Decoding scheme for a stacked bank architecture
US6868476B2 (en) 2001-08-27 2005-03-15 Intel Corporation Software controlled content addressable memory in a general purpose execution datapath
US7216204B2 (en) 2001-08-27 2007-05-08 Intel Corporation Mechanism for providing early coherency detection to enable high performance memory updates in a latency sensitive multithreaded environment
US7225281B2 (en) 2001-08-27 2007-05-29 Intel Corporation Multiprocessor infrastructure for providing flexible bandwidth allocation via multiple instantiations of separate data buses, control buses and support mechanisms
US7487505B2 (en) 2001-08-27 2009-02-03 Intel Corporation Multithreaded microprocessor with register allocation based on number of active threads
US7126952B2 (en) 2001-09-28 2006-10-24 Intel Corporation Multiprotocol decapsulation/encapsulation control structure and packet protocol conversion method
US7158964B2 (en) * 2001-12-12 2007-01-02 Intel Corporation Queue management
US7107413B2 (en) * 2001-12-17 2006-09-12 Intel Corporation Write queue descriptor count instruction for high speed queuing
US7269179B2 (en) * 2001-12-18 2007-09-11 Intel Corporation Control mechanisms for enqueue and dequeue operations in a pipelined network processor
US7895239B2 (en) * 2002-01-04 2011-02-22 Intel Corporation Queue arrays in network devices
US7181573B2 (en) * 2002-01-07 2007-02-20 Intel Corporation Queue array caching in network devices
US6934951B2 (en) 2002-01-17 2005-08-23 Intel Corporation Parallel processor with functional pipeline providing programming engines by supporting multiple contexts and critical section
US7610451B2 (en) 2002-01-25 2009-10-27 Intel Corporation Data transfer mechanism using unidirectional pull bus and push bus
US7181594B2 (en) * 2002-01-25 2007-02-20 Intel Corporation Context pipelines
US7149226B2 (en) * 2002-02-01 2006-12-12 Intel Corporation Processing data packets
US7437724B2 (en) * 2002-04-03 2008-10-14 Intel Corporation Registers for data transfers
US7471688B2 (en) 2002-06-18 2008-12-30 Intel Corporation Scheduling system for transmission of cells to ATM virtual circuits and DSL ports
US7337275B2 (en) 2002-08-13 2008-02-26 Intel Corporation Free list and ring data structure management
US7352769B2 (en) 2002-09-12 2008-04-01 Intel Corporation Multiple calendar schedule reservation structure and method
US7433307B2 (en) 2002-11-05 2008-10-07 Intel Corporation Flow control in a network environment
US6941438B2 (en) 2003-01-10 2005-09-06 Intel Corporation Memory interleaving
TWI222597B (en) * 2003-03-14 2004-10-21 Mediatek Inc Method for accessing external memory of a microprocessor
US7443836B2 (en) 2003-06-16 2008-10-28 Intel Corporation Processing a data packet
US7213099B2 (en) 2003-12-30 2007-05-01 Intel Corporation Method and apparatus utilizing non-uniformly distributed DRAM configurations and to detect in-range memory address matches
US9652241B2 (en) * 2007-04-10 2017-05-16 Cambridge Consultants Ltd. Data processing apparatus with instruction encodings to enable near and far memory access modes
GB2461848B (en) * 2008-07-10 2013-01-30 Cambridge Consultants Data processing apparatus having a number of operating modes
WO2010004242A2 (en) 2008-07-10 2010-01-14 Cambridge Consultants Limited Data processing apparatus, for example using vector pointers
US8825926B2 (en) * 2009-04-13 2014-09-02 Microchip Technology Incorporated Processor with assignable general purpose register set

Family Cites Families (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4091447A (en) * 1976-07-19 1978-05-23 Union Carbide Corporation Interrupt control system for a microcomputer
US4217638A (en) * 1977-05-19 1980-08-12 Tokyo Shibaura Electric Co., Ltd. Data-processing apparatus and method
US4250546A (en) * 1978-07-31 1981-02-10 Motorola, Inc. Fast interrupt method
JPS5757345A (en) * 1980-09-24 1982-04-06 Toshiba Corp Data controller
JPS6140650A (ja) * 1984-08-02 1986-02-26 Nec Corp マイクロコンピユ−タ
JPS61262922A (ja) * 1985-05-17 1986-11-20 Fujitsu Ltd レジスタデ−タの高速スタツク回路
JPS6290728A (ja) * 1985-06-27 1987-04-25 Nec Corp 割込処理方法
JP2545789B2 (ja) * 1986-04-14 1996-10-23 株式会社日立製作所 情報処理装置
US5050067A (en) * 1987-08-20 1991-09-17 Davin Computer Corporation Multiple sliding register stacks in a computer
US5146581A (en) * 1988-02-24 1992-09-08 Sanyo Electric Co., Ltd. Subprogram executing data processing system having bank switching control storing in the same address area in each of memory banks
JPH0795277B2 (ja) * 1988-11-25 1995-10-11 日本電気株式会社 データ処理装置
JPH02183342A (ja) * 1989-01-10 1990-07-17 Fuji Electric Co Ltd 割込み制御装置
JPH0711793B2 (ja) * 1989-07-13 1995-02-08 株式会社東芝 マイクロプロセッサ

Also Published As

Publication number Publication date
US5557766A (en) 1996-09-17
EP0538817B1 (de) 2001-07-25
DE69231957D1 (de) 2001-08-30
EP0538817A3 (en) 1993-08-18
KR970008523B1 (ko) 1997-05-24
EP0538817A2 (de) 1993-04-28

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition