DE69231762D1 - Risc-prozessor mit dehnbarer architektur - Google Patents

Risc-prozessor mit dehnbarer architektur

Info

Publication number
DE69231762D1
DE69231762D1 DE69231762T DE69231762T DE69231762D1 DE 69231762 D1 DE69231762 D1 DE 69231762D1 DE 69231762 T DE69231762 T DE 69231762T DE 69231762 T DE69231762 T DE 69231762T DE 69231762 D1 DE69231762 D1 DE 69231762D1
Authority
DE
Germany
Prior art keywords
instruction
execution
functional units
instructions
unit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE69231762T
Other languages
English (en)
Other versions
DE69231762T2 (de
Inventor
Le Trong Nguyen
Derek J Lentz
Yoshiyuki Miyayama
Sanjiv Garg
Yasuaki Hagiwara
Johannes Wang
Tei-Li Lau
Quang H Trang
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Seiko Epson Corp
Original Assignee
Seiko Epson Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Seiko Epson Corp filed Critical Seiko Epson Corp
Application granted granted Critical
Publication of DE69231762D1 publication Critical patent/DE69231762D1/de
Publication of DE69231762T2 publication Critical patent/DE69231762T2/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

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    • G06F9/06Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30Arrangements for executing machine instructions, e.g. instruction decode
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    • G06F9/30Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30145Instruction analysis, e.g. decoding, instruction word fields
    • G06F9/3016Decoding the operand specifier, e.g. specifier format
    • G06F9/30167Decoding the operand specifier, e.g. specifier format of immediate specifier, e.g. constants
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    • G06F9/38Concurrent instruction execution, e.g. pipeline, look ahead
    • G06F9/3824Operand accessing
    • G06F9/3826Bypassing or forwarding of data results, e.g. locally between pipeline stages or within a pipeline stage
    • G06F9/3828Bypassing or forwarding of data results, e.g. locally between pipeline stages or within a pipeline stage with global bypass, e.g. between pipelines, between clusters
    • GPHYSICS
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    • G06F9/384Register renaming
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    • G06F9/30Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38Concurrent instruction execution, e.g. pipeline, look ahead
    • G06F9/3836Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution
    • G06F9/3853Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution of compound instructions
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    • G06F9/30Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38Concurrent instruction execution, e.g. pipeline, look ahead
    • G06F9/3854Instruction completion, e.g. retiring, committing or graduating
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    • G06F9/3861Recovery, e.g. branch miss-prediction, exception handling
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    • G06F9/30Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38Concurrent instruction execution, e.g. pipeline, look ahead
    • G06F9/3861Recovery, e.g. branch miss-prediction, exception handling
    • G06F9/3865Recovery, e.g. branch miss-prediction, exception handling using deferred exception handling, e.g. exception flags
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    • G06F9/00Arrangements for program control, e.g. control units
    • G06F9/06Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38Concurrent instruction execution, e.g. pipeline, look ahead
    • G06F9/3885Concurrent instruction execution, e.g. pipeline, look ahead using a plurality of independent parallel functional units
DE69231762T 1991-07-08 1992-07-07 Risc-prozessor mit dehnbarer architektur Expired - Lifetime DE69231762T2 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US72705891A 1991-07-08 1991-07-08
PCT/JP1992/000871 WO1993001546A1 (en) 1991-07-08 1992-07-07 Extensible risc microprocessor architecture

Publications (2)

Publication Number Publication Date
DE69231762D1 true DE69231762D1 (de) 2001-05-10
DE69231762T2 DE69231762T2 (de) 2001-07-26

Family

ID=24921163

Family Applications (2)

Application Number Title Priority Date Filing Date
DE69233493T Expired - Lifetime DE69233493T2 (de) 1991-07-08 1992-07-07 RISC-Prozessor mit erweiterbarer Architektur
DE69231762T Expired - Lifetime DE69231762T2 (de) 1991-07-08 1992-07-07 Risc-prozessor mit dehnbarer architektur

Family Applications Before (1)

Application Number Title Priority Date Filing Date
DE69233493T Expired - Lifetime DE69233493T2 (de) 1991-07-08 1992-07-07 RISC-Prozessor mit erweiterbarer Architektur

Country Status (8)

Country Link
US (7) US5560032A (de)
EP (3) EP0886209B1 (de)
JP (16) JP3441071B2 (de)
KR (2) KR100299691B1 (de)
AT (2) ATE291755T1 (de)
DE (2) DE69233493T2 (de)
HK (2) HK1014784A1 (de)
WO (1) WO1993001546A1 (de)

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JP2005327309A (ja) 2005-11-24
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