DE69228044D1 - Verfahren zur Strukturierung von Wolframschichten - Google Patents

Verfahren zur Strukturierung von Wolframschichten

Info

Publication number
DE69228044D1
DE69228044D1 DE69228044T DE69228044T DE69228044D1 DE 69228044 D1 DE69228044 D1 DE 69228044D1 DE 69228044 T DE69228044 T DE 69228044T DE 69228044 T DE69228044 T DE 69228044T DE 69228044 D1 DE69228044 D1 DE 69228044D1
Authority
DE
Germany
Prior art keywords
structuring
tungsten layers
tungsten
layers
structuring tungsten
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE69228044T
Other languages
English (en)
Other versions
DE69228044T2 (de
Inventor
Thomas Robert Fullowan
Stephen John Pearton
Fan Ren
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
AT&T Corp
Original Assignee
AT&T Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by AT&T Corp filed Critical AT&T Corp
Publication of DE69228044D1 publication Critical patent/DE69228044D1/de
Application granted granted Critical
Publication of DE69228044T2 publication Critical patent/DE69228044T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • C—CHEMISTRY; METALLURGY
    • C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
    • C23F—NON-MECHANICAL REMOVAL OF METALLIC MATERIAL FROM SURFACE; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL; MULTI-STEP PROCESSES FOR SURFACE TREATMENT OF METALLIC MATERIAL INVOLVING AT LEAST ONE PROCESS PROVIDED FOR IN CLASS C23 AND AT LEAST ONE PROCESS COVERED BY SUBCLASS C21D OR C22F OR CLASS C25
    • C23F4/00—Processes for removing metallic material from surfaces, not provided for in group C23F1/00 or C23F3/00
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321—After treatment
    • H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
    • H01L21/32133—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only
    • H01L21/32134—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by liquid etching only
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321—After treatment
    • H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
    • H01L21/32133—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only
    • H01L21/32135—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only
    • H01L21/32136—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only using plasmas
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321—After treatment
    • H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
    • H01L21/32139—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer using masks
DE69228044T 1991-10-28 1992-10-21 Verfahren zur Strukturierung von Wolframschichten Expired - Fee Related DE69228044T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US07/783,647 US5176792A (en) 1991-10-28 1991-10-28 Method for forming patterned tungsten layers

Publications (2)

Publication Number Publication Date
DE69228044D1 true DE69228044D1 (de) 1999-02-11
DE69228044T2 DE69228044T2 (de) 1999-08-19

Family

ID=25129969

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69228044T Expired - Fee Related DE69228044T2 (de) 1991-10-28 1992-10-21 Verfahren zur Strukturierung von Wolframschichten

Country Status (4)

Country Link
US (1) US5176792A (de)
EP (1) EP0540230B1 (de)
JP (1) JPH06291089A (de)
DE (1) DE69228044T2 (de)

Families Citing this family (28)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3179212B2 (ja) * 1992-10-27 2001-06-25 日本電気株式会社 半導体装置の製造方法
US5338702A (en) * 1993-01-27 1994-08-16 International Business Machines Corporation Method for fabricating tungsten local interconnections in high density CMOS
US5882992A (en) * 1994-08-25 1999-03-16 International Business Machines Corporation Method for fabricating Tungsten local interconnections in high density CMOS circuits
JPH08186120A (ja) * 1994-12-28 1996-07-16 Nec Corp 半導体装置の製造方法
KR100322696B1 (ko) * 1995-03-29 2002-06-20 김순택 전계효과전자방출용마이크로-팁및그제조방법
US5843289A (en) 1996-01-22 1998-12-01 Etex Corporation Surface modification of medical implants
US6033582A (en) 1996-01-22 2000-03-07 Etex Corporation Surface modification of medical implants
US5681486A (en) * 1996-02-23 1997-10-28 The Boeing Company Plasma descaling of titanium and titanium alloys
US5866483A (en) * 1997-04-04 1999-02-02 Applied Materials, Inc. Method for anisotropically etching tungsten using SF6, CHF3, and N2
KR100397860B1 (ko) 1997-09-22 2003-12-18 카가쿠기쥬쯔죠 킨조쿠자이료 기쥬쯔켄큐죠 반응성이온에칭법및그장치
US6872322B1 (en) 1997-11-12 2005-03-29 Applied Materials, Inc. Multiple stage process for cleaning process chambers
US6136211A (en) * 1997-11-12 2000-10-24 Applied Materials, Inc. Self-cleaning etch process
US6322714B1 (en) 1997-11-12 2001-11-27 Applied Materials Inc. Process for etching silicon-containing material on substrates
US6797188B1 (en) 1997-11-12 2004-09-28 Meihua Shen Self-cleaning process for etching silicon-containing material
JP3576783B2 (ja) * 1997-12-26 2004-10-13 Ｔｄｋ株式会社 薄膜磁気ヘッドの製造方法
US6958295B1 (en) * 1998-01-20 2005-10-25 Tegal Corporation Method for using a hard mask for critical dimension growth containment
US6527968B1 (en) * 2000-03-27 2003-03-04 Applied Materials Inc. Two-stage self-cleaning silicon etch process
SE517275C2 (sv) * 2000-09-20 2002-05-21 Obducat Ab Sätt vid våtetsning av ett substrat
US6905800B1 (en) 2000-11-21 2005-06-14 Stephen Yuen Etching a substrate in a process zone
US6852242B2 (en) 2001-02-23 2005-02-08 Zhi-Wen Sun Cleaning of multicompositional etchant residues
US6863930B2 (en) 2002-09-06 2005-03-08 Delphi Technologies, Inc. Refractory metal mask and methods for coating an article and forming a sensor
US8118946B2 (en) * 2007-11-30 2012-02-21 Wesley George Lau Cleaning process residues from substrate processing chamber components
US8052776B2 (en) 2009-05-29 2011-11-08 Corning Incorporated Poly(amino-alcohol)-silica hybrid compositions and membranes
DE102011075888B4 (de) 2011-05-16 2014-07-10 Robert Bosch Gmbh Halbleitervorrichtung mit mindestens einem Kontakt und Herstellungsverfahren für eine Halbleitervorrichtung mit mindestens einem Kontakt
JP6422262B2 (ja) * 2013-10-24 2018-11-14 東京エレクトロン株式会社 プラズマ処理方法及びプラズマ処理装置
DE102013226270B3 (de) 2013-12-17 2015-04-02 Forschungsverbund Berlin E.V. Verfahren zum Ausbilden eines Metallkontakts auf einer Oberfläche eines Halbleiters und Vorrichtung mit einem Metallkontakt
US9595448B2 (en) * 2015-06-29 2017-03-14 Taiwan Semiconductor Manufacturing Co., Ltd. Method for cleaning plasma processing chamber and substrate
GB202010407D0 (en) * 2020-07-07 2020-08-19 Univ Court Univ Of Glasgow Micromachined mechcahnical part and methods of fabrication thereof

Family Cites Families (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5032538A (en) * 1979-08-10 1991-07-16 Massachusetts Institute Of Technology Semiconductor embedded layer technology utilizing selective epitaxial growth methods
US4674174A (en) * 1984-10-17 1987-06-23 Kabushiki Kaisha Toshiba Method for forming a conductor pattern using lift-off
JPS6196765A (ja) * 1984-10-17 1986-05-15 Toshiba Corp 金属パタ−ン形成方法
JPS6212502A (ja) * 1986-07-04 1987-01-21 Toshiba Seiki Kk 電子部品の搬送装置
JPS6336547A (ja) * 1986-07-31 1988-02-17 Nec Corp 半導体装置の製造方法
FR2613134B1 (fr) * 1987-03-24 1990-03-09 Labo Electronique Physique Dispositif semiconducteur du type transistor a effet de champ
JPS647621A (en) * 1987-06-30 1989-01-11 Yokogawa Electric Corp Manufacture of mesfet
JPH01236622A (ja) * 1988-03-17 1989-09-21 Toshiba Corp Ｘ線マスク及びその製造方法
US4898804A (en) * 1988-03-31 1990-02-06 Cornell Research Foundation Self-aligned, high resolution resonant dielectric lithography
US4900398A (en) * 1989-06-19 1990-02-13 General Motors Corporation Chemical milling of titanium
JP3371143B2 (ja) * 1991-06-03 2003-01-27 ソニー株式会社 ドライエッチング方法

Also Published As

Publication number Publication date
JPH06291089A (ja) 1994-10-18
EP0540230A2 (de) 1993-05-05
EP0540230A3 (en) 1993-08-25
EP0540230B1 (de) 1998-12-30
US5176792A (en) 1993-01-05
DE69228044T2 (de) 1999-08-19

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee