DE69133497T2 - Leiterrahmen für eine Halbleiteranordnung und dessen Herstellungsverfahren - Google Patents
Leiterrahmen für eine Halbleiteranordnung und dessen Herstellungsverfahren Download PDFInfo
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- DE69133497T2 DE69133497T2 DE69133497T DE69133497T DE69133497T2 DE 69133497 T2 DE69133497 T2 DE 69133497T2 DE 69133497 T DE69133497 T DE 69133497T DE 69133497 T DE69133497 T DE 69133497T DE 69133497 T2 DE69133497 T2 DE 69133497T2
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- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/1517—Multilayer substrate
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- H01L2924/161—Cap
- H01L2924/1615—Shape
- H01L2924/16152—Cap comprising a cavity for hosting the device, e.g. U-shaped cap
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- H—ELECTRICITY
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- H01L2924/1901—Structure
- H01L2924/1904—Component type
- H01L2924/19041—Component type being a capacitor
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
- H01L2924/1901—Structure
- H01L2924/1904—Component type
- H01L2924/19043—Component type being a resistor
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
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- H01L2924/351—Thermal stress
Description
- Die vorliegende Erfindung betrifft eine Halbleitervorrichtung, bei welcher eine elektrische Verbindung zwischen Elektroden auf einem Halbleiterchip und inneren Leitungen auf einem Leiterrahmen bereitgestellt ist und eine elektrische Verbindung zwischen äußeren Leitungen des Leiterrahmens und Verdrahtungsmustern auf einer Leiterplatte und dessen Herstellungsverfahren, und im Genaueren eine Halbleitervorrichtung, in der ein Abstand zwischen Elektroden auf dem Halbleiterchip, um die elektrische Verbindung bereitzustellen, und ein Abstand zwischen den inneren Leitungen des Leiterrahmens und ein Abstand zwischen den aüßeren Leitungen davon exakt sind, und deren Herstellungsverfahren.
- Wenn die Halbleitervorrichtung hergestellt wird, gibt es zahlreiche Teile, wo eine elektrische Verbindung vorzusehen ist, wie beispielsweise ein Teil zwischen einem elektrischen Anschlußflecken auf einem Halbleiterchip und einer inneren Leitung eines Leitungsrahmens und ein Teil zwischen einer äußeren Leitung des Leitungsrahmens und einem Verdrahtungsmuster auf einer Leiterplatte.
- Herkömmlicherweise wird die elektrische Leiterplatte zwischen dem Elektrodenanschlußflecken auf dem Halbleiterchip und der inneren Leitung durch eine Metallbondierung, wie beispielsweise eine Drahtbondierung unter Verwendung von AU-Draht oder Al-Draht, ein TAB-(automatisches Filmbondierungs-) Verfahren, einen ohmschen Kontakt, wie beispielsweise einen metallischen Kontakt zwischen einer Bump-Elektrode auf einem Flip-Chip und einer Leitung, und ähnliches durchgeführt.
- Hinsichtlich der Verbindung durch eine Verdrahtungsbondierung ist der kürzeste Abstand zwischen benachbarten Drähten durch die äußere Form eines zu verwendenden Bondierungskapillars beschränkt. Deshalb ist es schwierig, den Abstand zwischen den Anschlußflecken auf dem Halbleiterchip so zu reduzieren, um etwa 100 μm zu sein.
- Darüber hinaus ist es zum Verbinden einer Au-Kugel oder eines Al-Drahts mit einem Aluminium-Anschlußflecken auf dem Halbleiterchip nötig, eine physikalische Belastung, wie beispielsweise ein Erhitzen, ein Drücken, eine Ultraschallschwingung, anzuwenden. Daher wird oft der Halbleiterchip selbst unter dem Elektroden-Anschlußflecken beschädigt.
- In dem Fall, in welchem ein TAB-System oder das Flip-Chip verwendet wird, ist es nötig, einen Au-Bump oder einen Plattierungsbump mit dem inneren Leiter über Metall zu verbinden. Deshalb wird die Temperatur des obigen Falls oft größer als diejenige, bei der Drahtbondierungsverbindung, so daß eine physikalische Beschädigung aufgrund von Druck zurückbleibt. In diesem Fall kann der Abstand zwischen den Anschlußflecken auf etwa 80 μm reduziert werden, jedoch gibt es eine Beschränkung in bezug auf die Reduzierung der Bumpgröße aufgrund der Verwendung der Metallverbindung. Darüber hinaus wird eine große Anzahl von Teilen gleichzeitig verbunden. Deshalb ist es bei einem weiteren Größerwerden der Anzahl von Teilen, die zu verbinden sind, schwieriger, eine stabile Verbindung angesichts der Höhe des Bumps und des Zustands der Verbindung zu erhalten. Deshalb ist es erforderlich, daß die Prozessbedingungen bzw. -zustände stabilisiert werden.
- Das oben angegebene Problem tritt nicht nur bei der elektrischen Verbindung zwischen dem Anschlußflecken auf dem Halbleiterchip oder dem Bump und der inneren Leitung auf, sondern auch bei der elektrischen Verbindung zwischen der äußeren Leitung und dem Verdrahtungsmuster auf der Leiterplatte.
- Es ist eine Aufgabe der vorliegenden Erfindung, eine Halbleitervorrichtung zu schaffen, bei welcher die Abstände zwischen Teilen, die elektrisch zu verbinden sind, um mehr als im herkömmlichen Fall reduziert werden können, und eine hohe Zuverlässigkeit erhalten werden kann, ohne physikalische Beschädigungen aufgrund von Erhitzen, Drücken, wenn eine elektrische Verbindung hergestellt wird, anzulegen, und ihr Herstellungsverfahren.
- In JP-A-01207938 ist ein Verfahren offenbart, in dem Leiter mit Elektroden-Anschlußflecken von Halbleiterchips verbunden werden, das die Verwendung von leitender Paste einbindet, die in Aperturen des isolierenden Filmträgers für die Leiter disponiert ist, dessen Aperturen mit den Elektroden ausgerichtet sind.
- In JP-A-02121359 ist eine Verbesserung der Verbindung zwischen einem Leiter und einer Stromleiter-Schaltung der Bindungsstärke und elektrische Zuverlässigkeit durch ein Verfahren beschrieben, in dem eine Plattierungsschicht auf der Oberfläche eines Leiters, einem elektrisch leitenden Verbindungsvermittler und einer Stromleiter-Schaltung ausgebildet ist.
- Gemäß der Erfindung ist eine Halbleitervorrichtung bereitgestellt, umfassend: a) einen aus leitendem Material gebildeten mindestens einen Leiter aufweisenden Leiterrahmen; b) einen mindestens eine Elektrode auf seiner Oberfläche aufweisenden Halbleiterchip; und wobei jeder der Leiter durch einen leitenden Klebstoff elektrisch verbunden ist mit einer jeweiligen Elektrode, gekennzeichnet durch c) einen erster Verbindungsabschnitt, wobei jeder der Leiter des Leiterrahmens durch einen leitenden Klebstoff mit der jeweiligen Elektrode auf dem Halbleiterchip elektrisch verbunden ist; und d) einen zweiten Verbindungsabschnitt, wobei jeder Leiter mit der jeweiligen Elektrode auf dem Halbleiterchip elektrisch durch eine den ersten Verbindungsabschnitt bedeckenden und umgebenden und sich bis zu der Elektrode und dem Leiter erstreckende und beide, den Leiter und die Elektrode, verbindende metallischen Plattierung verbunden ist.
- Des weiteren ist emäß der Erfindung ist ein Verfahren zur Herstellung einer Halbleitervorrichtung bereitgestellt, umfassend die Schritte: a) Bilden eines leitenden Klebstoffes als einen ersten Verbindungsabschnitt auf jeder einer Vielzahl von Elektroden eines Halbleiterchips durch ein Schablonendruck Verfahren, b) Anhaften jeder Elektrode an einen jeweiligen Leiter eines aus leitendem Material gebildeten Leiterrahmens mittels des ersten Verbindungsabschnitts, und c) Bilden einer metallischen Plattierung als einen zweiten jeden ersten Verbindungsabschnitt umgebenden Verbindungsabschnitt, wobei die Plattierungsschicht jede Elektrode und den jeweiligen Leiter elektrisch verbindet und sich bis zu der Elektrode und dem Leiter erstreckt und beide, den Leiter und die Elektrode, verbindet.
- Diese Erfindung kann vollständiger aus der folgenden detaillierten Beschreibung verstanden werden, wenn sie in Zusammenhang mit den beigefügten Zeichnungen genommen wird, wobei:
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1 eine Querschnittsansicht ist, die die Struktur eines Teils einer Vorrichtung zeigt, die nicht in Übereinstimmung mit der vorliegenden Erfindung ist; -
2 eine Querschnittsansicht ist, die eine allgemeine Struktur der Vorrichtung aus1 zeigt; -
3 eine Querschnittsansicht ist, die eine spezifische Struktur eines Elektroden-Anschlußfleckens der Vorrichtung aus1 zeigt; -
4 eine Draufsicht ist, die einen Zustand der Verbindung zwischen einer Vielzahl von Elektroden-Anschlußflecken der Vorrichtung aus1 und einer Vielzahl von inneren Leitungen zeigt; -
5 und6 jeweils Draufsichten auf ein TAB-Band sind, das bei der Vorrichtung aus1 verwendet wird; -
7 und8 jeweils Draufsichten auf Modifikationen der Vorrichtung aus1 sind; -
9 eine Querschnittsansicht ist, die eine andere Vorrichtung zeigt, die nicht in Übereinstimmung vorliegenden Erfindung ist. -
10 eine Querschnittsansicht ist, die eine Vorrichtung nach einem Ausführungsbeispiel der vorliegenden Erfindung zeigt. - Ein Ausführungsbeispiel der vorliegenden Erfindung wird unter Bezugnahme auf die Zeichnungen, von denen
1 –9 nicht in Übereinstimmung sind mit der vorliegenden Erfindung sind aber das Verständnis dieser erleichtern, erklärt werden. -
1 zeigt die Struktur eines Teils einer Halbleitervorrichtung und der Verbindung zwischen einer Vielzahl von Elektroden-Anschlußflecken auf einem Halbleiterchip und einer Vielzahl von inneren Leitungen an einem TAB-Band verwendet wird, und2 ist die allgemeine Struktur davon. - In den Zeichnungen ist ein Bezugszeichen
11 ein Halbleiterchip mit einem aktiven Element, wie beispielsweise einem Transistor, und einem passiven Element, wie beispielsweise einem Widerstand und einem Kondensator. Um die Hauptoberfläche des Halbleiterchips11 ist eine Vielzahl von Elektroden-Anschlußflecken14 ausgebildet, die aus einer ersten metallischen Schicht12 ausgebildet sind, die eine aus Aluminium (Al) ausgebildete untere Schicht aufweist, und aus einer zweiten metallischen Schicht13 , die eine obere Schicht aus wenigstens einer Nickelschicht aufweist. Diese Elektroden-Anschlußflecken14 sind in einer Reihe mit einem vorbestimmten Abstand angeordnet. Die Teile des Halbleiterchips11 , die andere als die Elektrodenanschlußflecken-Ausbildungsposition sind, sind mit einem isolierenden Oberflächenschutzfilm15 bedeckt, wie beispielsweise einem Siliziumoxidationsfilm. Der Halbleiterchip11 ist an einen vorbestimmten Teil eines TAB-Bandes17 durch ein Epoxy-Klebemittel16 angebracht. - Wie es in
1 gezeigt ist, ist das TAB-Band17 aus Epoxy- oder Polyimid-Harz hergestellt. Eine Metallfolie, wie beispielsweise eine Kupfer-(Cu)-Folie, mit einer Dicke von etwa 35 μm ist auf einem organischen Filmmaterial18 mit einer Dicke von etwa 75 μm laminiert. Danach wird ein Verdrahtungsmuster, das eine Vielzahl von inneren Leitungen19 aufweist, die mit der Vielzahl von Elektroden-Anschlußflecken14 zu verbinden sind, durch eine Auswahl-Ätztechnik ausgebildet, und mit den äußeren Leitungen, die mit diesen inneren Leitungen elektrisch verbunden sind (nicht gezeigt). Die Verdrahtungsmuster-Ausbildungsoberfläche ist durch ein Klebemittel16 am Halbleiterchip11 angebracht. - Wenn der Halbleiterchip
11 am TAB-Band17 angebracht wird, wird das Positionieren in einem Zustand durchgeführt, in welchem jeder Elektroden-Anschlußflecken14 nahe dem Teil positioniert wird, wo jede Endoberfläche der Endteile der Vielzahl von inneren Leitungen19 freigelegt ist. Dann wird jeder Elektroden-Anschlußflecken14 auf dem Halbleiterchip11 und jeder Endteil des inneren Leiters19 durch eine metallische Plattierungsschicht20 , die aus Nickel (Ni) gebildet ist, elektrisch verbunden. -
3 zeigt die spezifische Struktur eines jeweiligen Elektroden-Anschlußfleckens14 . Die zweite Metallschicht13 , die auf der aus Aluminium (Al) hergestellten ersten Metallschicht12 ausgebildet ist, weist wenigstens zwei Metallschichten auf. Spezifischer wird die untere Schicht, die die aus Aluminium hergestellte erste Metallschicht kontaktiert, aus einer Titan-(Ti)-Schicht31 mit einer Dicke von 100 nm (1000 Å) ausgebildet, und die obere Schicht wird aus einer Nickel-(Ni)-Schicht32 mit einer Dicke von 300 nm (3000 Å) ausgebildet. Die Nickelschicht32 , die die obere Schicht der zweiten Metallschicht13 ist, wird ausgebildet, um zuzulassen, daß die metallische Plattierungsschicht20 aus Nickel auf dem Elektroden-Anschlußflecken14 ausgebildet wird. Ebenso hat die Titanschicht31 , die die untere Schicht der zweiten Metallschicht13 ist, eine Funktion als Grenzmetall. -
4 zeigt einen Zustand der Verbindung zwischen der Vielzahl von Elektroden-Anschlußflecken14 und der Vielzahl von inneren Leitungen19 des TAB-Bandes17 . In der Zeichnung zeigt ein Bereich, in welchem schräge Linien hinzugefügt sind, die metallische Plattierungsschicht20 . - Jeder Elektroden-Anschlußflecken
14 auf dem Halbleiterchip11 und jede innere Leitung19 sind durch die metallische Plattierungsschicht20 verbunden. Deshalb sind ein Bondierungskapillar und ein TAB-Werkzeug, die bei einem Drahtbondieren und einer TAB-Verbindung verwendet werden, nicht erforderlich. Dadurch kann der Abstand zwischen Elektroden-Anschlußflecken14 auf 100 μm oder darunter reduziert werden, z.B. etwa 50 μm. - Darüber hinaus wird dann, wenn jeder Elektroden-Anschlußflecken
14 und jede innere Leitung19 elektrisch verbunden werden, ein physikalischer Druck auf den Halbleiterchip11 ausgeübt, so daß eine Zuverlässigkeit aufgrund einer Druckbeschädigung nicht verringert wird. Dann kann deshalb, weil eine große Anzahl von Teilen gleichzeitig unter derselben Bedingung verbunden werden kann, eine Zuverlässigkeit einer Verbindung verbessert werden. Darüber hinaus ist es deshalb, weil es keine Notwendigkeit zum Heizen gibt, wenn die Verbindung durchgeführt wird, möglich, zu verhindern, daß eine Zuverlässigkeit durch eine thermische Belastung verringert wird, was durch eine Fehlanpassung des thermischen Expansionskoeffizienten jeder Halbleiterschicht im Halbleiterchip verursacht wird. - Ein Verfahren zum Ausbilden der obigen metallischen Plattierungsschicht, wo die Elektroden-Anschlußflecken und die inneren Leitungen elektrisch verbunden werden, wird erklärt werden.
- In dem TAB-Band, wie es in
5 gezeigt ist, wird eine Metallfolie, wie beispielsweise eine Kupferfolie, auf dem organischen Filmmaterial18 im voraus laminiert. Danach wird in jeder Halbleitervorrichtung eine Vielzahl von Leitungselektroden41 mit den inneren Leitungen und den mit den inneren Leitungen verbundenen äußeren Leitungen durch die Auswahl-Ätztechnik ausgebildet. Gleichzeitig mit dem Durchführen des Auswahlätzens werden gemeinsame Elektroden42 , die mit den Leitungselektroden41 elektrisch verbunden werden, um jede Halbleitervorrichtung in einem Zustand ausgebildet, daß alle gemeinsamen Elektroden42 verbunden werden. Zusätzlich ist in5 ein Bezugszeichen43 eine Öffnung, die im organischen Filmmaterial18 ausgebildet ist. -
6 zeigt eine vergrößerte einzelne Halbleitervorrichtung im TAB-Band der5 . In der Zeichnung ist der Halbleiterchip am TAB-Band in einem Zustand angebracht, in welchem der Halbleiterchip in dem durch eine einzelne gestrichelte Linie gezeigten Bereich positioniert ist. In diesem Fall ist der Halbleiterchip am TAB-Band so angebracht, daß der Anschlußflecken jeder Elektrode auf dem Halbleiterchip nahe dem Teil positioniert ist, wo jedes Ende des Endteils der Vielzahl von Leitungen freigelegt ist. - Danach wird das TAB-Band in ein Nickel-Plattierungsbad zusammen mit einer Plattierungselektrode eingetaucht. Das Nickel-Plattierungsbad wird allgemein Watt-Bad genannt, und Nickel-Sulfat, Nickel-Chlorid und ein Klebemittel werden verwendet. Nachdem das TAB-Band und die Plattierungselektrode in das Watt-Bad eingetaucht sind, wird eine vorbestimmte Gleichspannung zwischen der gemeinsamen Elektrode
42 und der Plattierungselektrode angelegt, so daß die gemeinsame Elektrode42 als positive Elektrode dient und die Plattierungselektrode als negative Elektrode dient, und ein elektrolytisches Plattieren wird für eine vorbestimmte Zeitperiode durchgeführt. Beispielsweise wurde eine anzulegende Gleichspannung auf 2 V eingestellt, wurde ein zwischen der positiven und der negativen Elektrode zuzuführender Strom auf 60 mA eingestellt und wurde die Plattierungszeit auf 10 Minuten eingestellt. Als Ergebnis wurde eine Nickelplattierungsschicht mit einer Dicke von 10 μm als metallische Plattierungsschicht20 erhalten. Die metallische Plattierungsschicht wächst von jeder Endfläche von dem obersten Endteil des inneren Leiters auf, direkt nachdem eine Plattierung beginnt. Dann, wenn das Aufwachsen fortschreitet und die Plattierungsschicht den Elektroden- Anschlußflecken auf dem Halbleiterchip kontaktiert, wächst auch die Metallschicht an dem Elektroden-Anschlußflecken auf, und sowohl die gemeinsame Elektrode42 als auch die Plattierungselektrode sind schließlich durch die Plattierungsschicht elektrisch verbunden. Nach dem Ende einer Plattierung wird die Plattierungsschicht mit reinem Wasser gewaschen, und eine Kontaminierung, die beim Plattieren an die Oberfläche angebracht wurde, wird entfernt. Zusätzlich wird an der Oberfläche jeder Leitungselektrode41 , die die inneren und äußeren Leiter aufweist, das meiste der Oberfläche, das anders als der Endteil der inneren Leitung ist, mit dem Epoxy-Isolierfilm beschichtet, was Grünbeschichtung genannt wird. Dadurch ist es möglich, die Plattierungsschicht nur auf dem notwendigen Teil auszubilden. Daher kann eine Plattierungszeit verkürzt werden. - Obig wurden die Elektroden-Anschlußflecken mit einem vorbestimmten Abstand in einer Reihe angeordnet. Bei der modifizierten Vorrichtung der
7 sind die Elektroden-Anschlußflecken14 auf dem Halbleiterchip auf eine Zick-Zack-Weise angeordnet. Dieselben Bezugszeichen wie bei4 sind bei den Teilen hinzugefügt, die den Teilen der4 entsprechen, und die Erklärung davon ist weggelassen. -
8 zeigt eine Modifikation der Vorrichtung unter Verwendung eines Halbleiters, der das sogenannte Anschlußflecken-Layoutsystem mit freiem Zugriff ist, wobei die Elektroden-Anschlußflecken auf der gesamten Oberfläche des Halbleiterchips zufällig angeordnet sind. - Wie es oben angegeben ist, kann irgendein Typ von Chip ungeachtet der Anordnung der Elektroden-Anschlußflecken auf dem Chip verwendet werden.
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9 zeigt die Struktur einer anderen Halbleitervorrichtung, die nicht in Übereinstimung mit der vorliegenden Erfindung ist, wo die Verbindung zwischen den äußeren Leitern des Leiterrahmens und dem Verdrahtungsmuster auf der Leiterplatte ist. In der Zeichnung ist ein Bezugszeichen11 ein Halbleiterchip und ist ein Bezugszeichen17 ein TAB-Band. Der Endteil des inneren Leiters des TAB-Bandes und ein Elektroden-Anschlußflecken (nicht gezeigt) auf dem Halbleiterchip11 sind durch eine metallische Plattierungsschicht20 elektrisch verbunden, was ähnlich dem oben beschriebenen ist. Ein Verdrahtungsmuster52 , das auf einer Leiterplatte51 ausgebildet ist, und der äußere Leiter des TAB-Bandes sind durch die metallische Plattierungsschicht20 elektrisch verbunden. - Ein Ausführungsbeispiel der voriegenden Erfindung wird nun mit Bezug auf
10 beschrieben, die die Struktur der Halbleitervorrichtung und der Verbindung zwischen den inneren Leitern des Leiterrahmens und den Elektroden-Anschlußflecken des Halbleiterchips zeigt. - Nach dem Ausführungsbeispiel ist der Leiterrahmen ausgebilded durch Stanzen eines dünne metallischen Films, der aus einer Legierung, wie einer 4-2 Legierung und Kupfer durch einen Pressprozess ausgebildet ist. Ein innerer Leiter
53 des Leiterrahmens und ein Elektrodden-Anschlußflecken14 auf dem Halbleiterchip sind miteinander elektrisch verbunden durch Verwenden sowohl eines leitenden Klebemittels54 und einer Plattierungsschicht. In dem Fall der oben beschriebenen Vorrichtung, die ein TAB-Band verwendet, kann die Metall-Plattierungsschicht auf eine Art ausgebildet sein, dass der Halbleiterchip an das TAB-Band durch den Epoxyd-Kleber im voraus geklebt ist. In dem Fall aus10 des Verwendens des Leiterrahmens, der durch Stanzen des dünnen Metallfilms ausgebildet ist, ist der leitende Kleber54 auf jedem Elektroden-Anschlußflecken14 im Voraus ausgebildet durch ein Siebdruckverfahren, und der Elektroden-Anschlußflecken14 und der Leiterrahmen53 sind durch den leitenden Kleber54 angeklebt. Danach wird die Plattierungsschicht55 durch das selbe oben erwähnte Verfahren ausgeformt, und sowohl der Elektroden-Anschlußflecken als auch der Leiterrahmen können elektrisch verbunden werden. - Die vorliegende Erfindung ist nicht auf das oben angegebene Ausführungsbeispiel beschränkt. Es muß nicht gesagt werden, daß die vorliegende Erfindung modifiziert werden kann. Beispielsweise wurde oben der Fall beschrieben, bei welchem die metallische Plattierungsschicht eine Nickel-Plattierungsschicht war. Gemäß der vorliegenden Erfindung können eine Au-Plattierungsschicht und eine Kupfer-Plattierungsschicht zusätzlich zum obigen Fall verwendet werden.
- Oben wurde der Fall erklärt, in dem das meiste der anderen Oberfläche als das Endteil des inneren Leiters mit dem isolierenden Film im voraus beschichtet wurde. Jedoch ist in dem anderen Teil als dem Endteil des innerern Leiters die Dicke, aus der die Plattierungsschicht auf dem oberen Teil wachsen kann, ungefähr nur 1/10 mal die des Endteils, wenn das elektrolytische Palattieren ausgeführt wird, wobei das Kleben des isolierenden Films weggelassen werden kann.
- Darüber hinaus erklärte das Verfahren den Fall, dass die Plattierungsschicht durch das elektrolytische Plattierungsverfahren ausgebildet wurde. Jedoch kann die Plattierungsschicht durch ein elektroloses Plattierungsverfahren ausgebildet werden.
Claims (9)
- Halbleitervorrichtung, umfassend: a) einen aus leitendem Material gebildeten mindestens einen Leiter (
53 ) aufweisenden Leiterrahmen; b) einen mindestens eine Elektrode (14 ) auf seiner Oberfläche aufweisenden Halbleiterchip (11 ); und wobei jeder der Leiter elektrisch verbunden ist mit einer die elektrische Verbindung beinhaltenden jeweiligen Elektrode. c) einen erster Verbindungsabschnitt (54 ), wobei jeder der Leiter (53 ) des Leiterrahmens durch einen leitenden Klebstoff mit der jeweiligen Elektrode (14 ) auf dem Halbleiterchip elektrisch verbunden ist; wobei die elektrische Verbindung gekennzeichnet ist durch d) einen zweiten Verbindungsabschnitt (55 ), wobei jeder Leiter (53 ) mit der jeweiligen Elektrode (14 ) auf dem Halbleiterchip elektrisch durch eine den ersten Verbindungsabschnitt (54 ) bedeckenden und umgebenden und sich bis zu der Elektrode und dem Leiter erstreckende und beide, den Leiter und die Elektrode, verbindende metallischen Plattierung verbunden ist. - Halbleitervorrichtung nach Anspruch 1, dadurch gekennzeichnet, dass der Leiterrahmen (
53 ) aus einem gestanzten Metallfilm besteht. - Halbleitervorrichtung nach Anspruch 1, dadurch gekennzeichnet, dass eine Vielzahl der Elektroden (
14 ) auf der Oberfläche des Halbleiterchips gebildet ist und jede eine Aluminiumschicht (12 ), eine auf der Aluminiumschicht (12 ) gebildeten Titanschicht (31 ) und eine auf der Titanschicht gebildeten eine Nickelschicht oder eine Kupferschicht umfassende Metallschicht (32 ), umfasst. - Halbleitervorrichtung nach Anspruch 1 dadurch gekennzeichnet, dass eine Vielzahl der Elektroden auf dem Halbleiterchip in einer Zick-Zack-Art angeordnet sind.
- Halbleitervorrichtung nach Anspruch 1 dadurch gekennzeichnet, dass eine Vielzahl der Elektroden auf dem Halbleiterchip zufällig angeordnet sind.
- Halbleitervorrichtung nach Anspruch 1 dadurch gekennzeichnet, dass die metallische Plattierung (
55 ) der zweiten Verbindung ein Endteil des direkt an der Elektrode (14 ) anliegenden Leiters (53 ) kontaktiert. - Verfahren zur Herstellung einer Halbleitervorrichtung, umfassend die Schritte: a) Bilden eines leitenden Klebstoffes als einen ersten Verbindungsabschnitt (
54 ) auf jeder einer Vielzahl von Elektroden (14 ) eines Halbleiterchips durch ein Schablonendruck Verfahren, b) Anhaften jeder Elektrode (14 ) an einen jeweiligen Leiter (53 ) eines aus leitendem Material gebildeten Leiterrahmens mittels des ersten Verbindungsabschnitts (54 ), und c) Bilden einer metallischen Plattierung als einen zweiten jeden ersten Verbindungsabschnitt (54 ) umgebenden Verbindungsabschnitt (55 ), wobei die Plattierungsschicht jede Elektrode (14 ) und den jeweiligen Leiter elektrisch verbindet und sich bis zu der Elektrode und dem Leiter erstreckt und beide, den Leiter und die Elektrode, verbindet. - Verfahren zur Herstellung einer Halbleitervorrichtung nach Anspruch 7, dadurch gekennzeichnet, dass Schritt c) die Schritte umfasst: a) Eintauchen des Leiterrahmens und des Halbleiterchips in eine elektrolytische Plattierungslösung, und b) Bilden der metallischen Plattierungsschicht.
- Verfahren zur Herstellung einer Halbleitervorrichtung nach Anspruch 8, dadurch gekennzeichnet, dass der Leiterrahmen eine Vielzahl von Leitungselektroden (
41 ) aufweist, wobei die Vielzahl der Leitungselektroden (41 ) durch eine gemeinsame Elektrode (42 ) elektrisch verbunden sind, und ein elektrisches Potenzial an die gemeinsame Elektrode (42 ) angelegt ist, wenn die metallische Plattierungsschicht gebildet wird.
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
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JP14168490 | 1990-06-01 | ||
JP2141684A JP2540652B2 (ja) | 1990-06-01 | 1990-06-01 | 半導体装置 |
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DE69133497D1 DE69133497D1 (de) | 2006-01-19 |
DE69133497T2 true DE69133497T2 (de) | 2006-08-24 |
Family
ID=15297809
Family Applications (2)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
DE69133497T Expired - Fee Related DE69133497T2 (de) | 1990-06-01 | 1991-05-31 | Leiterrahmen für eine Halbleiteranordnung und dessen Herstellungsverfahren |
DE69132685T Expired - Fee Related DE69132685T2 (de) | 1990-06-01 | 1991-05-31 | Halbleiteranordnung bestehend aus einem TAB-Band und deren Herstellungsverfahren |
Family Applications After (1)
Application Number | Title | Priority Date | Filing Date |
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DE69132685T Expired - Fee Related DE69132685T2 (de) | 1990-06-01 | 1991-05-31 | Halbleiteranordnung bestehend aus einem TAB-Band und deren Herstellungsverfahren |
Country Status (5)
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US (1) | US5654584A (de) |
EP (2) | EP0459493B1 (de) |
JP (1) | JP2540652B2 (de) |
KR (1) | KR970000972B1 (de) |
DE (2) | DE69133497T2 (de) |
Families Citing this family (127)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5249728A (en) * | 1993-03-10 | 1993-10-05 | Atmel Corporation | Bumpless bonding process having multilayer metallization |
JPH0799213A (ja) * | 1993-06-09 | 1995-04-11 | At & T Corp | 集積回路チップ |
JP2833996B2 (ja) * | 1994-05-25 | 1998-12-09 | 日本電気株式会社 | フレキシブルフィルム及びこれを有する半導体装置 |
JP3226752B2 (ja) * | 1995-04-12 | 2001-11-05 | 株式会社東芝 | 半導体装置の製造方法 |
KR0157905B1 (ko) * | 1995-10-19 | 1998-12-01 | 문정환 | 반도체 장치 |
KR100186333B1 (ko) * | 1996-06-20 | 1999-03-20 | 문정환 | 칩 사이즈 반도체 패키지 및 그 제조방법 |
SG75841A1 (en) | 1998-05-02 | 2000-10-24 | Eriston Invest Pte Ltd | Flip chip assembly with via interconnection |
US6406939B1 (en) | 1998-05-02 | 2002-06-18 | Charles W. C. Lin | Flip chip assembly with via interconnection |
US6143981A (en) | 1998-06-24 | 2000-11-07 | Amkor Technology, Inc. | Plastic integrated circuit package and method and leadframe for making the package |
TW522536B (en) | 1998-12-17 | 2003-03-01 | Wen-Chiang Lin | Bumpless flip chip assembly with strips-in-via and plating |
TW444236B (en) | 1998-12-17 | 2001-07-01 | Charles Wen Chyang Lin | Bumpless flip chip assembly with strips and via-fill |
TW396462B (en) | 1998-12-17 | 2000-07-01 | Eriston Technologies Pte Ltd | Bumpless flip chip assembly with solder via |
KR100379089B1 (ko) * | 1999-10-15 | 2003-04-08 | 앰코 테크놀로지 코리아 주식회사 | 리드프레임 및 이를 이용한 반도체패키지 |
US6639308B1 (en) | 1999-12-16 | 2003-10-28 | Amkor Technology, Inc. | Near chip size semiconductor package |
US7042068B2 (en) | 2000-04-27 | 2006-05-09 | Amkor Technology, Inc. | Leadframe and semiconductor package made using the leadframe |
US6562657B1 (en) | 2000-08-22 | 2003-05-13 | Charles W. C. Lin | Semiconductor chip assembly with simultaneously electrolessly plated contact terminal and connection joint |
US6660626B1 (en) | 2000-08-22 | 2003-12-09 | Charles W. C. Lin | Semiconductor chip assembly with simultaneously electrolessly plated contact terminal and connection joint |
US6402970B1 (en) | 2000-08-22 | 2002-06-11 | Charles W. C. Lin | Method of making a support circuit for a semiconductor chip assembly |
US6436734B1 (en) | 2000-08-22 | 2002-08-20 | Charles W. C. Lin | Method of making a support circuit for a semiconductor chip assembly |
US6551861B1 (en) | 2000-08-22 | 2003-04-22 | Charles W. C. Lin | Method of making a semiconductor chip assembly by joining the chip to a support circuit with an adhesive |
US6562709B1 (en) | 2000-08-22 | 2003-05-13 | Charles W. C. Lin | Semiconductor chip assembly with simultaneously electroplated contact terminal and connection joint |
US6350633B1 (en) | 2000-08-22 | 2002-02-26 | Charles W. C. Lin | Semiconductor chip assembly with simultaneously electroplated contact terminal and connection joint |
US6403460B1 (en) | 2000-08-22 | 2002-06-11 | Charles W. C. Lin | Method of making a semiconductor chip assembly |
US6350386B1 (en) | 2000-09-20 | 2002-02-26 | Charles W. C. Lin | Method of making a support circuit with a tapered through-hole for a semiconductor chip assembly |
US6350632B1 (en) | 2000-09-20 | 2002-02-26 | Charles W. C. Lin | Semiconductor chip assembly with ball bond connection joint |
US6511865B1 (en) | 2000-09-20 | 2003-01-28 | Charles W. C. Lin | Method for forming a ball bond connection joint on a conductive trace and conductive pad in a semiconductor chip assembly |
US6448108B1 (en) | 2000-10-02 | 2002-09-10 | Charles W. C. Lin | Method of making a semiconductor chip assembly with a conductive trace subtractively formed before and after chip attachment |
US6544813B1 (en) | 2000-10-02 | 2003-04-08 | Charles W. C. Lin | Method of making a semiconductor chip assembly with a conductive trace subtractively formed before and after chip attachment |
US6548393B1 (en) | 2000-10-13 | 2003-04-15 | Charles W. C. Lin | Semiconductor chip assembly with hardened connection joint |
US6699780B1 (en) | 2000-10-13 | 2004-03-02 | Bridge Semiconductor Corporation | Method of connecting a conductive trace to a semiconductor chip using plasma undercut etching |
US6576539B1 (en) | 2000-10-13 | 2003-06-10 | Charles W.C. Lin | Semiconductor chip assembly with interlocked conductive trace |
US6673710B1 (en) | 2000-10-13 | 2004-01-06 | Bridge Semiconductor Corporation | Method of connecting a conductive trace and an insulative base to a semiconductor chip |
US6440835B1 (en) | 2000-10-13 | 2002-08-27 | Charles W. C. Lin | Method of connecting a conductive trace to a semiconductor chip |
US6492252B1 (en) | 2000-10-13 | 2002-12-10 | Bridge Semiconductor Corporation | Method of connecting a bumped conductive trace to a semiconductor chip |
US6908788B1 (en) | 2000-10-13 | 2005-06-21 | Bridge Semiconductor Corporation | Method of connecting a conductive trace to a semiconductor chip using a metal base |
US7071089B1 (en) | 2000-10-13 | 2006-07-04 | Bridge Semiconductor Corporation | Method of making a semiconductor chip assembly with a carved bumped terminal |
US7262082B1 (en) | 2000-10-13 | 2007-08-28 | Bridge Semiconductor Corporation | Method of making a three-dimensional stacked semiconductor package with a metal pillar and a conductive interconnect in an encapsulant aperture |
US6876072B1 (en) | 2000-10-13 | 2005-04-05 | Bridge Semiconductor Corporation | Semiconductor chip assembly with chip in substrate cavity |
US7414319B2 (en) * | 2000-10-13 | 2008-08-19 | Bridge Semiconductor Corporation | Semiconductor chip assembly with metal containment wall and solder terminal |
US7129113B1 (en) | 2000-10-13 | 2006-10-31 | Bridge Semiconductor Corporation | Method of making a three-dimensional stacked semiconductor package with a metal pillar in an encapsulant aperture |
US7009297B1 (en) | 2000-10-13 | 2006-03-07 | Bridge Semiconductor Corporation | Semiconductor chip assembly with embedded metal particle |
US7094676B1 (en) | 2000-10-13 | 2006-08-22 | Bridge Semiconductor Corporation | Semiconductor chip assembly with embedded metal pillar |
US7190080B1 (en) | 2000-10-13 | 2007-03-13 | Bridge Semiconductor Corporation | Semiconductor chip assembly with embedded metal pillar |
US6740576B1 (en) | 2000-10-13 | 2004-05-25 | Bridge Semiconductor Corporation | Method of making a contact terminal with a plated metal peripheral sidewall portion for a semiconductor chip assembly |
US6576493B1 (en) | 2000-10-13 | 2003-06-10 | Bridge Semiconductor Corporation | Method of connecting a conductive trace and an insulative base to a semiconductor chip using multiple etch steps |
US7132741B1 (en) | 2000-10-13 | 2006-11-07 | Bridge Semiconductor Corporation | Semiconductor chip assembly with carved bumped terminal |
US7264991B1 (en) | 2000-10-13 | 2007-09-04 | Bridge Semiconductor Corporation | Method of connecting a conductive trace to a semiconductor chip using conductive adhesive |
US7319265B1 (en) | 2000-10-13 | 2008-01-15 | Bridge Semiconductor Corporation | Semiconductor chip assembly with precision-formed metal pillar |
US6949408B1 (en) | 2000-10-13 | 2005-09-27 | Bridge Semiconductor Corporation | Method of connecting a conductive trace and an insulative base to a semiconductor chip using multiple etch steps |
US6667229B1 (en) | 2000-10-13 | 2003-12-23 | Bridge Semiconductor Corporation | Method of connecting a bumped compliant conductive trace and an insulative base to a semiconductor chip |
US7129575B1 (en) | 2000-10-13 | 2006-10-31 | Bridge Semiconductor Corporation | Semiconductor chip assembly with bumped metal pillar |
US6872591B1 (en) | 2000-10-13 | 2005-03-29 | Bridge Semiconductor Corporation | Method of making a semiconductor chip assembly with a conductive trace and a substrate |
US6537851B1 (en) | 2000-10-13 | 2003-03-25 | Bridge Semiconductor Corporation | Method of connecting a bumped compliant conductive trace to a semiconductor chip |
US7075186B1 (en) | 2000-10-13 | 2006-07-11 | Bridge Semiconductor Corporation | Semiconductor chip assembly with interlocked contact terminal |
US6984576B1 (en) | 2000-10-13 | 2006-01-10 | Bridge Semiconductor Corporation | Method of connecting an additively and subtractively formed conductive trace and an insulative base to a semiconductor chip |
US6444489B1 (en) | 2000-12-15 | 2002-09-03 | Charles W. C. Lin | Semiconductor chip assembly with bumped molded substrate |
US6653170B1 (en) | 2001-02-06 | 2003-11-25 | Charles W. C. Lin | Semiconductor chip assembly with elongated wire ball bonded to chip and electrolessly plated to support circuit |
KR100369393B1 (ko) | 2001-03-27 | 2003-02-05 | 앰코 테크놀로지 코리아 주식회사 | 리드프레임 및 이를 이용한 반도체패키지와 그 제조 방법 |
US6905914B1 (en) | 2002-11-08 | 2005-06-14 | Amkor Technology, Inc. | Wafer level package and fabrication method |
US7723210B2 (en) | 2002-11-08 | 2010-05-25 | Amkor Technology, Inc. | Direct-write wafer level chip scale package |
US7993983B1 (en) | 2003-11-17 | 2011-08-09 | Bridge Semiconductor Corporation | Method of making a semiconductor chip assembly with chip and encapsulant grinding |
US7538415B1 (en) | 2003-11-20 | 2009-05-26 | Bridge Semiconductor Corporation | Semiconductor chip assembly with bumped terminal, filler and insulative base |
US7425759B1 (en) | 2003-11-20 | 2008-09-16 | Bridge Semiconductor Corporation | Semiconductor chip assembly with bumped terminal and filler |
US7761814B2 (en) | 2004-09-13 | 2010-07-20 | Microsoft Corporation | Flick gesture |
US7268421B1 (en) | 2004-11-10 | 2007-09-11 | Bridge Semiconductor Corporation | Semiconductor chip assembly with welded metal pillar that includes enlarged ball bond |
US7446419B1 (en) | 2004-11-10 | 2008-11-04 | Bridge Semiconductor Corporation | Semiconductor chip assembly with welded metal pillar of stacked metal balls |
US7750483B1 (en) | 2004-11-10 | 2010-07-06 | Bridge Semiconductor Corporation | Semiconductor chip assembly with welded metal pillar and enlarged plated contact terminal |
US7507603B1 (en) | 2005-12-02 | 2009-03-24 | Amkor Technology, Inc. | Etch singulated semiconductor package |
US7572681B1 (en) | 2005-12-08 | 2009-08-11 | Amkor Technology, Inc. | Embedded electronic component package |
US7902660B1 (en) | 2006-05-24 | 2011-03-08 | Amkor Technology, Inc. | Substrate for semiconductor device and manufacturing method thereof |
US7968998B1 (en) | 2006-06-21 | 2011-06-28 | Amkor Technology, Inc. | Side leaded, bottom exposed pad and bottom exposed lead fusion quad flat semiconductor package |
JP2008078561A (ja) * | 2006-09-25 | 2008-04-03 | Toshiba Corp | 半導体装置及びその製造方法 |
US7811863B1 (en) | 2006-10-26 | 2010-10-12 | Bridge Semiconductor Corporation | Method of making a semiconductor chip assembly with metal pillar and encapsulant grinding and heat sink attachment |
US7494843B1 (en) | 2006-12-26 | 2009-02-24 | Bridge Semiconductor Corporation | Method of making a semiconductor chip assembly with thermal conductor and encapsulant grinding |
US7687893B2 (en) | 2006-12-27 | 2010-03-30 | Amkor Technology, Inc. | Semiconductor package having leadframe with exposed anchor pads |
US7829990B1 (en) | 2007-01-18 | 2010-11-09 | Amkor Technology, Inc. | Stackable semiconductor package including laminate interposer |
US7982297B1 (en) | 2007-03-06 | 2011-07-19 | Amkor Technology, Inc. | Stackable semiconductor package having partially exposed semiconductor die and method of fabricating the same |
US7977774B2 (en) | 2007-07-10 | 2011-07-12 | Amkor Technology, Inc. | Fusion quad flat semiconductor package |
US7687899B1 (en) | 2007-08-07 | 2010-03-30 | Amkor Technology, Inc. | Dual laminate package structure with embedded elements |
US7777351B1 (en) | 2007-10-01 | 2010-08-17 | Amkor Technology, Inc. | Thin stacked interposer package |
US8089159B1 (en) | 2007-10-03 | 2012-01-03 | Amkor Technology, Inc. | Semiconductor package with increased I/O density and method of making the same |
US7847386B1 (en) | 2007-11-05 | 2010-12-07 | Amkor Technology, Inc. | Reduced size stacked semiconductor package and method of making the same |
US7956453B1 (en) | 2008-01-16 | 2011-06-07 | Amkor Technology, Inc. | Semiconductor package with patterning layer and method of making same |
US7723852B1 (en) | 2008-01-21 | 2010-05-25 | Amkor Technology, Inc. | Stacked semiconductor package and method of making same |
US8067821B1 (en) | 2008-04-10 | 2011-11-29 | Amkor Technology, Inc. | Flat semiconductor package with half package molding |
US7768135B1 (en) | 2008-04-17 | 2010-08-03 | Amkor Technology, Inc. | Semiconductor package with fast power-up cycle and method of making same |
US7808084B1 (en) | 2008-05-06 | 2010-10-05 | Amkor Technology, Inc. | Semiconductor package with half-etched locking features |
US8125064B1 (en) | 2008-07-28 | 2012-02-28 | Amkor Technology, Inc. | Increased I/O semiconductor package and method of making same |
US8184453B1 (en) | 2008-07-31 | 2012-05-22 | Amkor Technology, Inc. | Increased capacity semiconductor package |
US7847392B1 (en) | 2008-09-30 | 2010-12-07 | Amkor Technology, Inc. | Semiconductor device including leadframe with increased I/O |
US7989933B1 (en) | 2008-10-06 | 2011-08-02 | Amkor Technology, Inc. | Increased I/O leadframe and semiconductor device including same |
US8008758B1 (en) | 2008-10-27 | 2011-08-30 | Amkor Technology, Inc. | Semiconductor device with increased I/O leadframe |
US8089145B1 (en) | 2008-11-17 | 2012-01-03 | Amkor Technology, Inc. | Semiconductor device including increased capacity leadframe |
US8072050B1 (en) | 2008-11-18 | 2011-12-06 | Amkor Technology, Inc. | Semiconductor device with increased I/O leadframe including passive device |
US7875963B1 (en) | 2008-11-21 | 2011-01-25 | Amkor Technology, Inc. | Semiconductor device including leadframe having power bars and increased I/O |
US7982298B1 (en) | 2008-12-03 | 2011-07-19 | Amkor Technology, Inc. | Package in package semiconductor device |
US8680656B1 (en) | 2009-01-05 | 2014-03-25 | Amkor Technology, Inc. | Leadframe structure for concentrated photovoltaic receiver package |
US20170117214A1 (en) | 2009-01-05 | 2017-04-27 | Amkor Technology, Inc. | Semiconductor device with through-mold via |
US8058715B1 (en) | 2009-01-09 | 2011-11-15 | Amkor Technology, Inc. | Package in package device for RF transceiver module |
US8026589B1 (en) | 2009-02-23 | 2011-09-27 | Amkor Technology, Inc. | Reduced profile stackable semiconductor package |
US7960818B1 (en) | 2009-03-04 | 2011-06-14 | Amkor Technology, Inc. | Conformal shield on punch QFN semiconductor package |
US8575742B1 (en) | 2009-04-06 | 2013-11-05 | Amkor Technology, Inc. | Semiconductor device with increased I/O leadframe including power bars |
US8796561B1 (en) | 2009-10-05 | 2014-08-05 | Amkor Technology, Inc. | Fan out build up substrate stackable package and method |
US8937381B1 (en) | 2009-12-03 | 2015-01-20 | Amkor Technology, Inc. | Thin stackable package and method |
US9691734B1 (en) | 2009-12-07 | 2017-06-27 | Amkor Technology, Inc. | Method of forming a plurality of electronic component packages |
US8324511B1 (en) | 2010-04-06 | 2012-12-04 | Amkor Technology, Inc. | Through via nub reveal method and structure |
US8294276B1 (en) | 2010-05-27 | 2012-10-23 | Amkor Technology, Inc. | Semiconductor device and fabricating method thereof |
US8440554B1 (en) | 2010-08-02 | 2013-05-14 | Amkor Technology, Inc. | Through via connected backside embedded circuit features structure and method |
US8487445B1 (en) | 2010-10-05 | 2013-07-16 | Amkor Technology, Inc. | Semiconductor device having through electrodes protruding from dielectric layer |
US8791501B1 (en) | 2010-12-03 | 2014-07-29 | Amkor Technology, Inc. | Integrated passive device structure and method |
US8674485B1 (en) | 2010-12-08 | 2014-03-18 | Amkor Technology, Inc. | Semiconductor device including leadframe with downsets |
US8390130B1 (en) | 2011-01-06 | 2013-03-05 | Amkor Technology, Inc. | Through via recessed reveal structure and method |
US8648450B1 (en) | 2011-01-27 | 2014-02-11 | Amkor Technology, Inc. | Semiconductor device including leadframe with a combination of leads and lands |
TWI557183B (zh) | 2015-12-16 | 2016-11-11 | 財團法人工業技術研究院 | 矽氧烷組成物、以及包含其之光電裝置 |
US8866278B1 (en) | 2011-10-10 | 2014-10-21 | Amkor Technology, Inc. | Semiconductor device with increased I/O configuration |
US8552548B1 (en) | 2011-11-29 | 2013-10-08 | Amkor Technology, Inc. | Conductive pad on protruding through electrode semiconductor device |
US9704725B1 (en) | 2012-03-06 | 2017-07-11 | Amkor Technology, Inc. | Semiconductor device with leadframe configured to facilitate reduced burr formation |
US9129943B1 (en) | 2012-03-29 | 2015-09-08 | Amkor Technology, Inc. | Embedded component package and fabrication method |
US9048298B1 (en) | 2012-03-29 | 2015-06-02 | Amkor Technology, Inc. | Backside warpage control structure and fabrication method |
JP2013138511A (ja) * | 2013-03-27 | 2013-07-11 | Taiyo Yuden Co Ltd | 弾性波装置 |
KR101486790B1 (ko) | 2013-05-02 | 2015-01-28 | 앰코 테크놀로지 코리아 주식회사 | 강성보강부를 갖는 마이크로 리드프레임 |
US20150075849A1 (en) * | 2013-09-17 | 2015-03-19 | Jia Lin Yap | Semiconductor device and lead frame with interposer |
KR101563911B1 (ko) | 2013-10-24 | 2015-10-28 | 앰코 테크놀로지 코리아 주식회사 | 반도체 패키지 |
US9673122B2 (en) | 2014-05-02 | 2017-06-06 | Amkor Technology, Inc. | Micro lead frame structure having reinforcing portions and method |
CN107946201B (zh) * | 2017-12-19 | 2020-03-31 | 哈尔滨工业大学 | 一种基于局域电沉积的引线键合焊点结构的制备方法 |
CN108054108B (zh) * | 2017-12-19 | 2019-10-25 | 哈尔滨工业大学 | 一种基于快速局域电沉积的引线键合方法 |
KR102646637B1 (ko) * | 2022-12-07 | 2024-03-12 | 주식회사바텍 | 엑스선 소스용 전압변환장치 |
Family Cites Families (29)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS53103659U (de) * | 1977-01-25 | 1978-08-21 | ||
US4176443A (en) * | 1977-03-08 | 1979-12-04 | Sgs-Ates Componenti Elettronici S.P.A. | Method of connecting semiconductor structure to external circuits |
JPS5524479A (en) * | 1978-08-09 | 1980-02-21 | Nec Corp | Semiconductor |
JPS5750056A (en) * | 1980-09-09 | 1982-03-24 | Toshiba Corp | Information processor having branch trace function |
JPS57143848A (en) * | 1981-02-27 | 1982-09-06 | Nec Corp | Semiconductor device |
US4496965A (en) * | 1981-05-18 | 1985-01-29 | Texas Instruments Incorporated | Stacked interdigitated lead frame assembly |
JPS6092636A (ja) * | 1983-10-27 | 1985-05-24 | Toshiba Corp | 半導体装置の製造方法 |
JPS60115247A (ja) * | 1983-11-28 | 1985-06-21 | Fujitsu Ltd | 半導体装置 |
JPS61208245A (ja) * | 1985-03-13 | 1986-09-16 | Kyushu Hitachi Maxell Ltd | 半導体装置のリ−ドフレ−ム製造方法 |
JPS62108534A (ja) * | 1985-11-06 | 1987-05-19 | Nec Corp | 半導体装置 |
US4977441A (en) * | 1985-12-25 | 1990-12-11 | Hitachi, Ltd. | Semiconductor device and tape carrier |
JPH0682705B2 (ja) * | 1986-03-10 | 1994-10-19 | 株式会社東芝 | 半導体装置の実装方法 |
JPS62296431A (ja) * | 1986-06-17 | 1987-12-23 | Alps Electric Co Ltd | フリツプチツプの接続方法 |
JPS6373644A (ja) * | 1986-09-17 | 1988-04-04 | Fujitsu Ltd | 半導体装置の製造方法 |
US4885630A (en) * | 1986-10-27 | 1989-12-05 | Electric Power Research Institute | High power multi-layer semiconductive switching device having multiple parallel contacts with improved forward voltage drop |
US4839713A (en) * | 1987-02-20 | 1989-06-13 | Mitsubishi Denki Kabushiki Kaisha | Package structure for semiconductor device |
JP2623578B2 (ja) * | 1987-07-14 | 1997-06-25 | 日本電気株式会社 | 半導体集積回路装置 |
JPS6473734A (en) * | 1987-09-16 | 1989-03-20 | Nec Corp | Tape carrier |
JPH01207938A (ja) * | 1988-02-15 | 1989-08-21 | Nec Corp | 半導体装置 |
JPH01276750A (ja) * | 1988-04-28 | 1989-11-07 | Matsushita Electric Ind Co Ltd | 半導体装置 |
JPH0233929A (ja) * | 1988-07-23 | 1990-02-05 | Nec Corp | 半導体装置 |
JPH0266953A (ja) * | 1988-08-31 | 1990-03-07 | Nec Corp | 半導体素子の実装構造およびその製造方法 |
US5016082A (en) * | 1988-09-16 | 1991-05-14 | Delco Electronics Corporation | Integrated circuit interconnect design |
JPH0287538A (ja) * | 1988-09-26 | 1990-03-28 | Hitachi Ltd | テープキャリアモジュール |
JP2651608B2 (ja) * | 1988-10-28 | 1997-09-10 | イビデン株式会社 | 電子部品搭載用基板 |
JPH02119252A (ja) * | 1988-10-28 | 1990-05-07 | Nec Corp | 混成集積回路装置 |
US4922322A (en) * | 1989-02-09 | 1990-05-01 | National Semiconductor Corporation | Bump structure for reflow bonding of IC devices |
JPH02208957A (ja) * | 1989-02-09 | 1990-08-20 | Toshiba Corp | 電子機器用封着材料 |
US4948645A (en) * | 1989-08-01 | 1990-08-14 | Rogers Corporation | Tape automated bonding and method of making the same |
-
1990
- 1990-06-01 JP JP2141684A patent/JP2540652B2/ja not_active Expired - Fee Related
-
1991
- 1991-05-31 DE DE69133497T patent/DE69133497T2/de not_active Expired - Fee Related
- 1991-05-31 DE DE69132685T patent/DE69132685T2/de not_active Expired - Fee Related
- 1991-05-31 EP EP91108886A patent/EP0459493B1/de not_active Expired - Lifetime
- 1991-05-31 KR KR1019910009041A patent/KR970000972B1/ko not_active IP Right Cessation
- 1991-05-31 EP EP00103351A patent/EP1020903B1/de not_active Expired - Lifetime
-
1994
- 1994-11-18 US US08/344,605 patent/US5654584A/en not_active Expired - Fee Related
Also Published As
Publication number | Publication date |
---|---|
EP1020903A1 (de) | 2000-07-19 |
US5654584A (en) | 1997-08-05 |
KR920001701A (ko) | 1992-01-30 |
DE69133497D1 (de) | 2006-01-19 |
EP1020903B1 (de) | 2005-12-14 |
EP0459493B1 (de) | 2001-08-16 |
EP0459493A3 (de) | 1994-02-23 |
KR970000972B1 (ko) | 1997-01-21 |
JP2540652B2 (ja) | 1996-10-09 |
EP0459493A2 (de) | 1991-12-04 |
JPH0437149A (ja) | 1992-02-07 |
DE69132685D1 (de) | 2001-09-20 |
DE69132685T2 (de) | 2002-06-13 |
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