DE69130290T2 - Verfahren zur herstellung von halbleitermikrochips - Google Patents

Verfahren zur herstellung von halbleitermikrochips

Info

Publication number
DE69130290T2
DE69130290T2 DE69130290T DE69130290T DE69130290T2 DE 69130290 T2 DE69130290 T2 DE 69130290T2 DE 69130290 T DE69130290 T DE 69130290T DE 69130290 T DE69130290 T DE 69130290T DE 69130290 T2 DE69130290 T2 DE 69130290T2
Authority
DE
Germany
Prior art keywords
pct
insulating layer
holes
sec
date
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE69130290T
Other languages
English (en)
Other versions
DE69130290D1 (de
Inventor
Edward Keible
Nicholas Smith
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Raychem Ltd
Original Assignee
Raychem Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Raychem Ltd filed Critical Raychem Ltd
Publication of DE69130290D1 publication Critical patent/DE69130290D1/de
Application granted granted Critical
Publication of DE69130290T2 publication Critical patent/DE69130290T2/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10Bump connectors ; Manufacturing methods related thereto
    • H01L24/12Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/52Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/532Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
    • H01L23/5329Insulating materials
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
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    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10Bump connectors ; Manufacturing methods related thereto
    • H01L24/11Manufacturing methods
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/11Manufacturing methods
    • H01L2224/1147Manufacturing methods using a lift-off mask
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/12Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001Core members of the bump connector
    • H01L2224/13099Material
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01005Boron [B]
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    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01006Carbon [C]
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    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01013Aluminum [Al]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01015Phosphorus [P]
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    • H01L2924/01Chemical elements
    • H01L2924/01023Vanadium [V]
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    • H01ELECTRIC ELEMENTS
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    • H01L2924/01024Chromium [Cr]
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    • H01L2924/01027Cobalt [Co]
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    • H01L2924/01029Copper [Cu]
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    • H01L2924/01033Arsenic [As]
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    • H01L2924/01044Ruthenium [Ru]
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    • H01L2924/01049Indium [In]
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    • H01L2924/01077Iridium [Ir]
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    • H01L2924/01078Platinum [Pt]
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    • H01L2924/01079Gold [Au]
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    • H01L2924/01082Lead [Pb]
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    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013Alloys
    • H01L2924/014Solder alloys
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    • H01L2924/10Details of semiconductor or other solid state devices to be connected
    • H01L2924/11Device type
    • H01L2924/12Passive devices, e.g. 2 terminal devices
    • H01L2924/1203Rectifying Diode
    • H01L2924/12033Gunn diode
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10Details of semiconductor or other solid state devices to be connected
    • H01L2924/11Device type
    • H01L2924/12Passive devices, e.g. 2 terminal devices
    • H01L2924/1204Optical Diode
    • H01L2924/12042LASER
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10Details of semiconductor or other solid state devices to be connected
    • H01L2924/11Device type
    • H01L2924/14Integrated circuits
    • YGENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10STECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S438/00Semiconductor device manufacturing: process
    • Y10S438/94Laser ablative material removal
DE69130290T 1990-07-18 1991-07-16 Verfahren zur herstellung von halbleitermikrochips Expired - Lifetime DE69130290T2 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
GB909015820A GB9015820D0 (en) 1990-07-18 1990-07-18 Processing microchips
PCT/GB1991/001172 WO1992002038A1 (en) 1990-07-18 1991-07-16 Processing microchips

Publications (2)

Publication Number Publication Date
DE69130290D1 DE69130290D1 (de) 1998-11-05
DE69130290T2 true DE69130290T2 (de) 1999-06-02

Family

ID=10679291

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69130290T Expired - Lifetime DE69130290T2 (de) 1990-07-18 1991-07-16 Verfahren zur herstellung von halbleitermikrochips

Country Status (8)

Country Link
US (1) US5411918A (de)
EP (1) EP0539481B1 (de)
JP (1) JP3091222B2 (de)
AT (1) ATE171813T1 (de)
CA (1) CA2087429A1 (de)
DE (1) DE69130290T2 (de)
GB (1) GB9015820D0 (de)
WO (1) WO1992002038A1 (de)

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US5843363A (en) * 1995-03-31 1998-12-01 Siemens Aktiengesellschaft Ablation patterning of multi-layered structures
US5587342A (en) * 1995-04-03 1996-12-24 Motorola, Inc. Method of forming an electrical interconnect
GB2307785B (en) * 1995-11-29 1998-04-29 Simage Oy Forming contacts on semiconductor substrates for radiation detectors and imaging devices
US6809421B1 (en) * 1996-12-02 2004-10-26 Kabushiki Kaisha Toshiba Multichip semiconductor device, chip therefor and method of formation thereof
US5874369A (en) * 1996-12-05 1999-02-23 International Business Machines Corporation Method for forming vias in a dielectric film
US6008070A (en) * 1998-05-21 1999-12-28 Micron Technology, Inc. Wafer level fabrication and assembly of chip scale packages
US6627998B1 (en) * 2000-07-27 2003-09-30 International Business Machines Corporation Wafer scale thin film package
US6521485B2 (en) * 2001-01-17 2003-02-18 Walsin Advanced Electronics Ltd Method for manufacturing wafer level chip size package
CN1287945C (zh) * 2001-03-22 2006-12-06 埃克赛尔技术有限公司 激光加工系统和方法
JP4672199B2 (ja) * 2001-07-10 2011-04-20 富士通株式会社 電気的相互接続方法
TW533188B (en) * 2001-07-20 2003-05-21 Getters Spa Support for microelectronic, microoptoelectronic or micromechanical devices
US7361171B2 (en) 2003-05-20 2008-04-22 Raydiance, Inc. Man-portable optical ablation system
US7115514B2 (en) * 2003-10-02 2006-10-03 Raydiance, Inc. Semiconductor manufacturing using optical ablation
US8921733B2 (en) 2003-08-11 2014-12-30 Raydiance, Inc. Methods and systems for trimming circuits
US9022037B2 (en) 2003-08-11 2015-05-05 Raydiance, Inc. Laser ablation method and apparatus having a feedback loop and control unit
US8173929B1 (en) 2003-08-11 2012-05-08 Raydiance, Inc. Methods and systems for trimming circuits
US20050167405A1 (en) * 2003-08-11 2005-08-04 Richard Stoltz Optical ablation using material composition analysis
US20050253245A1 (en) * 2004-05-12 2005-11-17 Mark Lynch Package design and method for electrically connecting die to package
US7575999B2 (en) * 2004-09-01 2009-08-18 Micron Technology, Inc. Method for creating conductive elements for semiconductor device structures using laser ablation processes and methods of fabricating semiconductor device assemblies
US9929080B2 (en) * 2004-11-15 2018-03-27 Intel Corporation Forming a stress compensation layer and structures formed thereby
US8135050B1 (en) 2005-07-19 2012-03-13 Raydiance, Inc. Automated polarization correction
US8232687B2 (en) 2006-04-26 2012-07-31 Raydiance, Inc. Intelligent laser interlock system
US7444049B1 (en) 2006-01-23 2008-10-28 Raydiance, Inc. Pulse stretcher and compressor including a multi-pass Bragg grating
US8189971B1 (en) 2006-01-23 2012-05-29 Raydiance, Inc. Dispersion compensation in a chirped pulse amplification system
TWI287273B (en) * 2006-01-25 2007-09-21 Advanced Semiconductor Eng Three dimensional package and method of making the same
TWI293499B (en) 2006-01-25 2008-02-11 Advanced Semiconductor Eng Three dimensional package and method of making the same
US7822347B1 (en) 2006-03-28 2010-10-26 Raydiance, Inc. Active tuning of temporal dispersion in an ultrashort pulse laser system
CN102149509B (zh) * 2008-07-09 2014-08-20 Fei公司 用于激光加工的方法和设备
US8125704B2 (en) 2008-08-18 2012-02-28 Raydiance, Inc. Systems and methods for controlling a pulsed laser by combining laser signals
EP2200412A1 (de) 2008-12-17 2010-06-23 Nederlandse Organisatie voor toegepast-natuurwetenschappelijk Onderzoek TNO Flexibles elektronisches Produkt und Verfahren zu dessen Herstellung
KR101023296B1 (ko) * 2009-11-09 2011-03-18 삼성전기주식회사 포스트 범프 형성방법
JP5609186B2 (ja) * 2010-03-18 2014-10-22 株式会社リコー トナー担持体、現像装置及び画像形成装置
WO2012021748A1 (en) 2010-08-12 2012-02-16 Raydiance, Inc. Polymer tubing laser micromachining
WO2012037468A1 (en) 2010-09-16 2012-03-22 Raydiance, Inc. Singulation of layered materials using selectively variable laser output
US9070851B2 (en) 2010-09-24 2015-06-30 Seoul Semiconductor Co., Ltd. Wafer-level light emitting diode package and method of fabricating the same
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CN111508926B (zh) 2019-01-31 2022-08-30 奥特斯(中国)有限公司 一种部件承载件以及制造部件承载件的方法

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Also Published As

Publication number Publication date
ATE171813T1 (de) 1998-10-15
DE69130290D1 (de) 1998-11-05
WO1992002038A1 (en) 1992-02-06
EP0539481A1 (de) 1993-05-05
JP3091222B2 (ja) 2000-09-25
US5411918A (en) 1995-05-02
CA2087429A1 (en) 1992-01-19
EP0539481B1 (de) 1998-09-30
GB9015820D0 (en) 1990-09-05
JPH05509441A (ja) 1993-12-22

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