DE69129565T2 - Hochleistungsfähiger Emulator mit Pipelining - Google Patents
Hochleistungsfähiger Emulator mit PipeliningInfo
- Publication number
- DE69129565T2 DE69129565T2 DE69129565T DE69129565T DE69129565T2 DE 69129565 T2 DE69129565 T2 DE 69129565T2 DE 69129565 T DE69129565 T DE 69129565T DE 69129565 T DE69129565 T DE 69129565T DE 69129565 T2 DE69129565 T2 DE 69129565T2
- Authority
- DE
- Germany
- Prior art keywords
- pipelining
- high performance
- emulator
- performance emulator
- performance
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/38—Concurrent instruction execution, e.g. pipeline, look ahead
- G06F9/3802—Instruction prefetching
- G06F9/3804—Instruction prefetching for branches, e.g. hedging, branch folding
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/3017—Runtime instruction translation, e.g. macros
- G06F9/30174—Runtime instruction translation, e.g. macros for non-native instruction set, e.g. Javabyte, legacy code
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/38—Concurrent instruction execution, e.g. pipeline, look ahead
- G06F9/3877—Concurrent instruction execution, e.g. pipeline, look ahead using a slave processor, e.g. coprocessor
- G06F9/3879—Concurrent instruction execution, e.g. pipeline, look ahead using a slave processor, e.g. coprocessor for non-native instruction execution, e.g. executing a command; for Java instruction set
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US07/546,348 US5430862A (en) | 1990-06-29 | 1990-06-29 | Emulation of CISC instructions by RISC instructions using two pipelined stages for overlapped CISC decoding and RISC execution |
Publications (2)
Publication Number | Publication Date |
---|---|
DE69129565D1 DE69129565D1 (de) | 1998-07-16 |
DE69129565T2 true DE69129565T2 (de) | 1999-03-18 |
Family
ID=24180022
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
DE69129565T Expired - Fee Related DE69129565T2 (de) | 1990-06-29 | 1991-06-20 | Hochleistungsfähiger Emulator mit Pipelining |
Country Status (4)
Country | Link |
---|---|
US (1) | US5430862A (de) |
EP (1) | EP0464494B1 (de) |
CA (1) | CA2041507C (de) |
DE (1) | DE69129565T2 (de) |
Families Citing this family (51)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5438668A (en) * | 1992-03-31 | 1995-08-01 | Seiko Epson Corporation | System and method for extraction, alignment and decoding of CISC instructions into a nano-instruction bucket for execution by a RISC computer |
US5848289A (en) * | 1992-11-27 | 1998-12-08 | Motorola, Inc. | Extensible central processing unit |
JP3210466B2 (ja) * | 1993-02-25 | 2001-09-17 | 株式会社リコー | Cpuコア、該cpuコアを有するasic、及び該asicを備えたエミュレーションシステム |
JP3248992B2 (ja) * | 1993-07-13 | 2002-01-21 | 富士通株式会社 | マルチプロセッサ |
US5392408A (en) * | 1993-09-20 | 1995-02-21 | Apple Computer, Inc. | Address selective emulation routine pointer address mapping system |
US5574887A (en) * | 1993-09-20 | 1996-11-12 | Apple Computer, Inc. | Apparatus and method for emulation routine pointer prefetch |
US5408622A (en) * | 1993-09-23 | 1995-04-18 | Apple Computer, Inc. | Apparatus and method for emulation routine control transfer via host jump instruction creation and insertion |
US5574927A (en) * | 1994-03-25 | 1996-11-12 | International Meta Systems, Inc. | RISC architecture computer configured for emulation of the instruction set of a target computer |
JPH08339298A (ja) * | 1995-02-02 | 1996-12-24 | Ricoh Co Ltd | マイクロプロセッサにおける命令追加方法及びそれを用いたマイクロプロセッサ |
US5758141A (en) * | 1995-02-10 | 1998-05-26 | International Business Machines Corporation | Method and system for selective support of non-architected instructions within a superscaler processor system utilizing a special access bit within a machine state register |
JP3451595B2 (ja) * | 1995-06-07 | 2003-09-29 | インターナショナル・ビジネス・マシーンズ・コーポレーション | 二つの別個の命令セット・アーキテクチャへの拡張をサポートすることができるアーキテクチャ・モード制御を備えたマイクロプロセッサ |
WO1997005546A1 (en) * | 1995-08-01 | 1997-02-13 | Bull Hn Information Systems Inc. | Method for emulating program instructions |
US5678032A (en) * | 1995-09-06 | 1997-10-14 | Bull Hn Information Systems Inc. | Method of optimizing the execution of program instuctions by an emulator using a plurality of execution units |
US5854909A (en) * | 1995-09-29 | 1998-12-29 | Intel Corporation | Test and control access architecture for an integrated circuit |
US5790825A (en) * | 1995-11-08 | 1998-08-04 | Apple Computer, Inc. | Method for emulating guest instructions on a host computer through dynamic recompilation of host instructions |
US5784638A (en) * | 1996-02-22 | 1998-07-21 | International Business Machines Corporation | Computer system supporting control transfers between two architectures |
US5896522A (en) * | 1996-12-31 | 1999-04-20 | Unisys Corporation | Selective emulation interpretation using transformed instructions |
US5898850A (en) * | 1997-03-31 | 1999-04-27 | International Business Machines Corporation | Method and system for executing a non-native mode-sensitive instruction within a computer system |
TW384445B (en) * | 1997-04-11 | 2000-03-11 | Ibm | Method for bursting processor data to or from an I/O device |
US5930491A (en) * | 1997-06-18 | 1999-07-27 | International Business Machines Corporation | Identification of related instructions resulting from external to internal translation by use of common ID field for each group |
JP4018158B2 (ja) * | 1997-10-02 | 2007-12-05 | コーニンクレッカ フィリップス エレクトロニクス エヌ ヴィ | 可変命令セットコンピュータ |
US6067601A (en) * | 1997-11-03 | 2000-05-23 | Brecis Communications | Cache memory based instruction execution |
US5940626A (en) * | 1997-11-03 | 1999-08-17 | Teragen Corporation | Processor having an instruction set architecture implemented with hierarchically organized primitive operations |
US5923894A (en) | 1997-11-03 | 1999-07-13 | Teragen Corporation | Adaptable input/output pin control |
US6438679B1 (en) | 1997-11-03 | 2002-08-20 | Brecis Communications | Multiple ISA support by a processor using primitive operations |
US6016539A (en) | 1997-11-03 | 2000-01-18 | Teragen Corporation | Datapath control logic for processors having instruction set architectures implemented with hierarchically organized primitive operations |
US6178482B1 (en) | 1997-11-03 | 2001-01-23 | Brecis Communications | Virtual register sets |
US6216218B1 (en) | 1997-11-03 | 2001-04-10 | Donald L. Sollars | Processor having a datapath and control logic constituted with basis execution blocks |
US6041402A (en) * | 1998-01-05 | 2000-03-21 | Trw Inc. | Direct vectored legacy instruction set emulation |
US6546479B1 (en) * | 1998-02-10 | 2003-04-08 | Koninklijke Philips Electronics N.V. | Reduced instruction fetch latency in a system including a pipelined processor |
US6668242B1 (en) | 1998-09-25 | 2003-12-23 | Infineon Technologies North America Corp. | Emulator chip package that plugs directly into the target system |
US7225436B1 (en) | 1998-12-08 | 2007-05-29 | Nazomi Communications Inc. | Java hardware accelerator using microcode engine |
US20050149694A1 (en) * | 1998-12-08 | 2005-07-07 | Mukesh Patel | Java hardware accelerator using microcode engine |
US6332215B1 (en) | 1998-12-08 | 2001-12-18 | Nazomi Communications, Inc. | Java virtual machine hardware for RISC and CISC processors |
US6826749B2 (en) | 1998-12-08 | 2004-11-30 | Nazomi Communications, Inc. | Java hardware accelerator using thread manager |
US6314557B1 (en) | 1998-12-14 | 2001-11-06 | Infineon Technologies Development Center Tel Aviv Ltd | Hybrid computer programming environment |
DE19905510A1 (de) * | 1999-02-10 | 2000-08-31 | Siemens Ag | Mikroprozessor und Verfahren zur Adressierung in einem Mikroprozessor |
GB2365546B (en) | 1999-12-23 | 2004-02-18 | St Microelectronics Sa | A computer system with two debug watch modes |
GB2362730B (en) | 1999-12-23 | 2004-02-11 | St Microelectronics Sa | Computer register watch |
GB2362729B (en) * | 1999-12-23 | 2004-02-11 | St Microelectronics Sa | Memory access debug facility |
GB2366006B (en) * | 1999-12-23 | 2004-06-30 | St Microelectronics Sa | A computer system with debug facility |
GB2362968B (en) * | 1999-12-23 | 2003-12-10 | St Microelectronics Sa | Computer system with debug facility |
KR20020028814A (ko) * | 2000-10-10 | 2002-04-17 | 나조미 커뮤니케이션즈, 인코포레이티드 | 마이크로코드 엔진을 이용한 자바 하드웨어 가속기 |
US7149878B1 (en) * | 2000-10-30 | 2006-12-12 | Mips Technologies, Inc. | Changing instruction set architecture mode by comparison of current instruction execution address with boundary address register values |
US7107439B2 (en) * | 2001-08-10 | 2006-09-12 | Mips Technologies, Inc. | System and method of controlling software decompression through exceptions |
US8769508B2 (en) | 2001-08-24 | 2014-07-01 | Nazomi Communications Inc. | Virtual machine hardware for RISC and CISC processors |
US7802080B2 (en) * | 2004-03-24 | 2010-09-21 | Arm Limited | Null exception handling |
GB2426083A (en) * | 2005-05-09 | 2006-11-15 | Sony Comp Entertainment Europe | Software emulation of a pipeline processor |
US20060294443A1 (en) * | 2005-06-03 | 2006-12-28 | Khaled Fekih-Romdhane | On-chip address generation |
US9026424B1 (en) * | 2008-10-27 | 2015-05-05 | Juniper Networks, Inc. | Emulation of multiple instruction sets |
CN116450570B (zh) * | 2023-06-19 | 2023-10-17 | 先进能源科学与技术广东省实验室 | 基于fpga的32位risc-v处理器及电子设备 |
Family Cites Families (22)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US3766532A (en) * | 1972-04-28 | 1973-10-16 | Nanodata Corp | Data processing system having two levels of program control |
FR2269150B1 (de) * | 1974-04-25 | 1977-10-28 | Honeywell Bull Soc Ind | |
US4307445A (en) * | 1978-11-17 | 1981-12-22 | Motorola, Inc. | Microprogrammed control apparatus having a two-level control store for data processor |
US4415969A (en) * | 1980-02-07 | 1983-11-15 | Intel Corporation | Macroinstruction translator unit for use in a microprocessor |
US4514803A (en) * | 1982-04-26 | 1985-04-30 | International Business Machines Corporation | Methods for partitioning mainframe instruction sets to implement microprocessor based emulation thereof |
EP0124517A1 (de) * | 1982-10-22 | 1984-11-14 | International Business Machines Corporation | Beschleunigte befehlsabbildung äusserer quellen- und zielbefehlsströme für fast-echtzeitinjektion in die letzte |
US4633417A (en) * | 1984-06-20 | 1986-12-30 | Step Engineering | Emulator for non-fixed instruction set VLSI devices |
JPS61229133A (ja) * | 1985-04-03 | 1986-10-13 | Nec Corp | シングルチツプマイクロコンピユ−タ用エミユレ−タ |
US4720780A (en) * | 1985-09-17 | 1988-01-19 | The Johns Hopkins University | Memory-linked wavefront array processor |
JPS6286407A (ja) * | 1985-10-11 | 1987-04-20 | Omron Tateisi Electronics Co | プログラマブル・コントロ−ラ |
US5070475A (en) * | 1985-11-14 | 1991-12-03 | Data General Corporation | Floating point unit interface |
JPH0744567B2 (ja) * | 1986-08-27 | 1995-05-15 | 日産自動車株式会社 | 通信インタ−フエイス装置 |
US4972317A (en) * | 1986-10-06 | 1990-11-20 | International Business Machines Corp. | Microprocessor implemented data processing system capable of emulating execution of special instructions not within the established microprocessor instruction set by switching access from a main store portion of a memory |
US4841476A (en) * | 1986-10-06 | 1989-06-20 | International Business Machines Corporation | Extended floating point operations supporting emulation of source instruction execution |
US4821183A (en) * | 1986-12-04 | 1989-04-11 | International Business Machines Corporation | A microsequencer circuit with plural microprogrom instruction counters |
US4992934A (en) * | 1986-12-15 | 1991-02-12 | United Technologies Corporation | Reduced instruction set computing apparatus and methods |
CA1278382C (en) * | 1986-12-15 | 1990-12-27 | Brian J. Sprague | Reduced instruction set computing apparatus and methods |
JPH0810437B2 (ja) * | 1987-05-11 | 1996-01-31 | 株式会社日立製作所 | 仮想計算機システムのゲスト実行制御方式 |
US4862407A (en) * | 1987-10-05 | 1989-08-29 | Motorola, Inc. | Digital signal processing apparatus |
US5019967A (en) * | 1988-07-20 | 1991-05-28 | Digital Equipment Corporation | Pipeline bubble compression in a computer system |
US5046190A (en) * | 1988-09-06 | 1991-09-03 | Allen-Bradley Company, Inc. | Pipeline image processor |
US5293592A (en) * | 1989-04-07 | 1994-03-08 | Intel Corporatino | Decoder for pipelined system having portion indicating type of address generation and other portion controlling address generation within pipeline |
-
1990
- 1990-06-29 US US07/546,348 patent/US5430862A/en not_active Expired - Lifetime
-
1991
- 1991-04-30 CA CA002041507A patent/CA2041507C/en not_active Expired - Fee Related
- 1991-06-20 DE DE69129565T patent/DE69129565T2/de not_active Expired - Fee Related
- 1991-06-20 EP EP91110177A patent/EP0464494B1/de not_active Expired - Lifetime
Also Published As
Publication number | Publication date |
---|---|
EP0464494A2 (de) | 1992-01-08 |
CA2041507C (en) | 1999-04-06 |
DE69129565D1 (de) | 1998-07-16 |
EP0464494B1 (de) | 1998-06-10 |
CA2041507A1 (en) | 1991-12-30 |
EP0464494A3 (en) | 1993-12-08 |
US5430862A (en) | 1995-07-04 |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
8364 | No opposition during term of opposition | ||
8339 | Ceased/non-payment of the annual fee |