DE69128678D1 - Verfahren zum selektiven epitaxialen Wachstum und Ätzen von III-V oder II-VI-Halbleitern in demselben Wachstumsapparat - Google Patents

Verfahren zum selektiven epitaxialen Wachstum und Ätzen von III-V oder II-VI-Halbleitern in demselben Wachstumsapparat

Info

Publication number
DE69128678D1
DE69128678D1 DE69128678T DE69128678T DE69128678D1 DE 69128678 D1 DE69128678 D1 DE 69128678D1 DE 69128678 T DE69128678 T DE 69128678T DE 69128678 T DE69128678 T DE 69128678T DE 69128678 D1 DE69128678 D1 DE 69128678D1
Authority
DE
Germany
Prior art keywords
semiconductors
etching
iii
selective epitaxial
epitaxial growth
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE69128678T
Other languages
English (en)
Other versions
DE69128678T2 (de
Inventor
Rosette Azoulay
Louis Dugrand
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Orange SA
Original Assignee
France Telecom SA
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by France Telecom SA filed Critical France Telecom SA
Application granted granted Critical
Publication of DE69128678D1 publication Critical patent/DE69128678D1/de
Publication of DE69128678T2 publication Critical patent/DE69128678T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02612—Formation types
    • H01L21/02617—Deposition types
    • H01L21/02636—Selective deposition, e.g. simultaneous growth of mono- and non-monocrystalline semiconductor materials
    • H01L21/02639—Preparation of substrate for selective deposition
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02367—Substrates
    • H01L21/0237—Materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02367—Substrates
    • H01L21/0237—Materials
    • H01L21/02387—Group 13/15 materials
    • H01L21/02395—Arsenides
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02518—Deposited layers
    • H01L21/02521—Materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02518—Deposited layers
    • H01L21/02521—Materials
    • H01L21/02538—Group 13/15 materials
    • H01L21/02546—Arsenides
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02612—Formation types
    • H01L21/02617—Deposition types
    • H01L21/0262—Reduction or decomposition of gaseous compounds, e.g. CVD
DE69128678T 1990-09-20 1991-09-18 Verfahren zum selektiven epitaxialen Wachstum und Ätzen von III-V oder II-VI-Halbleitern in demselben Wachstumsapparat Expired - Fee Related DE69128678T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
FR9011615A FR2667197B1 (fr) 1990-09-20 1990-09-20 Procede d'epitaxie selective et de gravure de materiau iii-v ou ii-vi dans un meme bati de croissance omcvd.

Publications (2)

Publication Number Publication Date
DE69128678D1 true DE69128678D1 (de) 1998-02-19
DE69128678T2 DE69128678T2 (de) 1998-07-23

Family

ID=9400488

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69128678T Expired - Fee Related DE69128678T2 (de) 1990-09-20 1991-09-18 Verfahren zum selektiven epitaxialen Wachstum und Ätzen von III-V oder II-VI-Halbleitern in demselben Wachstumsapparat

Country Status (5)

Country Link
US (1) US5212113A (de)
EP (1) EP0477096B1 (de)
JP (1) JPH0629215A (de)
DE (1) DE69128678T2 (de)
FR (1) FR2667197B1 (de)

Families Citing this family (21)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO1993001614A1 (en) * 1991-07-05 1993-01-21 Mitsubishi Kasei Corporation Compound semiconductor and manufacturing method therefor
US5827365A (en) * 1991-07-05 1998-10-27 Mitsubishi Kasei Corporation Compound semiconductor and its fabrication
BE1006865A6 (nl) * 1992-04-29 1995-01-10 Imec Inter Uni Micro Electr Werkwijze voor het fabriceren van opto-electronische componenten.
JP3444610B2 (ja) * 1992-09-29 2003-09-08 三菱化学株式会社 半導体レーザ装置
DE4421539C2 (de) * 1993-06-22 2001-03-22 Mitsubishi Chem Corp Verfahren zur Herstellung eines Halbleiters aus einer Verbindung der Gruppe II-VI
JP2822868B2 (ja) * 1993-12-10 1998-11-11 日本電気株式会社 半導体レーザの製造方法
JP3330218B2 (ja) * 1994-03-25 2002-09-30 三菱電機株式会社 半導体装置の製造方法，及び半導体装置
JP3729210B2 (ja) * 1994-07-26 2005-12-21 富士通株式会社 半導体装置の製造方法
US5818078A (en) * 1994-08-29 1998-10-06 Fujitsu Limited Semiconductor device having a regrowth crystal region
FR2761811B1 (fr) * 1997-04-03 1999-07-16 France Telecom Technologie sans gravure pour integration de composants
WO1999052647A1 (en) 1998-04-16 1999-10-21 The University Of New Mexico Non-planar micro-optical structures
US20090087967A1 (en) * 2005-11-14 2009-04-02 Todd Michael A Precursors and processes for low temperature selective epitaxial growth
EP1965416A3 (de) * 2005-12-22 2009-04-29 Freiberger Compound Materials GmbH Freistehende III-N-Schichten oder Vorrichtungen, die durch selektive Maskierung von III-N-Schichten während des III-N-Schichtenwachstums erhalten werden
PL2122015T3 (pl) * 2006-12-08 2012-07-31 Saint Gobain Cristaux & Detecteurs Sposób wytwarzania monokryształu azotku przez wzrost epitaksjalny na podłożu zapobiegającym wzrostowi na krawędziach podłoża
CN102474000B (zh) 2009-12-24 2015-07-22 株式会社村田制作所 天线及便携终端
US8603898B2 (en) * 2012-03-30 2013-12-10 Applied Materials, Inc. Method for forming group III/V conformal layers on silicon substrates
US9941295B2 (en) 2015-06-08 2018-04-10 Sandisk Technologies Llc Method of making a three-dimensional memory device having a heterostructure quantum well channel
US9425299B1 (en) 2015-06-08 2016-08-23 Sandisk Technologies Llc Three-dimensional memory device having a heterostructure quantum well channel
US9941363B2 (en) 2015-12-18 2018-04-10 International Business Machines Corporation III-V transistor device with self-aligned doped bottom barrier
US9721963B1 (en) 2016-04-08 2017-08-01 Sandisk Technologies Llc Three-dimensional memory device having a transition metal dichalcogenide channel
US9818801B1 (en) 2016-10-14 2017-11-14 Sandisk Technologies Llc Resistive three-dimensional memory device with heterostructure semiconductor local bit line and method of making thereof

Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE1444502B2 (de) * 1963-08-01 1970-01-08 IBM Deutschland Internationale Büro-Maschinen OmbH, 7032 Sindelfingen Verfahren zur Regelung der Schärfe von an Galliumarsenid-Einkristallen zu bildenden pn-übergängen
US4368098A (en) * 1969-10-01 1983-01-11 Rockwell International Corporation Epitaxial composite and method of making
US4488914A (en) * 1982-10-29 1984-12-18 The United States Of America As Represented By The Secretary Of The Air Force Process for the epitaxial deposition of III-V compounds utilizing a continuous in-situ hydrogen chloride etch
GB2162207B (en) * 1984-07-26 1989-05-10 Japan Res Dev Corp Semiconductor crystal growth apparatus
DE3726971A1 (de) * 1987-08-13 1989-02-23 Standard Elektrik Lorenz Ag Methode zur herstellung planarer epitaxieschichten mittels selektiver metallorganischer gasphasenepitaxie (movpe)
EP0305144A3 (de) * 1987-08-24 1989-03-08 Canon Kabushiki Kaisha Verfahren zur Herstellung einer Vebindungshalbleiterkristallschicht
JPH01175727A (ja) * 1987-12-29 1989-07-12 Nec Corp ３−ｖ族化合物半導体の選択埋め込み成長方法
US5103271A (en) * 1989-09-28 1992-04-07 Kabushiki Kaisha Toshiba Semiconductor light emitting device and method of fabricating the same

Also Published As

Publication number Publication date
FR2667197B1 (fr) 1993-12-24
DE69128678T2 (de) 1998-07-23
EP0477096A1 (de) 1992-03-25
EP0477096B1 (de) 1998-01-14
FR2667197A1 (fr) 1992-03-27
US5212113A (en) 1993-05-18
JPH0629215A (ja) 1994-02-04

Similar Documents

Publication Publication Date Title
DE69128678D1 (de) Verfahren zum selektiven epitaxialen Wachstum und Ätzen von III-V oder II-VI-Halbleitern in demselben Wachstumsapparat
DE69511995T2 (de) Verfahren zum züchten von galliumnitridhalbleiterkristallen und vorrichtung
DE3886023D1 (de) Verfahren und Vorrichtung zum Atomschicht-Epitaxie-Aufwachsen.
DE69024077T2 (de) Einrichtung und Verfahren zur Behandlung von Halbleiterscheiben
DE59107982D1 (de) Verfahren und Vorrichtung zum Halten und Transportieren von plattenförmigen Substraten
DE3681074D1 (de) Gasgemische und verfahren zum niederschlag von amorphen halbleitern.
KR880701454A (ko) 반도체 웨이퍼 세정 방법 및 장치
DE3854111T2 (de) Vorrichtung und verfahren zur behandlung mit plasma.
DE69615603D1 (de) Vorrichtung und Verfahren zum Reinigen von Halbleiterplättchen
DE68918049T2 (de) Verfahren und Vorrichtung zur epitaktischen Züchtung.
DE69509561T2 (de) Verfahren und Vorrichtung zum Abfasen von Halbleiterscheiben
DE69120193D1 (de) Batchverfahren und Vorrichtung zur Behandlung von Halbleiterscheiben
DE3863887D1 (de) Verfahren zum zuechten von homogenen kristallen und vorrichtung zur durchfuehrung des verfahrens.
DE59206795D1 (de) Verfahren und Vorrichtung zum einseitigen Behandeln von plattenförmigen Gegenständen
DE69307157T2 (de) Methode und Vorrichtung zum Polieren der Rundkanten von Wafern
DE69228271D1 (de) Vorrichtung und Verfahren zum Schälen von frischen Früchten
DE68916157D1 (de) Vorrichtung und Verfahren zur Züchtung von Kristallen aus Halbleitermaterialien.
DE3781535D1 (de) Verfahren und vorrichtung zur aseptischen behandlung von lebensmitteln.
DE69115234D1 (de) Verfahren und Vorrichtung zur Handhabung von Wafern.
DE3878990D1 (de) Vorrichtung und verfahren zur zuechtung von kristallen aus halbleitermaterialien.
DE69128822D1 (de) Verfahren und Vorrichtung für den Transport von Halbleitersubstraten in einem Verarbeitungssystem für Halbleiter
DE69324069D1 (de) Verfahren und Vorrichtung zur Nasschemische Behandlung von Halbleiterscheiben und andere gegenstände
DE3774864D1 (de) Verfahren und vorrichtung zum transportieren von artikeln.
DE69131983T2 (de) Verfahren und vorrichtung zum herstellen von einkristallhalbleitern mit hohem spaltdissoranteil
DE68901566D1 (de) Verfahren und vorrichtung zum spalten von siliciumwafern.

Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee