DE69126596T2 - BiCMOS-Verfahren mit Bipolartransistoren mit geringem Basis-Rekombinationsstrom - Google Patents
BiCMOS-Verfahren mit Bipolartransistoren mit geringem Basis-RekombinationsstromInfo
- Publication number
- DE69126596T2 DE69126596T2 DE69126596T DE69126596T DE69126596T2 DE 69126596 T2 DE69126596 T2 DE 69126596T2 DE 69126596 T DE69126596 T DE 69126596T DE 69126596 T DE69126596 T DE 69126596T DE 69126596 T2 DE69126596 T2 DE 69126596T2
- Authority
- DE
- Germany
- Prior art keywords
- bipolar transistors
- low base
- recombination current
- base recombination
- bicmos method
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
- H01L27/06—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/74—Making of localized buried regions, e.g. buried collector layers, internal connections substrate contacts
- H01L21/743—Making of internal connections, substrate contacts
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8248—Combination of bipolar and field-effect technology
- H01L21/8249—Bipolar and MOS technology
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10S148/00—Metal treatment
- Y10S148/009—Bi-MOS
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10S148/00—Metal treatment
- Y10S148/01—Bipolar transistors-ion implantation
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US61319190A | 1990-11-14 | 1990-11-14 |
Publications (2)
Publication Number | Publication Date |
---|---|
DE69126596D1 DE69126596D1 (de) | 1997-07-24 |
DE69126596T2 true DE69126596T2 (de) | 1997-10-02 |
Family
ID=24456251
Family Applications (2)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
DE69126596T Expired - Lifetime DE69126596T2 (de) | 1990-11-14 | 1991-08-13 | BiCMOS-Verfahren mit Bipolartransistoren mit geringem Basis-Rekombinationsstrom |
DE69133446T Expired - Lifetime DE69133446T2 (de) | 1990-11-14 | 1991-08-13 | BiCMOS-Verfahren mit Bipolartransistor mit geringem Basis-Rekombinationsstrom |
Family Applications After (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
DE69133446T Expired - Lifetime DE69133446T2 (de) | 1990-11-14 | 1991-08-13 | BiCMOS-Verfahren mit Bipolartransistor mit geringem Basis-Rekombinationsstrom |
Country Status (5)
Country | Link |
---|---|
US (2) | US5304501A (de) |
EP (2) | EP0486134B1 (de) |
JP (1) | JPH073813B2 (de) |
KR (1) | KR950010287B1 (de) |
DE (2) | DE69126596T2 (de) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
DE10008032A1 (de) * | 2000-02-15 | 2001-09-13 | Infineon Technologies Ag | Verfahren zum Herstellen eines CMOS-kompatiblen Photosensors |
Families Citing this family (16)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5444004A (en) * | 1994-04-13 | 1995-08-22 | Winbond Electronics Corporation | CMOS process compatible self-alignment lateral bipolar junction transistor |
US5434096A (en) * | 1994-10-05 | 1995-07-18 | Taiwan Semiconductor Manufacturing Company Ltd. | Method to prevent silicide bubble in the VLSI process |
JPH08172139A (ja) * | 1994-12-19 | 1996-07-02 | Sony Corp | 半導体装置製造方法 |
TW389944B (en) * | 1997-03-17 | 2000-05-11 | United Microelectronics Corp | Method for forming gate oxide layers with different thickness |
US6251794B1 (en) * | 1999-02-18 | 2001-06-26 | Taiwan Semiconductor Manufacturing Company | Method and apparatus with heat treatment for stripping photoresist to eliminate post-strip photoresist extrusion defects |
US6245609B1 (en) * | 1999-09-27 | 2001-06-12 | Taiwan Semiconductor Manufacturing Company | High voltage transistor using P+ buried layer |
US6448124B1 (en) * | 1999-11-12 | 2002-09-10 | International Business Machines Corporation | Method for epitaxial bipolar BiCMOS |
US6483156B1 (en) * | 2000-03-16 | 2002-11-19 | International Business Machines Corporation | Double planar gated SOI MOSFET structure |
US7214593B2 (en) * | 2001-02-01 | 2007-05-08 | International Business Machines Corporation | Passivation for improved bipolar yield |
JP2004079953A (ja) * | 2002-08-22 | 2004-03-11 | Nec Electronics Corp | 半導体装置の製造方法 |
US6780695B1 (en) * | 2003-04-18 | 2004-08-24 | International Business Machines Corporation | BiCMOS integration scheme with raised extrinsic base |
WO2012139633A1 (en) | 2011-04-12 | 2012-10-18 | X-Fab Semiconductor Foundries Ag | Bipolar transistor with gate electrode over the emitter base junction |
US10213745B2 (en) | 2011-12-22 | 2019-02-26 | Refine Technology, Llc | Hollow fiber cartridges and components and methods of their construction |
US9001530B2 (en) * | 2012-06-29 | 2015-04-07 | Finisar Corporation | Integrated circuit with voltage conversion |
CN109309006B (zh) * | 2017-07-27 | 2021-10-15 | 中芯国际集成电路制造(上海)有限公司 | 半导体器件及其形成方法 |
CN108115277B (zh) * | 2018-01-31 | 2020-07-07 | 湖南振邦氢能科技有限公司 | 一种金属双极板活性区激光焊接方法 |
Family Cites Families (11)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS6080267A (ja) * | 1983-10-07 | 1985-05-08 | Toshiba Corp | 半導体集積回路装置の製造方法 |
JPH0628296B2 (ja) * | 1985-10-17 | 1994-04-13 | 日本電気株式会社 | 半導体装置の製造方法 |
US4752589A (en) * | 1985-12-17 | 1988-06-21 | Siemens Aktiengesellschaft | Process for the production of bipolar transistors and complementary MOS transistors on a common silicon substrate |
JPS63133662A (ja) * | 1986-11-26 | 1988-06-06 | Nec Corp | 半導体装置の製造方法 |
US4902640A (en) * | 1987-04-17 | 1990-02-20 | Tektronix, Inc. | High speed double polycide bipolar/CMOS integrated circuit process |
US5179031A (en) * | 1988-01-19 | 1993-01-12 | National Semiconductor Corporation | Method of manufacturing a polysilicon emitter and a polysilicon gate using the same etch of polysilicon on a thin gate oxide |
JPH0348457A (ja) * | 1989-04-14 | 1991-03-01 | Toshiba Corp | 半導体装置およびその製造方法 |
JP3024143B2 (ja) * | 1989-06-19 | 2000-03-21 | ソニー株式会社 | 半導体装置の製法 |
JPH03198371A (ja) * | 1989-12-27 | 1991-08-29 | Oki Electric Ind Co Ltd | 半導体装置の製造方法 |
US5104817A (en) * | 1990-03-20 | 1992-04-14 | Texas Instruments Incorporated | Method of forming bipolar transistor with integral base emitter load resistor |
US4987089A (en) * | 1990-07-23 | 1991-01-22 | Micron Technology, Inc. | BiCMOS process and process for forming bipolar transistors on wafers also containing FETs |
-
1991
- 1991-08-13 EP EP91307467A patent/EP0486134B1/de not_active Expired - Lifetime
- 1991-08-13 DE DE69126596T patent/DE69126596T2/de not_active Expired - Lifetime
- 1991-08-13 EP EP96117990A patent/EP0768709B1/de not_active Expired - Lifetime
- 1991-08-13 DE DE69133446T patent/DE69133446T2/de not_active Expired - Lifetime
- 1991-09-20 KR KR1019910016470A patent/KR950010287B1/ko not_active IP Right Cessation
- 1991-11-14 JP JP3326331A patent/JPH073813B2/ja not_active Expired - Lifetime
-
1992
- 1992-04-22 US US07/873,484 patent/US5304501A/en not_active Expired - Lifetime
-
1993
- 1993-10-01 US US08/130,249 patent/US5336625A/en not_active Expired - Lifetime
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
DE10008032A1 (de) * | 2000-02-15 | 2001-09-13 | Infineon Technologies Ag | Verfahren zum Herstellen eines CMOS-kompatiblen Photosensors |
DE10008032B4 (de) * | 2000-02-15 | 2004-03-04 | Infineon Technologies Ag | Verfahren zum Herstellen eines CMOS-kompatiblen Photosensors |
DE10066181B4 (de) * | 2000-02-15 | 2011-12-01 | Infineon Technologies Ag | Verfahren zum Herstellen eines Photosensors |
Also Published As
Publication number | Publication date |
---|---|
JPH073813B2 (ja) | 1995-01-18 |
JPH04286154A (ja) | 1992-10-12 |
KR950010287B1 (ko) | 1995-09-12 |
EP0486134A1 (de) | 1992-05-20 |
EP0768709A3 (de) | 1998-08-26 |
DE69133446D1 (de) | 2005-03-24 |
KR920010894A (ko) | 1992-06-27 |
US5336625A (en) | 1994-08-09 |
EP0768709B1 (de) | 2005-02-16 |
EP0768709A2 (de) | 1997-04-16 |
EP0486134B1 (de) | 1997-06-18 |
US5304501A (en) | 1994-04-19 |
DE69126596D1 (de) | 1997-07-24 |
DE69133446T2 (de) | 2006-02-09 |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
8364 | No opposition during term of opposition |