DE69123870T2 - Sputterverfahren zum Bilden von einer Aluminiumschicht auf einen gestuften Wafer - Google Patents

Sputterverfahren zum Bilden von einer Aluminiumschicht auf einen gestuften Wafer

Info

Publication number
DE69123870T2
DE69123870T2 DE69123870T DE69123870T DE69123870T2 DE 69123870 T2 DE69123870 T2 DE 69123870T2 DE 69123870 T DE69123870 T DE 69123870T DE 69123870 T DE69123870 T DE 69123870T DE 69123870 T2 DE69123870 T2 DE 69123870T2
Authority
DE
Germany
Prior art keywords
forming
aluminum layer
sputtering process
stepped wafer
stepped
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE69123870T
Other languages
English (en)
Other versions
DE69123870D1 (de
Inventor
Chien-Rhone Wang
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Applied Materials Inc
Original Assignee
Applied Materials Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Applied Materials Inc filed Critical Applied Materials Inc
Application granted granted Critical
Publication of DE69123870D1 publication Critical patent/DE69123870D1/de
Publication of DE69123870T2 publication Critical patent/DE69123870T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/7684Smoothing; Planarisation
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/283Deposition of conductive or insulating materials for electrodes conducting electric current
    • H01L21/285Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation
    • H01L21/28506Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers
    • H01L21/28512Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic System
    • H01L21/2855Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic System by physical means, e.g. sputtering, evaporation
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76877Filling of holes, grooves or trenches, e.g. vias, with conductive material
DE69123870T 1990-03-30 1991-03-21 Sputterverfahren zum Bilden von einer Aluminiumschicht auf einen gestuften Wafer Expired - Fee Related DE69123870T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US07/502,362 US5108570A (en) 1990-03-30 1990-03-30 Multistep sputtering process for forming aluminum layer over stepped semiconductor wafer

Publications (2)

Publication Number Publication Date
DE69123870D1 DE69123870D1 (de) 1997-02-13
DE69123870T2 true DE69123870T2 (de) 1997-05-22

Family

ID=23997467

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69123870T Expired - Fee Related DE69123870T2 (de) 1990-03-30 1991-03-21 Sputterverfahren zum Bilden von einer Aluminiumschicht auf einen gestuften Wafer

Country Status (5)

Country Link
US (1) US5108570A (de)
EP (1) EP0451571B1 (de)
KR (1) KR100227236B1 (de)
DE (1) DE69123870T2 (de)
ES (1) ES2098279T3 (de)

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Also Published As

Publication number Publication date
ES2098279T3 (es) 1997-05-01
KR100227236B1 (ko) 1999-11-01
US5108570A (en) 1992-04-28
EP0451571A3 (en) 1992-07-22
EP0451571B1 (de) 1997-01-02
DE69123870D1 (de) 1997-02-13
EP0451571A2 (de) 1991-10-16

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Legal Events

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8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee