DE69115856T2 - Gegossenes Gehäuse für eine integrierte Schaltung mit einer Vorrichtung zur Reduzierung der dynamischen Impedanz - Google Patents

Gegossenes Gehäuse für eine integrierte Schaltung mit einer Vorrichtung zur Reduzierung der dynamischen Impedanz

Info

Publication number
DE69115856T2
DE69115856T2 DE69115856T DE69115856T DE69115856T2 DE 69115856 T2 DE69115856 T2 DE 69115856T2 DE 69115856 T DE69115856 T DE 69115856T DE 69115856 T DE69115856 T DE 69115856T DE 69115856 T2 DE69115856 T2 DE 69115856T2
Authority
DE
Germany
Prior art keywords
reducing
integrated circuit
dynamic impedance
cast housing
cast
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE69115856T
Other languages
English (en)
Other versions
DE69115856D1 (de
Inventor
Michel Mermet-Guyennet
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
STMicroelectronics SA
Original Assignee
SGS Thomson Microelectronics SA
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by SGS Thomson Microelectronics SA filed Critical SGS Thomson Microelectronics SA
Application granted granted Critical
Publication of DE69115856D1 publication Critical patent/DE69115856D1/de
Publication of DE69115856T2 publication Critical patent/DE69115856T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49589—Capacitor integral with or on the leadframe
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49517—Additional leads
    • H01L23/49527—Additional leads the additional leads being a multilayer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/4912—Layout
    • H01L2224/49171—Fan-out arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/1901—Structure
    • H01L2924/1904—Component type
    • H01L2924/19041—Component type being a capacitor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/301—Electrical effects
    • H01L2924/30107—Inductance
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/301—Electrical effects
    • H01L2924/3011—Impedance
DE69115856T 1990-10-29 1991-10-25 Gegossenes Gehäuse für eine integrierte Schaltung mit einer Vorrichtung zur Reduzierung der dynamischen Impedanz Expired - Fee Related DE69115856T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
FR9013741A FR2668651A1 (fr) 1990-10-29 1990-10-29 Circuit integre a boitier moule comprenant un dispositif de reduction de l'impedance dynamique.

Publications (2)

Publication Number Publication Date
DE69115856D1 DE69115856D1 (de) 1996-02-08
DE69115856T2 true DE69115856T2 (de) 1996-08-14

Family

ID=9401896

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69115856T Expired - Fee Related DE69115856T2 (de) 1990-10-29 1991-10-25 Gegossenes Gehäuse für eine integrierte Schaltung mit einer Vorrichtung zur Reduzierung der dynamischen Impedanz

Country Status (5)

Country Link
US (1) US5243496A (de)
EP (1) EP0484257B1 (de)
JP (1) JPH04266056A (de)
DE (1) DE69115856T2 (de)
FR (1) FR2668651A1 (de)

Families Citing this family (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH06507275A (ja) * 1992-02-18 1994-08-11 インテル コーポレーション 薄膜法を用いた多層成形プラスチックパッケージ
US5905300A (en) * 1994-03-31 1999-05-18 Vlsi Technology, Inc. Reinforced leadframe to substrate attachment
WO1997029512A1 (de) * 1996-02-09 1997-08-14 Mci Computer Gmbh Halbleiterelement mit einem kondensator
US6069403A (en) * 1998-10-06 2000-05-30 Intersil Corporation Power module with lowered inductance and reduced voltage overshoots
DE10014382A1 (de) * 2000-03-23 2001-10-18 Infineon Technologies Ag Leiterbahn-Schichtstruktur und Vorstufe zu dieser
JP3615126B2 (ja) 2000-07-11 2005-01-26 寛治 大塚 半導体回路装置
US6320757B1 (en) * 2000-07-12 2001-11-20 Advanced Semiconductor Engineering, Inc. Electronic package
DE10057494A1 (de) * 2000-11-20 2002-06-13 Siemens Ag Anordnung auf einem Schaltungsträger und einer Leiterplatte oder einer Leiterplattenanordnung
TW488054B (en) * 2001-06-22 2002-05-21 Advanced Semiconductor Eng Semiconductor package for integrating surface mount devices

Family Cites Families (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6018145B2 (ja) * 1980-09-22 1985-05-09 株式会社日立製作所 樹脂封止型半導体装置
JPS61108160A (ja) * 1984-11-01 1986-05-26 Nec Corp コンデンサ内蔵型半導体装置及びその製造方法
JPS6392047A (ja) * 1986-10-06 1988-04-22 Rohm Co Ltd 半導体用リ−ドフレ−ム
JPS63122159A (ja) * 1986-11-10 1988-05-26 Nec Corp 半導体装置
US4993148A (en) * 1987-05-19 1991-02-19 Mitsubishi Denki Kabushiki Kaisha Method of manufacturing a circuit board
US4903113A (en) * 1988-01-15 1990-02-20 International Business Machines Corporation Enhanced tab package
JPH0687484B2 (ja) * 1989-04-06 1994-11-02 三菱電機株式会社 Ｉｃカード用モジュール
JPH063819B2 (ja) * 1989-04-17 1994-01-12 セイコーエプソン株式会社 半導体装置の実装構造および実装方法
JP2799472B2 (ja) * 1990-05-31 1998-09-17 イビデン株式会社 電子部品搭載用基板
US5175397A (en) * 1990-12-24 1992-12-29 Westinghouse Electric Corp. Integrated circuit chip package
KR940007649B1 (ko) * 1991-04-03 1994-08-22 삼성전자 주식회사 반도체 패키지

Also Published As

Publication number Publication date
EP0484257B1 (de) 1995-12-27
FR2668651A1 (fr) 1992-04-30
US5243496A (en) 1993-09-07
JPH04266056A (ja) 1992-09-22
EP0484257A1 (de) 1992-05-06
DE69115856D1 (de) 1996-02-08

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee