DE69034129D1 - Selektive und nicht-selektive Ablagerung von Si1-x Gex auf einem mit SiO2 teilweise beschichteten Si-Wafern - Google Patents

Selektive und nicht-selektive Ablagerung von Si1-x Gex auf einem mit SiO2 teilweise beschichteten Si-Wafern

Info

Publication number
DE69034129D1
DE69034129D1 DE69034129T DE69034129T DE69034129D1 DE 69034129 D1 DE69034129 D1 DE 69034129D1 DE 69034129 T DE69034129 T DE 69034129T DE 69034129 T DE69034129 T DE 69034129T DE 69034129 D1 DE69034129 D1 DE 69034129D1
Authority
DE
Germany
Prior art keywords
selective
gex
sio2
partially coated
wafer partially
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE69034129T
Other languages
English (en)
Other versions
DE69034129T2 (de
Inventor
Theodore I Kamins
David B Noble
July L Hoyt
James F Gibbons
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hewlett Packard Development Co LP
Original Assignee
Hewlett Packard Co
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hewlett Packard Co filed Critical Hewlett Packard Co
Publication of DE69034129D1 publication Critical patent/DE69034129D1/de
Application granted granted Critical
Publication of DE69034129T2 publication Critical patent/DE69034129T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02367—Substrates
    • H01L21/0237—Materials
    • H01L21/02373—Group 14 semiconducting materials
    • H01L21/02381—Silicon, silicon germanium, germanium
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02367—Substrates
    • H01L21/0237—Materials
    • H01L21/02387—Group 13/15 materials
    • H01L21/02395—Arsenides
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02518—Deposited layers
    • H01L21/02521—Materials
    • H01L21/02524—Group 14 semiconducting materials
    • H01L21/02532—Silicon, silicon germanium, germanium
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02612—Formation types
    • H01L21/02617—Deposition types
    • H01L21/0262—Reduction or decomposition of gaseous compounds, e.g. CVD
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02612—Formation types
    • H01L21/02617—Deposition types
    • H01L21/02636—Selective deposition, e.g. simultaneous growth of mono- and non-monocrystalline semiconductor materials
    • H01L21/02639—Preparation of substrate for selective deposition
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00—Metal treatment
    • Y10S148/026—Deposition thru hole in mask
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S438/00—Semiconductor device manufacturing: process
    • Y10S438/942—Masking
DE69034129T 1989-12-01 1990-11-30 Selektive und nicht-selektive Ablagerung von Si1-x Gex auf einem mit SiO2 teilweise beschichteten Si-Wafern Expired - Fee Related DE69034129T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US07/444,464 US5202284A (en) 1989-12-01 1989-12-01 Selective and non-selective deposition of Si1-x Gex on a Si subsrate that is partially masked with SiO2

Publications (2)

Publication Number Publication Date
DE69034129D1 true DE69034129D1 (de) 2004-04-01
DE69034129T2 DE69034129T2 (de) 2004-10-07

Family

ID=23765007

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69034129T Expired - Fee Related DE69034129T2 (de) 1989-12-01 1990-11-30 Selektive und nicht-selektive Ablagerung von Si1-x Gex auf einem mit SiO2 teilweise beschichteten Si-Wafern

Country Status (4)

Country Link
US (1) US5202284A (de)
EP (1) EP0430280B1 (de)
JP (1) JP3218472B2 (de)
DE (1) DE69034129T2 (de)

Families Citing this family (58)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5633179A (en) * 1989-12-01 1997-05-27 Kamins; Theodore I. Method of forming silicon/silicon-germanium heterojunction bipolar transistor
JPH04162431A (ja) * 1990-10-24 1992-06-05 Fujitsu Ltd 半導体装置の製造方法
US5266813A (en) * 1992-01-24 1993-11-30 International Business Machines Corporation Isolation technique for silicon germanium devices
US5273930A (en) * 1992-09-03 1993-12-28 Motorola, Inc. Method of forming a non-selective silicon-germanium epitaxial film
US5293050A (en) * 1993-03-25 1994-03-08 International Business Machines Corporation Semiconductor quantum dot light emitting/detecting devices
JP3274246B2 (ja) * 1993-08-23 2002-04-15 コマツ電子金属株式会社 エピタキシャルウェーハの製造方法
EP0800705B1 (de) * 1995-10-20 2000-07-12 Koninklijke Philips Electronics N.V. Herstellung einer halbleitereinrichtung mit einer selektiv abgeschiedenen halbleiterzone
US5893949A (en) * 1995-12-26 1999-04-13 Xerox Corporation Solid phase epitaxial crystallization of amorphous silicon films on insulating substrates
DE19615291C2 (de) * 1996-04-18 1999-07-22 Inst Halbleiterphysik Gmbh Verfahren zum selektiven epitaktischen Wachstum von Si oder Si¶1¶-¶x¶Ge¶x¶ auf strukturierten Si(113)-Oberflächen
US6063670A (en) * 1997-04-30 2000-05-16 Texas Instruments Incorporated Gate fabrication processes for split-gate transistors
KR100400808B1 (ko) * 1997-06-24 2003-10-08 매사츄세츠 인스티튜트 오브 테크놀러지 그레이드된 ＧｅＳｉ층 및 평탄화를 사용한 Ｓｉ상의 Ｇｅ의 쓰레딩 전위 밀도 제어
US7227176B2 (en) * 1998-04-10 2007-06-05 Massachusetts Institute Of Technology Etch stop layer system
DE19845792A1 (de) * 1998-09-21 2000-03-23 Inst Halbleiterphysik Gmbh Verfahren zur Erzeugung einer amorphen oder polykristallinen Schicht auf einem Isolatorgebiet
DE19845787A1 (de) * 1998-09-21 2000-03-23 Inst Halbleiterphysik Gmbh Bipolartransistor und Verfahren zu seiner Herstellung
US6602613B1 (en) 2000-01-20 2003-08-05 Amberwave Systems Corporation Heterointegration of materials using deposition and bonding
US6503773B2 (en) * 2000-01-20 2003-01-07 Amberwave Systems Corporation Low threading dislocation density relaxed mismatched epilayers without high temperature growth
US6750130B1 (en) 2000-01-20 2004-06-15 Amberwave Systems Corporation Heterointegration of materials using deposition and bonding
US6596377B1 (en) * 2000-03-27 2003-07-22 Science & Technology Corporation @ Unm Thin film product and method of forming
WO2002015244A2 (en) * 2000-08-16 2002-02-21 Massachusetts Institute Of Technology Process for producing semiconductor article using graded expitaxial growth
US6649480B2 (en) * 2000-12-04 2003-11-18 Amberwave Systems Corporation Method of fabricating CMOS inverter and integrated circuits utilizing strained silicon surface channel MOSFETs
US20020100942A1 (en) * 2000-12-04 2002-08-01 Fitzgerald Eugene A. CMOS inverter and integrated circuits utilizing strained silicon surface channel MOSFETs
US6724008B2 (en) 2001-03-02 2004-04-20 Amberwave Systems Corporation Relaxed silicon germanium platform for high speed CMOS electronics and high speed analog circuits
US6830976B2 (en) * 2001-03-02 2004-12-14 Amberwave Systems Corproation Relaxed silicon germanium platform for high speed CMOS electronics and high speed analog circuits
US6723661B2 (en) * 2001-03-02 2004-04-20 Amberwave Systems Corporation Relaxed silicon germanium platform for high speed CMOS electronics and high speed analog circuits
US6703688B1 (en) 2001-03-02 2004-03-09 Amberwave Systems Corporation Relaxed silicon germanium platform for high speed CMOS electronics and high speed analog circuits
US6660607B2 (en) 2001-03-30 2003-12-09 International Business Machines Corporation Method for fabricating heterojunction bipolar transistors
WO2002082514A1 (en) * 2001-04-04 2002-10-17 Massachusetts Institute Of Technology A method for semiconductor device fabrication
TW560102B (en) * 2001-09-12 2003-11-01 Itn Energy Systems Inc Thin-film electrochemical devices on fibrous or ribbon-like substrates and methd for their manufacture and design
WO2003022564A1 (en) * 2001-09-12 2003-03-20 Itn Energy Systems, Inc. Apparatus and method for the design and manufacture of multifunctional composite materials with power integration
US20030059526A1 (en) * 2001-09-12 2003-03-27 Benson Martin H. Apparatus and method for the design and manufacture of patterned multilayer thin films and devices on fibrous or ribbon-like substrates
US6831292B2 (en) * 2001-09-21 2004-12-14 Amberwave Systems Corporation Semiconductor structures employing strained material layers with defined impurity gradients and methods for fabricating same
US6933518B2 (en) 2001-09-24 2005-08-23 Amberwave Systems Corporation RF circuits including transistors having strained material layers
US6730588B1 (en) * 2001-12-20 2004-05-04 Lsi Logic Corporation Method of forming SiGe gate electrode
AU2003222003A1 (en) 2002-03-14 2003-09-29 Amberwave Systems Corporation Methods for fabricating strained layers on semiconductor substrates
US7615829B2 (en) * 2002-06-07 2009-11-10 Amberwave Systems Corporation Elevated source and drain elements for strained-channel heterojuntion field-effect transistors
US7307273B2 (en) * 2002-06-07 2007-12-11 Amberwave Systems Corporation Control of strain in device layers by selective relaxation
US20030227057A1 (en) * 2002-06-07 2003-12-11 Lochtefeld Anthony J. Strained-semiconductor-on-insulator device structures
US7074623B2 (en) * 2002-06-07 2006-07-11 Amberwave Systems Corporation Methods of forming strained-semiconductor-on-insulator finFET device structures
US6995430B2 (en) * 2002-06-07 2006-02-07 Amberwave Systems Corporation Strained-semiconductor-on-insulator device structures
US7335545B2 (en) * 2002-06-07 2008-02-26 Amberwave Systems Corporation Control of strain in device layers by prevention of relaxation
US6946371B2 (en) * 2002-06-10 2005-09-20 Amberwave Systems Corporation Methods of fabricating semiconductor structures having epitaxially grown source and drain elements
US6982474B2 (en) * 2002-06-25 2006-01-03 Amberwave Systems Corporation Reacted conductive gate electrodes
US7375385B2 (en) 2002-08-23 2008-05-20 Amberwave Systems Corporation Semiconductor heterostructures having reduced dislocation pile-ups
US7594967B2 (en) * 2002-08-30 2009-09-29 Amberwave Systems Corporation Reduction of dislocation pile-up formation during relaxed lattice-mismatched epitaxy
US7332417B2 (en) * 2003-01-27 2008-02-19 Amberwave Systems Corporation Semiconductor structures with structural homogeneity
EP1602125B1 (de) 2003-03-07 2019-06-26 Taiwan Semiconductor Manufacturing Company, Ltd. Verfahren zur flachen grabenisolation
US6831350B1 (en) 2003-10-02 2004-12-14 Freescale Semiconductor, Inc. Semiconductor structure with different lattice constant materials and method for forming the same
US6919258B2 (en) * 2003-10-02 2005-07-19 Freescale Semiconductor, Inc. Semiconductor device incorporating a defect controlled strained channel structure and method of making the same
US7393733B2 (en) 2004-12-01 2008-07-01 Amberwave Systems Corporation Methods of forming hybrid fin field-effect transistor structures
US20060113603A1 (en) * 2004-12-01 2006-06-01 Amberwave Systems Corporation Hybrid semiconductor-on-insulator structures and related methods
US7705385B2 (en) * 2005-09-12 2010-04-27 International Business Machines Corporation Selective deposition of germanium spacers on nitride
US8530934B2 (en) * 2005-11-07 2013-09-10 Atmel Corporation Integrated circuit structures containing a strain-compensated compound semiconductor layer and methods and systems related thereto
US7915104B1 (en) 2007-06-04 2011-03-29 The Arizona Board Of Regents, A Body Corporate Of The State Of Arizona Acting For And On Behalf Of Arizona State University Methods and compositions for preparing tensile strained Ge on Ge1-ySny buffered semiconductor substrates
US7795605B2 (en) * 2007-06-29 2010-09-14 International Business Machines Corporation Phase change material based temperature sensor
US7645666B2 (en) * 2007-07-23 2010-01-12 Infineon Technologies Ag Method of making a semiconductor device
US7772097B2 (en) * 2007-11-05 2010-08-10 Asm America, Inc. Methods of selectively depositing silicon-containing films
US20110045646A1 (en) * 2008-04-02 2011-02-24 Arizona Board Of Regents Selective deposition of sige layers from single source of si-ge hydrides
US8642407B2 (en) 2010-11-04 2014-02-04 International Business Machines Corporation Devices having reduced susceptibility to soft-error effects and method for fabrication

Family Cites Families (23)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4274891A (en) * 1979-06-29 1981-06-23 International Business Machines Corporation Method of fabricating buried injector memory cell formed from vertical complementary bipolar transistor circuits utilizing mono-poly deposition
JPS5687339A (en) * 1979-12-18 1981-07-15 Nec Corp Manufacture of semiconductor device
US4727047A (en) * 1980-04-10 1988-02-23 Massachusetts Institute Of Technology Method of producing sheets of crystalline material
JPS595644A (ja) * 1982-07-01 1984-01-12 Fujitsu Ltd 半導体装置の製造方法
JPS59134819A (ja) * 1982-09-03 1984-08-02 Nec Corp 半導体基板の製造方法
JPS59147471A (ja) * 1983-02-10 1984-08-23 Agency Of Ind Science & Technol ジヨセフソン論理集積回路
JPS59222923A (ja) * 1983-06-02 1984-12-14 Nec Corp 半導体基板の製造方法
JPS59225516A (ja) * 1983-06-06 1984-12-18 Sony Corp 半導体装置の製法
JPS60716A (ja) * 1983-06-16 1985-01-05 Tdk Corp アモルフアスカツトコア
JPS6016420A (ja) * 1983-07-08 1985-01-28 Mitsubishi Electric Corp 選択的エピタキシヤル成長方法
JPS6057964A (ja) * 1983-09-09 1985-04-03 Matsushita Electronics Corp 固体光電変換装置およびその製造方法
US4529455A (en) * 1983-10-28 1985-07-16 At&T Bell Laboratories Method for epitaxially growing Gex Si1-x layers on Si utilizing molecular beam epitaxy
JPS60193324A (ja) * 1984-03-15 1985-10-01 Nec Corp 半導体基板の製造方法
JPS60257541A (ja) * 1984-06-04 1985-12-19 Mitsubishi Electric Corp 半導体装置の製造方法
JPS6119118A (ja) * 1984-07-05 1986-01-28 Nec Corp 半導体基板の製造方法
JPH0715942B2 (ja) * 1986-08-25 1995-02-22 日本電気株式会社 集積回路基板の製造方法
JPS6358921A (ja) * 1986-08-29 1988-03-14 Fujitsu Ltd 半導体装置の製造方法
KR900007686B1 (ko) * 1986-10-08 1990-10-18 후지쓰 가부시끼가이샤 선택적으로 산화된 실리콘 기판상에 에피택셜 실리콘층과 다결정 실리콘층을 동시에 성장시키는 기상 증착방법
US4876210A (en) * 1987-04-30 1989-10-24 The University Of Delaware Solution growth of lattice mismatched and solubility mismatched heterostructures
JP2539428B2 (ja) * 1987-05-12 1996-10-02 ソニー株式会社 高分子圧電フィルムの製造方法
US4786615A (en) * 1987-08-31 1988-11-22 Motorola Inc. Method for improved surface planarity in selective epitaxial silicon
US4910164A (en) * 1988-07-27 1990-03-20 Texas Instruments Incorporated Method of making planarized heterostructures using selective epitaxial growth
JPH02150033A (ja) * 1988-11-30 1990-06-08 Fujitsu Ltd 半導体装置およびその製造方法

Also Published As

Publication number Publication date
JP3218472B2 (ja) 2001-10-15
US5202284A (en) 1993-04-13
JPH03276716A (ja) 1991-12-06
EP0430280A3 (en) 1991-10-09
DE69034129T2 (de) 2004-10-07
EP0430280B1 (de) 2004-02-25
EP0430280A2 (de) 1991-06-05

Similar Documents

Publication Publication Date Title
DE69034129T2 (de) Selektive und nicht-selektive Ablagerung von Si1-x Gex auf einem mit SiO2 teilweise beschichteten Si-Wafern
BR8503297A (pt) Gancho de mola giratorio de resina sintetica e metodo de fabricacao do mesmo
DE3765213D1 (de) Elektrostatisches beschichtungsverfahren und vorrichtung.
DE69018846D1 (de) Keramische Packung vom Halbleiteranordnungstyp und Verfahren zum Zusammensetzen derselben.
NO895079L (no) Belegningsblanding, samt fremstilling derav.
DE68922288T3 (de) Zentrales Aktualisieren einer nutzerseitigen Datenbank
DE3786804D1 (de) Beschichtungsmethode in einer beschichtungsstrasse und beschichtungsgeraet dafuer.
BR8501764A (pt) Gancho de mola giratorio e metodo de fabricacao do mesmo
DE69232311D1 (de) Herstellungsverfahren von integrierten Vorrichtungen und so hergestellte integrierte Vorrichtung
DE69006719T2 (de) Verfahren und Einrichtung zur Kontrolle der Verbindung einer bienennestartigen Struktur auf einem Träger.
DE68925625D1 (de) Verfahren zur Rückführung von Fehlern und neuronale Netzstruktur
DE68914927T2 (de) Halbleiteranordnung vom mit Plastik umhüllten Typ und Verfahren zur Herstellung derselben.
BR8903812A (pt) Transitor bipolar e metodo de formacao do mesmo
NO892542L (no) Fremgangsmaate for fremstilling av neurokinin a antagonister.
BR8802762A (pt) Copolimero de poliacetal contendo silicio e processo de sua manufatura
DE69010794D1 (de) Fluorborsilikatglas und beschichteter Gegenstand.
ATE132871T1 (de) Bis-arylphosphatester-antagonisten vom thrombocyten aktivierenden faktor
DK200588A (da) Thiophenforbindelser samt fremstillingen deraf
DK160089D0 (da) Blodpladeaktiverende faktor (paf)-antagonister samt fremstilling deraf
FI890183A (fi) Anordning foer roerelse i en roerformad ledning.
DK114091D0 (da) Ensartet overtrukne keramiske partikler
FR2586419B1 (fr) Peinture resistive de l'ordre du megohm et resistances realisees a partir de cette peinture
DK179088D0 (da) Chlorfluorhydrocarbonmaterialer samt anvendelse deraf
KR900011535A (ko) 다이어몬드 피복부재 및 그 제조방법
RO94494A2 (ro) Dispozitiv de actionare de verificare si limitare a sarcinilor pentrumacarale

Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8327 Change in the person/name/address of the patent owner

Owner name: HEWLETT-PACKARD DEVELOPMENT CO., L.P., HOUSTON, TE

8339 Ceased/non-payment of the annual fee