DE69029648D1 - Hochleistungsschnittstelle für anteilig genutzten Hauptspeicher - Google Patents

Hochleistungsschnittstelle für anteilig genutzten Hauptspeicher

Info

Publication number
DE69029648D1
DE69029648D1 DE69029648T DE69029648T DE69029648D1 DE 69029648 D1 DE69029648 D1 DE 69029648D1 DE 69029648 T DE69029648 T DE 69029648T DE 69029648 T DE69029648 T DE 69029648T DE 69029648 D1 DE69029648 D1 DE 69029648D1
Authority
DE
Germany
Prior art keywords
main memory
performance interface
shared main
shared
interface
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE69029648T
Other languages
English (en)
Other versions
DE69029648T2 (de
Inventor
Richard Glenn Eikill
Sheldon Bernard Levenstein
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
International Business Machines Corp
Original Assignee
International Business Machines Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by International Business Machines Corp filed Critical International Business Machines Corp
Application granted granted Critical
Publication of DE69029648D1 publication Critical patent/DE69029648D1/de
Publication of DE69029648T2 publication Critical patent/DE69029648T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00—Digital computers in general; Data processing equipment in general
    • G06F15/16—Combinations of two or more digital computers each having at least an arithmetic unit, a program unit and a register, e.g. for a simultaneous processing of several programs
    • G06F15/163—Interprocessor communication
    • G06F15/17—Interprocessor communication using an input/output type connection, e.g. channel, I/O port
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/36—Handling requests for interconnection or transfer for access to common bus or bus system
    • G06F13/368—Handling requests for interconnection or transfer for access to common bus or bus system with decentralised access control

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Software Systems (AREA)
  • Bus Control (AREA)
  • Multi Processors (AREA)
DE69029648T 1989-12-04 1990-10-31 Hochleistungsschnittstelle für anteilig genutzten Hauptspeicher Expired - Fee Related DE69029648T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US07/445,320 US5131085A (en) 1989-12-04 1989-12-04 High performance shared main storage interface

Publications (2)

Publication Number Publication Date
DE69029648D1 true DE69029648D1 (de) 1997-02-20
DE69029648T2 DE69029648T2 (de) 1997-07-17

Family

ID=23768465

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69029648T Expired - Fee Related DE69029648T2 (de) 1989-12-04 1990-10-31 Hochleistungsschnittstelle für anteilig genutzten Hauptspeicher

Country Status (4)

Country Link
US (1) US5131085A (de)
EP (1) EP0432076B1 (de)
JP (1) JPH0619754B2 (de)
DE (1) DE69029648T2 (de)

Families Citing this family (26)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5276809A (en) * 1990-06-26 1994-01-04 Digital Equipment Corporation Method and apparatus for capturing real-time data bus cycles in a data processing system
US5339397A (en) * 1990-10-12 1994-08-16 International Business Machines Corporation Hardware primary directory lock
US5257356A (en) * 1991-05-28 1993-10-26 Hewlett-Packard Company Method of reducing wasted bus bandwidth due to slow responding slaves in a multiprocessor computer system
US5953510A (en) * 1991-09-05 1999-09-14 International Business Machines Corporation Bidirectional data bus reservation priority controls having token logic
US5422885A (en) * 1992-06-01 1995-06-06 Motorola, Inc. Contention free local area network
DE4317567A1 (de) * 1993-05-26 1994-12-01 Siemens Ag Verfahren zum Betreiben eines Bussystems sowie Anordnung zur Durchführung des Verfahrens
US5469435A (en) * 1994-01-25 1995-11-21 Apple Computer, Inc. Bus deadlock avoidance during master split-transactions
US5572687A (en) * 1994-04-22 1996-11-05 The University Of British Columbia Method and apparatus for priority arbitration among devices in a computer system
US5717931A (en) * 1994-12-20 1998-02-10 Motorola, Inc. Method and apparatus for communicating between master and slave electronic devices where the slave device may be hazardous
US6199133B1 (en) * 1996-03-29 2001-03-06 Compaq Computer Corporation Management communication bus for networking devices
US6081860A (en) * 1997-11-20 2000-06-27 International Business Machines Corporation Address pipelining for data transfers
US6185646B1 (en) * 1997-12-03 2001-02-06 International Business Machines Corporation Method and apparatus for transferring data on a synchronous multi-drop
AU6495299A (en) * 1998-09-18 2000-04-10 Computron Multiple operating system controller for a computer
US6658552B1 (en) * 1998-10-23 2003-12-02 Micron Technology, Inc. Processing system with separate general purpose execution unit and data string manipulation unit
US6684279B1 (en) * 1999-11-08 2004-01-27 International Business Machines Corporation Method, apparatus, and computer program product for controlling data transfer
US20020178283A1 (en) * 2001-03-29 2002-11-28 Pelco, A Partnership Real-time networking protocol
US7007121B1 (en) * 2002-02-27 2006-02-28 Xilinx, Inc. Method and apparatus for synchronized buses
US6934782B2 (en) * 2002-12-23 2005-08-23 Lsi Logic Corporation Process and apparatus for managing use of a peripheral bus among a plurality of controllers
WO2007113801A2 (en) * 2006-03-30 2007-10-11 Given Imaging Ltd. In-vivo sensing device and method for communicating between imagers and processor thereof
US8935336B2 (en) * 2008-06-18 2015-01-13 Cisco Technology, Inc. Optimizing program requests over a wide area network
KR101611157B1 (ko) * 2009-11-24 2016-04-11 삼성전자 주식회사 공기조화기 및 그 통신방법
WO2013137023A1 (ja) * 2012-03-15 2013-09-19 オムロン株式会社 制御装置、情報処理装置、制御方法、コンピュータ読取可能な記録媒体、およびプログラム
WO2014070779A1 (en) * 2012-10-30 2014-05-08 Anayas360.Com, Llc. Address based serial communication interface for control and monitoring of system-on-chip implementations
US9213660B2 (en) * 2013-06-14 2015-12-15 Arm Limited Receiver based communication permission token allocation
US9665707B2 (en) * 2015-01-09 2017-05-30 GM Global Technology Operations LLC Systems and methods for cyber security of intra-vehicular peripherals powered by wire
DE102017117288A1 (de) * 2017-07-31 2019-01-31 Hengstler Gmbh Datenübertragungsverfahren zwischen einem Drehwinkelgeber und einer Motorsteuereinrichtung oder einer Auswerteeinheit

Family Cites Families (17)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4223380A (en) * 1978-04-06 1980-09-16 Ncr Corporation Distributed multiprocessor communication system
FR2474199B1 (fr) * 1980-01-21 1986-05-16 Bull Sa Dispositif pour superposer les phases successives du transfert des informations entre plusieurs unites d'un systeme de traitement de l'information
US4314335A (en) * 1980-02-06 1982-02-02 The Perkin-Elmer Corporation Multilevel priority arbiter
US4375639A (en) * 1981-01-12 1983-03-01 Harris Corporation Synchronous bus arbiter
CA1179069A (en) * 1981-04-10 1984-12-04 Yasushi Fukunaga Data transmission apparatus for a multiprocessor system
US4481572A (en) * 1981-10-13 1984-11-06 Teledyne Industries, Inc. Multiconfigural computers utilizing a time-shared bus
US4504906A (en) * 1982-11-30 1985-03-12 Anritsu Electric Company Limited Multiprocessor system
US4698746A (en) * 1983-05-25 1987-10-06 Ramtek Corporation Multiprocessor communication method and apparatus
JPS60107170A (ja) * 1983-11-15 1985-06-12 Nec Corp マルチプロセッサ制御方式
JPS60129872A (ja) * 1983-12-19 1985-07-11 Toshiba Corp デ−タの分散処理装置
US4561051A (en) * 1984-02-10 1985-12-24 Prime Computer, Inc. Memory access method and apparatus in multiple processor systems
US4633394A (en) * 1984-04-24 1986-12-30 International Business Machines Corp. Distributed arbitration for multiple processors
US4639859A (en) * 1984-05-24 1987-01-27 Rca Corporation Priority arbitration logic for a multi-master bus system
US4719622A (en) * 1985-03-15 1988-01-12 Wang Laboratories, Inc. System bus means for inter-processor communication
US4730268A (en) * 1985-04-30 1988-03-08 Texas Instruments Incorporated Distributed bus arbitration for a multiprocessor system
US4803617A (en) * 1986-02-10 1989-02-07 Eastman Kodak Company Multi-processor using shared buses
WO1987004826A1 (en) * 1986-02-10 1987-08-13 Eastman Kodak Company Multi-processor apparatus

Also Published As

Publication number Publication date
EP0432076B1 (de) 1997-01-08
DE69029648T2 (de) 1997-07-17
EP0432076A2 (de) 1991-06-12
EP0432076A3 (en) 1993-09-29
JPH0619754B2 (ja) 1994-03-16
US5131085A (en) 1992-07-14
JPH03214343A (ja) 1991-09-19

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee