DE69027576D1 - Eeprom mit grabenisolierten Bitleitungen - Google Patents
Eeprom mit grabenisolierten BitleitungenInfo
- Publication number
- DE69027576D1 DE69027576D1 DE69027576T DE69027576T DE69027576D1 DE 69027576 D1 DE69027576 D1 DE 69027576D1 DE 69027576 T DE69027576 T DE 69027576T DE 69027576 T DE69027576 T DE 69027576T DE 69027576 D1 DE69027576 D1 DE 69027576D1
- Authority
- DE
- Germany
- Prior art keywords
- trench
- eeprom
- bit lines
- insulated bit
- insulated
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/76202—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/788—Field effect transistors with field effect produced by an insulated gate with floating gate
- H01L29/7881—Programmable transistors with only two possible levels of programmation
- H01L29/7883—Programmable transistors with only two possible levels of programmation charging by tunnelling of carriers, e.g. Fowler-Nordheim tunnelling
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B69/00—Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US07/439,766 US5051795A (en) | 1989-11-21 | 1989-11-21 | EEPROM with trench-isolated bitlines |
Publications (2)
Publication Number | Publication Date |
---|---|
DE69027576D1 true DE69027576D1 (de) | 1996-08-01 |
DE69027576T2 DE69027576T2 (de) | 1996-10-31 |
Family
ID=23746058
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
DE69027576T Expired - Fee Related DE69027576T2 (de) | 1989-11-21 | 1990-10-10 | Eeprom mit grabenisolierten Bitleitungen |
Country Status (4)
Country | Link |
---|---|
US (1) | US5051795A (de) |
EP (1) | EP0428857B1 (de) |
JP (1) | JP3066064B2 (de) |
DE (1) | DE69027576T2 (de) |
Families Citing this family (19)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR970000533B1 (ko) * | 1990-12-20 | 1997-01-13 | 후지쓰 가부시끼가이샤 | Eprom 및 그 제조방법 |
JP2655765B2 (ja) * | 1991-05-29 | 1997-09-24 | ローム株式会社 | 半導体装置 |
US5110756A (en) * | 1991-07-03 | 1992-05-05 | At&T Bell Laboratories | Method of semiconductor integrated circuit manufacturing which includes processing for reducing defect density |
US5618742A (en) * | 1992-01-22 | 1997-04-08 | Macronix Internatioal, Ltd. | Method of making flash EPROM with conductive sidewall spacer contacting floating gate |
US5412238A (en) * | 1992-09-08 | 1995-05-02 | National Semiconductor Corporation | Source-coupling, split-gate, virtual ground flash EEPROM array |
US5379255A (en) * | 1992-12-14 | 1995-01-03 | Texas Instruments Incorporated | Three dimensional famos memory devices and methods of fabricating |
JPH07161845A (ja) * | 1993-12-02 | 1995-06-23 | Nec Corp | 半導体不揮発性記憶装置 |
EP0728367B1 (de) * | 1994-09-13 | 2003-05-07 | Macronix International Co., Ltd. | Flash-eprom-transistoren-matrix und verfahren zur herstellung |
US5703387A (en) * | 1994-09-30 | 1997-12-30 | United Microelectronics Corp. | Split gate memory cell with vertical floating gate |
US5834358A (en) * | 1996-11-12 | 1998-11-10 | Micron Technology, Inc. | Isolation regions and methods of forming isolation regions |
US6060358A (en) * | 1997-10-21 | 2000-05-09 | International Business Machines Corporation | Damascene NVRAM cell and method of manufacture |
JP3921773B2 (ja) * | 1998-01-26 | 2007-05-30 | ソニー株式会社 | 再生装置 |
US6093946A (en) * | 1998-02-20 | 2000-07-25 | Vantis Corporation | EEPROM cell with field-edgeless tunnel window using shallow trench isolation process |
US6175147B1 (en) * | 1998-05-14 | 2001-01-16 | Micron Technology Inc. | Device isolation for semiconductor devices |
JP2001168306A (ja) * | 1999-12-09 | 2001-06-22 | Toshiba Corp | 不揮発性半導体記憶装置及びその製造方法 |
JP2001230390A (ja) * | 2000-02-17 | 2001-08-24 | Mitsubishi Electric Corp | 半導体不揮発性記憶装置およびその製造法 |
US6448606B1 (en) * | 2000-02-24 | 2002-09-10 | Advanced Micro Devices, Inc. | Semiconductor with increased gate coupling coefficient |
JP2002359308A (ja) * | 2001-06-01 | 2002-12-13 | Toshiba Corp | 半導体記憶装置及びその製造方法 |
KR100549320B1 (ko) * | 2002-02-21 | 2006-02-02 | 마츠시타 덴끼 산교 가부시키가이샤 | 반도체기억장치 및 그 제조방법 |
Family Cites Families (18)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS58130571A (ja) * | 1982-01-29 | 1983-08-04 | Hitachi Ltd | 半導体装置 |
US4590504A (en) * | 1982-12-28 | 1986-05-20 | Thomson Components - Mostek Corporation | Nonvolatile MOS memory cell with tunneling element |
FR2562326B1 (fr) * | 1984-03-30 | 1987-01-23 | Bois Daniel | Procede de fabrication de zones d'isolation electrique des composants d'un circuit integre |
US4597060A (en) * | 1985-05-01 | 1986-06-24 | Texas Instruments Incorporated | EPROM array and method for fabricating |
JPS62123764A (ja) * | 1985-11-25 | 1987-06-05 | Hitachi Ltd | 半導体装置 |
JPS6231177A (ja) * | 1985-08-02 | 1987-02-10 | Nec Corp | 不揮発性半導体記憶装置 |
US4698900A (en) * | 1986-03-27 | 1987-10-13 | Texas Instruments Incorporated | Method of making a non-volatile memory having dielectric filled trenches |
US4892840A (en) * | 1986-03-27 | 1990-01-09 | Texas Instruments Incorporated | EPROM with increased floating gate/control gate coupling |
US4780424A (en) * | 1987-09-28 | 1988-10-25 | Intel Corporation | Process for fabricating electrically alterable floating gate memory devices |
JPH07120705B2 (ja) * | 1987-11-17 | 1995-12-20 | 三菱電機株式会社 | 素子間分離領域を有する半導体装置の製造方法 |
US4905062A (en) * | 1987-11-19 | 1990-02-27 | Texas Instruments Incorporated | Planar famos transistor with trench isolation |
US4853895A (en) * | 1987-11-30 | 1989-08-01 | Texas Instruments Incorporated | EEPROM including programming electrode extending through the control gate electrode |
US4835115A (en) * | 1987-12-07 | 1989-05-30 | Texas Instruments Incorporated | Method for forming oxide-capped trench isolation |
US4924437A (en) * | 1987-12-09 | 1990-05-08 | Texas Instruments Incorporated | Erasable programmable memory including buried diffusion source/drain lines and erase lines |
US4951103A (en) * | 1988-06-03 | 1990-08-21 | Texas Instruments, Incorporated | Fast, trench isolated, planar flash EEPROMS with silicided bitlines |
US4947222A (en) * | 1988-07-15 | 1990-08-07 | Texas Instruments Incorporated | Electrically programmable and erasable memory cells with field plate conductor defined drain regions |
US4912676A (en) * | 1988-08-09 | 1990-03-27 | Texas Instruments, Incorporated | Erasable programmable memory |
JPH088313B2 (ja) * | 1989-07-25 | 1996-01-29 | 株式会社東芝 | 不揮発性半導体記憶装置及びその製造方法 |
-
1989
- 1989-11-21 US US07/439,766 patent/US5051795A/en not_active Expired - Fee Related
-
1990
- 1990-10-10 EP EP90119394A patent/EP0428857B1/de not_active Expired - Lifetime
- 1990-10-10 DE DE69027576T patent/DE69027576T2/de not_active Expired - Fee Related
- 1990-11-20 JP JP2313029A patent/JP3066064B2/ja not_active Expired - Fee Related
Also Published As
Publication number | Publication date |
---|---|
EP0428857A2 (de) | 1991-05-29 |
EP0428857A3 (en) | 1992-03-18 |
DE69027576T2 (de) | 1996-10-31 |
US5051795A (en) | 1991-09-24 |
EP0428857B1 (de) | 1996-06-26 |
JP3066064B2 (ja) | 2000-07-17 |
JPH03209766A (ja) | 1991-09-12 |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
8364 | No opposition during term of opposition | ||
8339 | Ceased/non-payment of the annual fee |