DE69025888T2 - Halbleiterbauelement mit einem dielektrischen Isolierungsbereich mit der Struktur einer U-förmigen Nut - Google Patents

Halbleiterbauelement mit einem dielektrischen Isolierungsbereich mit der Struktur einer U-förmigen Nut

Info

Publication number
DE69025888T2
DE69025888T2 DE69025888T DE69025888T DE69025888T2 DE 69025888 T2 DE69025888 T2 DE 69025888T2 DE 69025888 T DE69025888 T DE 69025888T DE 69025888 T DE69025888 T DE 69025888T DE 69025888 T2 DE69025888 T2 DE 69025888T2
Authority
DE
Germany
Prior art keywords
shaped groove
isolation region
semiconductor component
dielectric isolation
dielectric
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE69025888T
Other languages
English (en)
Other versions
DE69025888D1 (de
Inventor
Shuji Kishi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Electronics Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Publication of DE69025888D1 publication Critical patent/DE69025888D1/de
Application granted granted Critical
Publication of DE69025888T2 publication Critical patent/DE69025888T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321—After treatment
    • H01L21/32105—Oxidation of silicon-containing layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/763—Polycrystalline semiconductor regions
DE69025888T 1989-12-20 1990-12-19 Halbleiterbauelement mit einem dielektrischen Isolierungsbereich mit der Struktur einer U-förmigen Nut Expired - Fee Related DE69025888T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP33205589 1989-12-20

Publications (2)

Publication Number Publication Date
DE69025888D1 DE69025888D1 (de) 1996-04-18
DE69025888T2 true DE69025888T2 (de) 1996-07-25

Family

ID=18250637

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69025888T Expired - Fee Related DE69025888T2 (de) 1989-12-20 1990-12-19 Halbleiterbauelement mit einem dielektrischen Isolierungsbereich mit der Struktur einer U-förmigen Nut

Country Status (3)

Country Link
US (1) US5148257A (de)
EP (1) EP0435550B1 (de)
DE (1) DE69025888T2 (de)

Families Citing this family (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH05152429A (ja) * 1991-11-28 1993-06-18 Nec Corp 半導体装置の製造方法
WO1996002070A2 (en) * 1994-07-12 1996-01-25 National Semiconductor Corporation Integrated circuit comprising a trench isolation structure and an oxygen barrier layer and method for forming the integrated circuit
GB2322736B (en) * 1997-02-28 2002-06-26 Int Rectifier Corp Integrated photovoltaic switch with integrated power device
US5914523A (en) * 1998-02-17 1999-06-22 National Semiconductor Corp. Semiconductor device trench isolation structure with polysilicon bias voltage contact
KR100285701B1 (ko) * 1998-06-29 2001-04-02 윤종용 트렌치격리의제조방법및그구조
DE10029036C1 (de) * 2000-06-13 2001-08-09 Infineon Technologies Ag Verfahren zur Erhöhung der Trenchkapazität
JP4618766B2 (ja) * 2003-10-01 2011-01-26 ローム株式会社 半導体デバイス
US7776708B1 (en) * 2005-08-11 2010-08-17 National Semiconductor Corporation System and method for providing a nitride cap over a polysilicon filled trench to prevent formation of a vertical bird's beak structure in the manufacture of a semiconductor device
US7863153B1 (en) 2006-07-13 2011-01-04 National Semiconductor Corporation System and method for creating different field oxide profiles in a locos process
US8461661B2 (en) * 2009-04-06 2013-06-11 Polar Semiconductor, Inc. Locos nitride capping of deep trench polysilicon fill
CN104517824B (zh) * 2014-08-01 2017-08-08 上海华虹宏力半导体制造有限公司 沟槽型双层栅的制造方法

Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0048175B1 (de) * 1980-09-17 1986-04-23 Hitachi, Ltd. Halbleiterbauelement und Verfahren zu dessen Herstellung
US4819054A (en) * 1982-09-29 1989-04-04 Hitachi, Ltd. Semiconductor IC with dual groove isolation
JPS5979548A (ja) * 1982-10-29 1984-05-08 Hitachi Ltd 誘電体分離方法
JPS59106133A (ja) * 1982-12-09 1984-06-19 Nec Corp 集積回路装置
JPS6083346A (ja) * 1983-10-14 1985-05-11 Hitachi Ltd 半導体集積回路装置
US4528047A (en) * 1984-06-25 1985-07-09 International Business Machines Corporation Method for forming a void free isolation structure utilizing etch and refill techniques
JPS6122646A (ja) * 1984-07-11 1986-01-31 Hitachi Ltd 絶縁分離溝の埋込み方法
US4656497A (en) * 1984-11-01 1987-04-07 Ncr Corporation Trench isolation structures

Also Published As

Publication number Publication date
EP0435550B1 (de) 1996-03-13
US5148257A (en) 1992-09-15
EP0435550A2 (de) 1991-07-03
DE69025888D1 (de) 1996-04-18
EP0435550A3 (de) 1991-07-24

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8327 Change in the person/name/address of the patent owner

Owner name: NEC ELECTRONICS CORP., KAWASAKI, KANAGAWA, JP

8339 Ceased/non-payment of the annual fee